JP4131344B2 - PLL circuit, demodulation circuit, IC card, and IC card processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a PLL circuit, a demodulation circuit, an IC card, and an IC card processing device, and can be applied to, for example, an IC card that inputs and outputs various data without contact, and an IC card processing device that performs data communication with the IC card. it can. The present invention selectively averages the phase comparison results of the oscillation output signal and the binarized signal to calculate a phase shift amount with respect to either the rising edge or the falling edge, and the oscillation output signal is calculated from the phase shift amount. By controlling, the control direction is determined on the basis of the positive / negative of the phase comparison result by the oscillation output signal having a phase difference of 90 degrees, and the oscillation output signal is controlled in this control direction. The input signal can be reliably processed even when the signal quality deteriorates.
[0002]
[Prior art]
Conventionally, an IC card system using an IC card is applied to a ticket gate system for transportation, a room entrance / exit management system, and the like. Such an IC card system includes an IC card carried by a user and a reader / writer (that is, an IC card processing device) that transmits and receives various data to and from these IC cards. There has been proposed one in which various data are transmitted and received between writers without contact.
[0003]
That is, in this type of IC card system, the reader / writer modulates a carrier wave having a predetermined frequency with a desired data string to generate a transmission signal, and sends the transmission signal to the IC card.
[0004]
The IC card receives this transmission signal via the antenna, and demodulates data transmitted from the reader / writer based on this transmission signal. Further, the IC card modulates data such as personal information held in the IC card with a predetermined carrier according to the received data and sends it to the reader / writer.
[0005]
The reader / writer receives data sent from the IC card, and opens / closes the door of the ticket gate and permits entry / exit of the room based on the received data.
[0006]
In such an IC card system, a demodulator as shown in FIG. 11 is used to receive data sent from a reader / writer and receive data sent from an IC card.
[0007]
That is, the demodulator 1 inputs the PSK modulation signal S1 demodulated from the antenna input to the binarization circuit 2 having a limiter circuit configuration, and binarizes the PSK modulation signal S1 here. The phase comparison circuit 3 includes an exclusive OR circuit that compares the phase of the binarized signal SA output from the binarization circuit 2 and the clock CK output from the control type oscillation circuit 4. The result is output to a low pass filter (LPF) 5. The low-pass filter 5 limits the band of the phase comparison result and generates a control signal for the control type oscillation circuit 4. The control type oscillation circuit 4 varies the oscillation frequency according to this control signal.
[0008]
As a result, the demodulator 1 generates a clock CK that forms a PLL circuit and is phase-synchronized with the binarized signal SA, and regenerates the clock CK from the PSK modulation signal. The latch circuit 6 sequentially latches the binarized signal by this clock CK, and thereby outputs a data string D1 obtained by demodulating the PSK modulation signal S1.
[0009]
[Problems to be solved by the invention]
Incidentally, in the IC card system, the antenna input varies greatly depending on the distance between the IC card and the reader / writer. Along with this, in the PSK modulation signal or the like by the Manchester code, the waveform of the PSK modulation signal S1 is remarkably deteriorated, and the S / N ratio is greatly deteriorated.
[0010]
In this case, the conventional demodulator changes the duty ratio in the binarized signal obtained by binarizing the PSK modulation signal S1, thereby correctly reproducing the clock of the PSK modulation signal S1 from the binarized signal SA. There is a problem that makes it difficult. When it becomes difficult to correctly reproduce the clock in this way, it becomes difficult to correctly reproduce the data accordingly.
[0011]
As one method for solving this problem, a method of demodulating a PSK modulated signal using a Costas loop can be considered. However, the Costas loop has a drawback that it is difficult to apply to an IC card that requires a simple configuration by processing a PSK modulated signal by analog signal processing.
[0012]
The present invention has been made in consideration of the above points. A PLL circuit, a demodulating circuit, an IC card using these, and a PLL circuit that can reliably process an input signal even when the input signal deteriorates with a simple configuration. An IC card processing device is proposed.
[0013]
[Means for Solving the Problems]
In order to solve this problem, in the present invention, in the PLL circuit, the phase comparison result between the oscillation output signal and the binarized signal is obtained. , By the rising edge of the oscillation output signal and by the falling edge of the oscillation output signal, respectively An average value is calculated, and a first phase shift amount of the binarized signal with respect to the rising edge of the oscillation output signal and a second phase shift amount of the binarized signal with respect to the falling edge of the oscillation output signal are calculated. A control signal for controlling the frequency of the oscillation output signal is output from the first or second phase shift amount, and the phase of the oscillation output signal is corrected based on the detection result of the second or first phase shift amount to generate a clock. Is output.
[0014]
In the demodulating circuit, the binary signal is sequentially latched by this clock.
[0015]
Further, in the IC card and the IC card processing device, the data string is demodulated from the transmission signal received via the antenna by the previous demodulation circuit.
[0019]
In the PLL circuit, the phase comparison result between the oscillation output signal and the binarized signal , By the rising edge of the oscillation output signal and by the falling edge of the oscillation output signal, respectively If averaging is performed and the first phase shift amount of the binarized signal with respect to the rising edge of the oscillation output signal and the second phase shift amount of the binarized signal with respect to the falling edge of the oscillation output signal are calculated, noise It is possible to calculate the first and second phase shift amounts while avoiding the influence of. If a control signal for controlling the frequency of the oscillation output signal is output from the first or second phase shift amount, the rising edge or the falling edge of the oscillation output signal can be obtained even when the duty ratio of the binarized signal changes. The oscillation output signal can be controlled so that one of the two is phase-synchronized with the binarized signal. If the phase of the oscillation output signal is corrected and the clock is output based on the detection result of the remaining second or first phase shift amount, the clock of the input signal can be reproduced.
[0020]
Accordingly, if the binarized signal is sequentially latched by this clock in the demodulation circuit, even if the input signal is deteriorated, the data transmitted by the input signal can be reliably demodulated.
[0021]
Further, in the IC card and the IC card processing device, if the data string is demodulated from the transmission signal received via the antenna by the previous demodulation circuit, the distance between the IC card and the IC card processing device changes and the transmission signal deteriorates. Even in such a case, data can be reliably received.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.
[0026]
(1) First embodiment
FIG. 2 is a block diagram showing an IC card system according to the first embodiment of the present invention. This IC card system 11 is applied to a ticket gate system for transportation, for example, and exchanges data between the IC card 12 and the reader / writer 13.
[0027]
Here, the IC card 12 is formed in a card shape by laminating a substrate on which an integrated circuit is mounted and a protective sheet. In the IC card 12, a loop antenna 14 is formed by the wiring pattern on the substrate. Also, the modem circuit 15 and the signal processing circuit 16 are formed by an integrated circuit mounted on the substrate.
[0028]
Here, the loop antenna 14 is coupled to the loop antenna 18 of the reader / writer 13 to receive the transmission signal transmitted from the loop antenna 18 and radiate the response signal generated by the modulation / demodulation circuit 15.
[0029]
The modem circuit 15 generates power, a clock, and the like necessary for the operation of the IC card 12 from the transmission signal received by the loop antenna 14. Further, the modem circuit 15 operates with this power and clock, and demodulates a data string (hereinafter referred to as a transmission data string) D (R → C) sent from the reader / writer 13 from the transmission signal to the signal processing circuit 16. Output. Further, a response signal is generated from a data string (hereinafter referred to as a response data string) D (C → R) input from the signal processing circuit 16 when transmission is prompted by the transmission data string D (R → C), and the response The response signal is emitted by driving the loop antenna 14 with the signal.
[0030]
The signal processing circuit 16 operates with the power and clock generated by the modulation / demodulation circuit 15, analyzes the transmission data string D (R → C), and converts the response data string D (C → R) as necessary. Output to.
[0031]
In the reader / writer 13, the modulation / demodulation circuit 19 generates a transmission signal from the transmission data string D (R → C) input from the SPU (signal processing unit) 20, and drives the loop antenna 18 with this transmission signal. The modulation / demodulation circuit 19 performs signal processing on the response signal received by the loop antenna 18 and demodulates the response data string D (C → R) sent from the IC card 12, and the response data string D (C → R). R) is output to the SPU 20.
[0032]
The SPU 20 is composed of an arithmetic processing unit that executes a relatively simple processing procedure. The SPU 20 sends a transmission data string D (R → C) to be transmitted to the IC card 12 to the modem circuit 9 and is input from the modem circuit 19. The response data string D (C → R) is processed. In this process, the SPU 20 displays the process progress and the process result on the display unit 21 as necessary. Further, the operation is switched by a command from the input unit 22, and data such as a processing procedure is input / output to / from the external device 23 as necessary.
[0033]
FIG. 3 is a block diagram showing the modem circuit 15 of the IC card 12 and the modem circuit 19 of the reader / writer 13.
[0034]
In the modulation / demodulation circuit 19, the modulator 27 PSK-modulates the transmission data string D (R → C) input from the SPU 20 with a clock CK1 having a predetermined frequency F1, and outputs a PSK modulation signal S1 based on Manchester code. The modulator 28 drives the loop antenna 18 by ASK modulating the PSK modulation signal S1 output from the modulator 27 with the main carrier Sm having a predetermined frequency Fm.
[0035]
As a result, the reader / writer 13 modulates the transmission data string D (R → C) in two stages to generate a transmission signal, and transmits the transmission signal from the loop antenna 18.
[0036]
In the modulation / demodulation circuit 15 on the IC card 12 side, the power supply circuit 29 receives a transmission signal induced in the loop antenna 14 and rectifies the transmission signal to generate a DC power supply. The power supply circuit 29 supplies this DC power to each circuit block of the IC card 12, thereby operating the modulation / demodulation circuit 15 and the signal processing circuit 16 with the power of the transmission signal.
[0037]
The carrier extractor 30 receives a transmission signal from the loop antenna 14 and extracts a main carrier component from the transmission signal. Further, this main carrier component is output as an operation clock to the demodulator 32. Further, the carrier extractor 30 generates various reference clocks based on the operation clock, and outputs the reference clocks to the signal processing circuit 16 and the like.
[0038]
The demodulator 32 receives the transmission signal from the loop antenna 14 and processes the transmission signal using the operation clock output from the carrier extractor 30, so that the PSK modulation of the modulator 27 superimposed on the transmission signal is performed. Demodulate the signal S1.
[0039]
The band pass filter 33 selectively outputs a signal component corresponding to the output signal S 1 of the modulator 27 by band-limiting the PSK modulation signal S 1 output from the demodulator 32.
[0040]
The demodulator 34 demodulates the transmission data string D (R → C) from the output signal of the bandpass filter 33 and outputs the transmission data string D (R → C) to the signal processing circuit 16. As a result, the IC card 12 can receive the transmission data string D (R → C) sent from the reader / writer 13.
[0041]
The modulator 35 receives the response data string D (C → R) sent from the signal processing circuit 16 to the reader / writer 13, and PSK-modulates the response data string D (C → R) with the clock CK2 having a predetermined frequency F2. A PSK modulation signal S2 based on Manchester code is output.
[0042]
The load circuit 36 is connected to the power supply line output from the power supply circuit 29, and changes the resistance value according to the output signal S2 of the modulator 25. As a result, the load circuit 36 changes the load of the power supply circuit 29 according to the output signal S2, and changes the input impedance of the power supply circuit 29 viewed from the loop antenna 14 according to the output signal S2. As a result, the load circuit 36 changes the power of the transmission signal induced by the loop antenna 14 and re-radiated from the loop antenna 14 in accordance with the output signal S2 of the modulator 35.
[0043]
The power re-radiated from the loop antenna 14 in this way is mainly the power from the main carrier Sm, and the main carrier Sm whose intensity changes around the loop antenna 14 according to the output signal S2 of the modulator 35. Thus, an electromagnetic field is formed. As a result, the modulation / demodulation circuit 15 equivalently ASK modulates the output signal S1 of the modulator 35 with the main carrier wave Sm, and generates a response signal that carries the response data string D (C → R) to the reader / writer 13. The response signal is radiated from the loop antenna 14.
[0044]
As a result, the load circuit 36 and the power supply circuit 29 constitute a modulation circuit that modulates the data string D (C → R) in two stages. The power supply stabilization circuit 37 stabilizes and outputs the power supply voltage that fluctuates due to the load change in this way.
[0045]
The demodulator 38 receives the response signal generated in this way and induced in the loop antenna 18 and demodulates the output signal S2 of the modulator 35 superimposed on the response signal.
[0046]
The bandpass filter 39 selectively outputs a signal component corresponding to the output signal S2 of the modulator 35 by band-limiting the output signal of the demodulator 38.
[0047]
The demodulator 40 demodulates the response data string D (C → R) from the output signal of the bandpass filter 39 and outputs the data string D (C → R) to the SPU 20. As a result, the reader / writer 13 can receive the response data string D (C → R) sent from the IC card 12.
[0048]
In the IC card 12 and the reader / writer 13 that transmit and receive the data string in this way, the frequencies F1 and F2 of the clocks CK1 and CK2 are set at frequencies that differ by a predetermined frequency. Further, as shown in FIG. 4, the frequencies F1 and F2 are obtained by combining the PSK modulation signal S1 output from the modulator 27 on the reader / writer 13 side and the PSK modulation signal S2 output from the modulator 35 on the frequency axis. , The sidebands S1U, S1L, S2U, and S2L do not overlap, and when these PSK modulation signals S1 and S2 are superimposed, PSK modulation is performed by bandpass filters 33 and 39 having a simple configuration. The frequency components are set at sufficiently separated frequencies so that the signal components of the signals S1 and S2 can be extracted.
[0049]
As a result, the IC card 12 and the reader / writer 13 can simultaneously exchange data in both directions.
[0050]
FIG. 1 is a block diagram showing demodulators 34 and 40 applied to the modem circuits 15 and 19, respectively. In the IC card system 11, the demodulator 34 and 40 are configured identically except that signals to be processed are different, so that only the demodulator 34 on the IC card 12 side will be described, and the demodulation on the reader / writer 13 side will be described. About the container 40, the code | symbol corresponding to the location which is different in FIG. 1 is attached | subjected, and the overlapping description is abbreviate | omitted. In the IC card system 11, the demodulator 34, 40 processes the PSK modulation signals S1, S2 by Manchester code to demodulate the data strings D (R → C) and D (C → R).
[0051]
Here, as shown in FIG. 5, the Manchester code is bit coding in which the phase is inverted in one cycle of the clock according to the logic level of the data to be transmitted (FIGS. 5A and 5B). As a result, in the PSK modulation signals S1 and S2, the edge information of the clocks CK1 and CK2 may not be transmitted according to the logic level of the data used for transmission.
[0052]
In the IC card system 11, when the distance between the IC card 12 and the reader / writer 13 is increased, the SN ratio of the demodulated PSK modulation signals S1 and S2 deteriorates and waveform distortion occurs (FIG. 5 ( C)).
[0053]
The binarization circuit 42 includes a binarization circuit having a limiter circuit configuration, binarizes the PSK modulation signal S1 input from the bandpass filter 33, and outputs a binarization signal S3 (FIG. 5D). ). In this case, the binary signal S3 is reproduced by changing the duty ratio from 50 [%] by the amount of distortion of the waveforms of the PSK modulation signals S1 and S2.
[0054]
The oscillator 43 oscillates at a predetermined frequency with respect to the clock CK1 of the PSK modulation signal S1, and outputs an oscillation output signal S4 based on a rectangular wave signal. The variable frequency divider 44 divides the oscillation output signal S4 and outputs a rectangular wave oscillation output signal S5 having a frequency about twice that of the clock CK1 of the PSK modulation signal S1. At this time, the variable frequency divider 44 determines whether the control signal S8 is positive or negative at a constant cycle, and sequentially varies the frequency dividing ratio based on this positive / negative. The two-frequency divider 45 divides this oscillation output signal S5 by ½, and thereby outputs a rectangular wave oscillation output signal S6 having a frequency substantially matching the clock of the PSK modulation signal S1.
[0055]
The edge position deviation amount detection circuit 46 generates the oscillation output signal S. 5 By detecting the logic level of the binarized signal S3 on the basis of the edge timing of the edge, the edge level in the binarized signal S3 is sequentially within a range of ½ period centering on each edge of the oscillation output signal S6. A phase comparison result S7 obtained by detecting presence / absence and whether the phase is a leading phase or a lagging phase with respect to the edge of the oscillation output signal S6 is output.
[0056]
That is, the oscillation output signal S 5 If the logic level of the binarized signal S3 is inverted in the detection of the continuous logic level with reference to, the edge of the corresponding oscillation output signal S6 in this case is present in the binarized signal S3. Judgment can be made. Also, the oscillation output signal S 5 The phase of the oscillation output signal S6 with respect to the edge can be determined by determining the inversion of the logic level with reference to the timing of the edge. As a result, the edge position shift amount detection circuit 46 causes the oscillation output signal S. 5 Is used as a reference, and the position of the edge of the PSK modulation signal S1 is inspected in the range of the front and rear quarter periods, and a phase comparator that outputs the presence / absence of the edge and the edge shift amount is configured.
[0057]
The statistic calculation circuit 47 holds the phase comparison result S7 sequentially input for a predetermined period, and processes the held phase comparison result S7 with reference to the oscillation output signal S6, thereby holding the phase comparison result S7. During the period, the number of edges of the binarized signal S3 corresponding to the rising edge of the oscillation output signal S6 and the number of edges of the binarized signal S3 corresponding to the falling edge of the oscillation output signal S6 are aggregated. . Similarly, every time the oscillation output signal S6 rises and falls, the edge shift amount is totaled and averaged.
[0058]
The statistic calculation circuit 47 selects the summation result of the edge shift amount having the larger number of edges from the number of edges thus summed up, and oscillates with respect to the edge corresponding to the binarized signal based on the summation result. It is determined whether the output signal S6 is a lead phase or a lag phase. Based on the determination result, the statistic calculation circuit 47 outputs a control signal S8 to the variable frequency divider 44, and varies the frequency division ratio of the variable frequency divider 44 in units of one frequency division.
[0059]
Thereby, the statistic calculation circuit 47 calculates the phase shift amount of the oscillation output signal S6 corresponding to the rising edge or the falling edge of the binarized signal S3 having a lot of edge information based on the phase comparison result. Then, phase comparison result processing means for varying the frequency of the oscillation output signal S6 from this phase shift amount is configured.
[0060]
As a result, the oscillator 43, the variable frequency divider 44, the two frequency dividers 45, the edge position deviation amount detection circuit 46, and the statistic calculation circuit 47 constitute a PLL circuit, and the rising edge or falling edge of the binarized signal S3. The edge timing coincides with the edge, and the oscillation output signal S6 that is phase-synchronized with a predetermined phase difference with respect to the clock of the PSK modulation signal S1 is generated (FIGS. 5E and 5F). .
[0061]
Furthermore, the statistic calculation circuit 47 outputs the calculation result S9 of the other phase shift amount provided for the output of the control signal S8 to the sampling position calculation circuit 48. The statistic calculation circuit 47 selectively captures and sequentially transfers the logic level detected by the edge position deviation amount detection circuit 46 at each edge of the oscillation output signal S6 and at timings before and after each edge, and An adder circuit for adding the outputs of the latch groups and a comparator circuit for comparing the addition results of these adder circuits. The comparison result is selectively output and the control signal S8 is output to the variable frequency divider 44. The calculation result S9 is output to the sampling position calculation circuit 48.
[0062]
The sampling position calculation circuit 48 delays the oscillation output signal S6 based on the calculation result S9, thereby gradually correcting the phase difference of the oscillation output signal S6 with respect to the clock of the PSK modulation signal S1 and outputting the clock CK. .
[0063]
The latch circuit 49 demodulates and outputs the data strings D (R → C) and D (C → R) by sequentially latching the binarized signal S3 with reference to the clock CK.
[0064]
In the above configuration, in the IC card system 11 (FIGS. 2 and 3), the transmission data string D (R → C) transmitted from the reader / writer 13 to the IC card 12 is PSK modulated by the modulator 27 by the clock CK1 having the frequency F1. After that, the signal is modulated by the main carrier wave Sm having the frequency Fm and transmitted from the loop antenna 18.
[0065]
As a result, when the IC card 12 approaches the reader / writer 13, a transmission signal modulated by the main carrier wave Sm is induced in the loop antenna 14 of the IC card 12. A part of the induced transmission signal is converted into power of the IC card 12 by the power supply circuit 29, and the modulation / demodulation circuit 15 and the signal processing circuit 16 of the IC card 12 are driven by this power.
[0066]
Further, the transmission signal obtained from the loop antenna 14 is demodulated by the demodulator 32, the output signal S1 of the modulator 27 is demodulated, and the signal component is band-limited by the bandpass filter 33 and separated from other signal components. The data is then input to the demodulator 34 where the transmission data string D (R → C) is demodulated.
[0067]
As a result, the transmission data string D (R → C) is analyzed by the signal processing circuit 16 to generate a response data string D (C → R) to be sent to the reader / writer 13. This response data string D (C → R) is generated. ) Is input to the modulator 35. Here, the response data string D (C → R) is modulated by the clock CK2 having the frequency F2, and the load impedance of the loop antenna 14 is varied by the PSK modulation signal S2 generated by the modulator 35. The signal is transmitted from the loop antenna 14 as an amplitude modulation signal of the main carrier wave Sm.
[0068]
As a result, the response data string D (C → R) is transmitted from the IC card 12 to the reader / writer 13. The response data string D (C → R) transmitted in this way is received by the reader / writer 13 by the loop antenna 18 coupled to the loop antenna 14, and a response signal composed of the received signal is input to the demodulator 38. Thereby, the output signal S2 of the modulator 35 is demodulated. Further, this signal component is band-limited by the band pass filter 39, and after being separated from other signal components, it is input to the following demodulator 40, where the response data string D (C → R) is demodulated. .
[0069]
The transmission data sequence D (R → C) and the response data sequence D (C → R) transmitted and received in this way are PSK modulated by the clocks CK1 and CK2 of the frequencies F1 and F2, and transmitted by bit coding using Manchester code. (FIG. 5), when demodulated by the IC card 12 and the read writer 13, respectively, waveform distortion occurs in the PSK modulation signals S1 and S2 depending on the distance between the IC card 12 and the read writer 13.
[0070]
The received PSK modulation signals S1 and S2 (FIG. 1) are binarized by a binarization circuit 42 having a simple limiter circuit configuration, whereby the binarized signal S3 is read from the IC card 12. The duty ratio changes greatly depending on the distance to the writer 13, and the logic level changes due to noise.
[0071]
In the demodulators 34 and 40, the oscillator 43 generates an oscillation output signal S4 using a rectangular wave signal that is a predetermined multiple of the frequency F1 of the clock CK1 of the PSK modulation signal S1, and the oscillation output signal S4 is converted into a variable frequency divider. A rectangular wave oscillation output signal S5 having a frequency about twice that of the clock CK1 of the PSK modulation signal S1 is generated by the frequency divider 44. The oscillation output signal S5 is divided by 1/2 by the divide-by-2 45 to generate a rectangular wave oscillation output signal S6 having substantially the same frequency as the clock CK1 of the PSK modulation signal S1.
[0072]
The binarized signal S3 is detected in the edge position deviation amount detection circuit 46 by the phase comparison with the oscillation output signal S5 in the range of ½ period centering on each edge of the oscillation output signal S6. Whether the leading phase or the lagging phase is detected with respect to the edge of the oscillation output signal S6 is detected. Further, in the subsequent statistic calculation circuit 47, the number of edges of the binarized signal S3 corresponding to the rising edge of the oscillation output signal S6 and the falling edge of the oscillation output signal S6 are obtained by statistical processing based on the oscillation output signal S6. And the number of edges of the binarized signal S3 corresponding to, and similarly, the amount of edge deviation is totaled every time the oscillation output signal S6 rises and falls.
[0073]
Further, the summation result of the edge shift amount having the larger number of edges is selected from the summed number of edges, and the oscillation output signal S6 advances or lags with respect to the corresponding edge of the binarized signal S3 based on the summation result. Is determined, and the frequency division ratio of the variable frequency divider 44 is sequentially switched so as to correct this phase shift. Thus, the phase of the oscillation output signal S6 is controlled so that the rising edge or the falling edge of the oscillation output signal S6 is phase-synchronized with the edge of the binarized signal S3.
[0074]
Further, the oscillation output signal S6 thus phase-controlled is delayed by the sampling position calculation circuit 48 by the calculation result S9 of the other phase shift amount remaining for the output of the control signal S8, and thereby the PSK modulation signal S1. A clock CK that is phase-synchronized with the clock CK1 is generated, and the binary signal S3 is sequentially latched by this clock CK to demodulate the data string D (R → C).
[0075]
As a result, one edge of the oscillation output signal S6 is controlled so as to be phase-synchronized with the binarized signal S3, and the clock CK is generated by correcting the timing of the oscillation output signal S6 by the phase difference of the other edge. Even when the duty ratio of the value signal S3 changes, the clock CK is correctly reproduced.
[0076]
Further, at this time, the summation result of the edge shift amount having the larger number of edges is selected, and the phase of the oscillation output signal S6 is controlled with respect to the corresponding edge of the binarized signal S3 based on the summation result. Even in the case where the phase is inverted in units of one clock and the logic levels of the modulation signals S1 and S2 are not switched in synchronization with the clock CK, the clock CK is reliably reproduced. At this time, the edge shift amount is totaled and processed, so that the influence of noise is effectively avoided.
[0077]
According to the above configuration, the frequency of the oscillation output signal S6 is controlled so that one edge of the oscillation output signal S6 is phase-synchronized with the binarized signal S3, and the timing of the oscillation output signal S6 is set to the level of the other edge. Even when the duty ratio of the binarized signal S3 is changed by generating the clock CK by correcting with the phase difference, the clock CK can be correctly reproduced. Further, the influence of noise can be effectively avoided by totaling the edge deviation amounts and averaging them. As a result, even when the distance between the IC card and the reader / writer changes and the PSK modulation signal as the input signal deteriorates, the input signal can be reliably processed with a simple configuration.
[0078]
(2) Second embodiment
FIG. 6 is a block diagram showing a demodulator applied to the IC card and the IC card processing device according to the second embodiment. In the configuration shown in FIG. 6, the same configuration as that of the demodulator described above with reference to FIG.
[0079]
In this demodulator 50, the binarization circuit 51 binarizes the PSK modulation signal S1, and outputs the binarization signal S3A and the binarization signal S3B obtained by inverting the polarity of the binarization signal S3A. Output.
[0080]
The variable frequency divider 52 divides the oscillation output signal S4 of the oscillator 43, and a first oscillation output signal S6Q having substantially the same frequency as the PSK modulation signal S1 is 90 degrees with respect to the first oscillation output signal S6Q. A second oscillation output signal S6I having a different phase is output.
[0081]
The selector 53Q exclusively outputs the binarized signals S3A and S3B with the first oscillation output signal S6Q as a reference, thereby exclusive ORing the first oscillation output signal S6Q and the binarized signal S3A. The same phase comparison result S7Q as that obtained by the phase comparison is output.
[0082]
The selector 53I exclusively outputs the binarized signals S3A and S3B on the basis of the second oscillation output signal S6I, thereby exclusive ORing the second oscillation output signal S6I and the binarized signal S3B. The same phase comparison result S7I as the phase comparison is performed is output.
[0083]
The low pass filter (LPF) 54Q obtains a moving average of the phase comparison result S7Q and outputs this moving average value as a demodulation result. The low-pass filter (LPF) 54I outputs a moving average of the phase comparison result S7I.
[0084]
The control direction determination circuit 55 determines the variable direction of the frequency division ratio in the variable frequency divider 52 with reference to the output signals of the low-pass filters 54Q and 54I, and outputs the control signal S8 according to the variable direction.
[0085]
That is, as shown in FIG. 7, when the phase comparison result based on the exclusive OR with the clock CK1 in comparison with the phase comparison results S7I and S7Q is represented by analog quantities S7IA and S7QA, the phase is equal to the clock CK1. If the phase difference is zero (when the phase difference is 0 and π / 2), the phase comparison results S7I and S7Q each have a large value. Is obtained. Further, these values change into a triangular wave shape due to a change in phase difference (FIGS. 7A and 7B).
[0086]
When this relationship is indicated by the signs of the phase comparison results S7I and S7Q (FIGS. 7C and 7D), in the second phase comparison result S7I, the value rises positively in the range of −90 degrees to 90 degrees. The value falls negative in the range of -90 degrees to -180 degrees and in the range of 90 degrees to 180 degrees. Further, in the first phase comparison result S7Q having a phase difference of 90 degrees from this, the value rises positive in the range from 0 degree to 90 degrees and falls negative in the range from 0 degree to -180 degrees.
[0087]
Thus, it can be seen that the phase shift with respect to the binarized signal S3A can be roughly detected by the signs of the phase comparison results S7I and S7Q.
[0088]
On the other hand, in the Manchester code which is a generation reference of the binarized signal S3A, phases of 0 degrees and 180 degrees are formed with respect to the clock CK according to the data logic level. In this case, in the phase comparison results S7I and S7Q using the binarized signal S3A, the portion synchronized in phase with the clock CK1 has a phase difference of 0 degree and a phase difference of 180 according to the data transmitted by the PSK modulation signal S1. It will be switched in degrees.
[0089]
As a result, when the phase difference detected by the phase comparison result S7I is in the range of −90 degrees to 90 degrees, the phase difference of the phase comparison result S7Q is controlled to be 0 degrees as indicated by the arrow a, It is possible to synchronize the oscillation output signal S6I, which is a reference for generating the comparison result S7I, with the clock CK.
[0090]
When the phase difference detected by the phase comparison result S7I is in the range of −180 degrees to −90 degrees and 90 degrees to 180 degrees, the phase difference of the phase comparison result S7Q is 180 degrees as indicated by the arrow b. And the oscillation output signal S6I, which is a reference for generating the phase comparison result S7I, can be synchronized with the clock CK.
[0091]
In accordance with this relationship, as shown in FIG. 8, the control direction determination circuit 55 holds a table in which the signs of the phase comparison results S7I and S7Q are addressed, determines the control direction based on this table, and controls the control signal based on this control direction. S8 is output. In FIG. 8, the control direction is indicated by + and-.
[0092]
According to the configuration shown in FIG. 6, the control direction is determined according to the positive and negative of the first and second phase comparison results based on the first and second phase comparison results from the oscillation output signals having a phase difference of 90 degrees. By changing the oscillation frequency, even if the PSK modulation signals S1 and S2 are deteriorated with a simple configuration, the clock CK can be reliably reproduced and the data can be demodulated.
[0093]
(3) Third embodiment
FIG. 9 is a block diagram showing a demodulator according to the third embodiment. The demodulator 60 detects the phase comparison results S7Q and S7I using exclusive OR circuits (EX-OR) 61Q and 61I instead of the selectors 53Q and 53I described above in FIG.
[0094]
The switching circuit 62 converts the outputs of the low-pass filters 54Q and 54I to absolute values and compares them, so that any of the phases of the first and second oscillation output signals S6Q and S6I corresponding to the outputs of the low-pass filters 54Q and 54I It is determined whether it is close to the phase of the clock CK. Further, based on the determination result, the outputs of the input low-pass filters 54Q and 54I are interchanged and output to the control direction determination circuit 55.
[0095]
As a result, the switching circuit 62 shows that the phase of the first oscillation output signal S6Q in FIG. 10 is indicated by the Q arm, and the phase of the second oscillation output signal S6I is indicated by the I arm. The phase comparison results S7I and S7Q are switched so as to approach the phase on the side, and the phase can be synchronized at a high speed when rising.
[0096]
According to the configuration shown in FIG. 9, in addition to the configuration of the third embodiment, by switching the phase comparison results S7I and S7Q so that the phase of the PSK modulation signal S1 approaches the phase on either side, In addition to the effects of the second embodiment, phase synchronization can be performed at a high speed at the time of startup.
[0097]
(4) Other embodiments
In the second and third embodiments, the case where the demodulation result is output from the output of the low-pass filter has been described. However, the present invention is not limited to this, and the binarized signal is separately latched by a latch circuit. Then, the demodulation result may be output.
[0098]
Furthermore, in the above-described embodiment, the case where the IC card is operated by the power of the transmission signal has been described, but the present invention is not limited to this and can be widely applied to the case where the IC card is operated.
[0099]
In the above-described embodiment, the case where the clock is generated from the PSK modulated signal by the Manchester code and the data is demodulated has been described. However, the present invention is not limited to this, and the clock is generated by various PSK modulated signals. In addition, the present invention can be widely applied to the case where data is demodulated, the clock is generated from various modulation signals such as when the clock is generated from the ASK modulation signal, and the data is reproduced using this clock.
[0100]
In the above-described embodiment, the case where the present invention is applied to a reader / writer composed of an IC card and an IC card processing device has been described. However, the present invention is not limited to this, and PLL circuits and demodulation of various data transmission devices. It can be widely applied to circuits.
[0101]
【The invention's effect】
As described above, according to the present invention, the phase comparison result between the oscillation output signal and the binarized signal is By the rising edge of the oscillation output signal and by the falling edge of the oscillation output signal, respectively By averaging and calculating the phase shift amount for either the rising edge or falling edge, and controlling the oscillation output signal from this phase shift amount Easy With an easy configuration, the input signal can be reliably processed even when the input signal is deteriorated.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a demodulator applied to an IC card and a reader / writer according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing an overall configuration of an IC card system.
3 is a block diagram showing a modulation / demodulation circuit of the IC card system of FIG. 2;
4 is a characteristic curve diagram showing a frequency spectrum of a transmission signal and a response signal in the IC card system of FIG. 2. FIG.
FIG. 5 is a signal waveform diagram for explaining the operation of the demodulator of FIG. 1;
FIG. 6 is a block diagram showing a demodulator applied to an IC card and a reader / writer according to a second embodiment of the present invention.
7 is a characteristic curve diagram for explaining the operation of the demodulator of FIG. 6; FIG.
8 is a chart for explaining a control direction determination circuit of the demodulator of FIG. 6;
FIG. 9 is a block diagram showing a demodulator applied to an IC card and a reader / writer according to a third embodiment of the present invention.
10 is a characteristic curve diagram for explaining the operation of the demodulator of FIG. 9;
FIG. 11 is a block diagram showing a conventional demodulator.
[Explanation of symbols]
1, 34, 40, 50, 60 ... demodulator, 2, 43, 51 ... binarization circuit, 3 ... phase comparison circuit, 4 ... control oscillation circuit, 5, 54I, 54Q ... low-pass filter , 6, 49... Latch, 11... IC card system, 12... IC card, 13... Reader / writer, 15, 19 .. modulation / demodulation circuit, 46. Calculation circuit 48... Sampling position calculation circuit 53I 53Q Selector 55 Control direction determination circuit 61I 61Q Exclusive OR circuit 62 Switching circuit

Claims (12)

In a PLL circuit that regenerates a clock that is used to regenerate data included in the input signal from an input signal that includes data transmitted in synchronization with the clock via a desired transmission system,
Binarization means for binarizing the input signal to generate a binarized signal;
Signal generating means for varying the frequency of the oscillation output signal by a control signal;
Phase comparison means for comparing the phase of the oscillation output signal and the binarized signal and outputting a phase comparison result;
The phase comparison result with respect to the rising edge of the oscillation output signal and the phase comparison result with respect to the falling edge of the oscillation output signal are averaged, and the first binarized signal with respect to the rising edge of the oscillation output signal is averaged. And a phase at which the control signal is output based on the first or second phase shift amount, and a second phase shift amount of the binarized signal with respect to a falling edge of the oscillation output signal. A comparison result processing means;
A PLL circuit comprising: phase correction means for correcting the phase of the oscillation output signal based on the detection result of the second or first phase shift amount and outputting the clock. The PLL circuit according to claim 1, wherein the input signal is a PSK modulation signal. The PLL circuit according to claim 1, wherein the input signal is a modulation signal based on Manchester code. In a demodulation circuit that reproduces a data string transmitted through the input signal from an input signal transmitted through a desired transmission system,
Binarization means for binarizing the input signal to generate a binarized signal;
Signal generating means for varying the frequency of the oscillation output signal by a control signal;
Phase comparison means for comparing the phase of the oscillation output signal and the binarized signal and outputting a phase comparison result;
The phase comparison result with respect to the rising edge of the oscillation output signal and the phase comparison result with respect to the falling edge of the oscillation output signal are averaged, and the first binarized signal with respect to the rising edge of the oscillation output signal is averaged. And a phase at which the control signal is output based on the first or second phase shift amount, and a second phase shift amount of the binarized signal with respect to a falling edge of the oscillation output signal. A comparison result processing means;
Timing correction means for correcting the phase of the oscillation output signal and outputting a timing correction signal based on the detection result of the second or first phase shift amount;
And a latch means for latching the binarized signal by the timing correction signal. The demodulation circuit according to claim 4, wherein the input signal is a PSK modulation signal. The demodulation circuit according to claim 4, wherein the input signal is a modulated signal based on Manchester code. In an IC card that demodulates and processes a data string from a transmission signal received via an antenna by a demodulation circuit,
The demodulation circuit includes:
Binarization means for binarizing a modulation signal obtained from the transmission signal to generate a binarized signal;
Signal generating means for varying the frequency of the oscillation output signal by a control signal;
Phase comparison means for comparing the phase of the oscillation output signal and the binarized signal and outputting a phase comparison result;
The phase comparison result with respect to the rising edge of the oscillation output signal and the phase comparison result with respect to the falling edge of the oscillation output signal are averaged, and the first binarized signal with respect to the rising edge of the oscillation output signal is averaged. And a phase at which the control signal is output based on the first or second phase shift amount, and a second phase shift amount of the binarized signal with respect to a falling edge of the oscillation output signal. A comparison result processing means;
Timing correction means for correcting the phase of the oscillation output signal and outputting a timing correction signal based on the detection result of the second or first phase shift amount;
An IC card comprising: latch means for latching the binarized signal by the timing correction signal and reproducing the data string. The IC card according to claim 7, wherein the modulation signal is a PSK modulation signal. The IC card according to claim 7, wherein the modulation signal is a signal based on Manchester code. In an IC card processing apparatus that demodulates and processes a data string sent from an IC card using a demodulation circuit from a response signal received via an antenna,
The demodulation circuit includes:
Binarization means for binarizing a modulation signal obtained from the response signal to generate a binarized signal;
Signal generating means for varying the frequency of the oscillation output signal by a control signal;
Phase comparison means for comparing the phase of the oscillation output signal and the binarized signal and outputting a phase comparison result;
The phase comparison result with respect to the rising edge of the oscillation output signal and the phase comparison result with respect to the falling edge of the oscillation output signal are averaged, and the first binarized signal with respect to the rising edge of the oscillation output signal is averaged. And a phase at which the control signal is output based on the first or second phase shift amount, and a second phase shift amount of the binarized signal with respect to a falling edge of the oscillation output signal. A comparison result processing means;
Timing correction means for correcting the phase of the oscillation output signal and outputting a timing correction signal based on the detection result of the second or first phase shift amount;
An IC card processing apparatus, comprising: latch means for latching the binarized signal by the timing correction signal and reproducing the data string. The IC card processing device according to claim 10, wherein the modulation signal is a PSK modulation signal. The IC card processing device according to claim 10, wherein the modulation signal is a signal based on Manchester code.

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