JP4513678B2 - PLL circuit and IC chip - Google Patents

Description

  The present invention relates to a PLL (Phase Lock Loop) circuit and an IC chip, and in particular, a PLL circuit and an IC chip that can increase a communication transfer rate without increasing the frequency of an oscillator provided in a non-contact IC chip. About.

  FIG. 1 is a diagram illustrating an example of a conventional PLL circuit.

  The phase comparator 1 compares the input reference input signal Asinωt (A is a constant) with the phase of the oscillation output signal −cos (ωt + φ) supplied from the controlled oscillator 3 to reduce the signal representing the phase difference. Output to the band pass filter 2.

  The low-pass filter 2 removes the high frequency component of the signal supplied from the phase comparator 1 and outputs the obtained signal to the control type oscillator 3 as a control signal. Since the output of the low-pass filter 2 is obtained by multiplying the reference input signal Asinωt and the oscillation output signal −cos (ωt + φ) and removing the high frequency component, −φ (≈−sinφ) as shown in FIG. It is represented by

  The controlled oscillator 3 is, for example, a VOC (Voltage Controlled Oscillator), and outputs an oscillation output signal −cos (ωt + φ) having a frequency corresponding to the control signal supplied from the low-pass filter 2 to the phase comparator 1. .

  The PLL circuit having such a configuration reproduces a clock signal based on a signal input from the outside.

  By the way, as a device in which a communication module including such a PLL circuit is mounted, there is a non-contact IC chip that performs non-contact communication with a reader / writer provided outside, and between the non-contact IC chip and the reader / writer. Then, data exchange is performed using the Manchester code.

  The Manchester code represents a value (data) of “0” from a sequence of H (High) level and L (Low) level on the basis of a clock signal having a duty ratio of 50%, and “1” from a sequence of L level and H level. Represents the value of "". A signal (Manchester signal) representing data encoded by the Manchester code is expressed by the following equation (1).

  Therefore, when the PLL circuit as shown in FIG. 1 is provided in the non-contact IC chip, the signal represented by the equation (1) is input to the PLL circuit, so that the value of D (t) is set. Accordingly, that is, the phase is reversed according to the content of the data transmitted from the reader / writer, and it becomes difficult to keep the locked state (the state in which the phase difference is stabilized to 0).

  Therefore, in the non-contact IC chip, as a clock generation circuit, for example, as shown in FIG. 2, the phase can be controlled following the Manchester signal (PSK (Phase Shift Keying) signal) in consideration of the polarity of data. A Costas loop as shown in FIG.

  The multiplier 11-1 (I multiplier) and the PSK modulation signal Asin (ωt + D (t) π) input via an RF (Radio Frequency) amplifier provided at the subsequent stage of the antenna and the voltage controlled oscillator 14 The oscillation output signal sin (ωt + φ) supplied from is multiplied and the obtained signal is output to the low-pass filter 12-1.

  The multiplier 11-2 (Q multiplier) has a phase of π / 2 with reference to the PSK modulation signal Asin (ωt + D (t) π) and the signal supplied from the voltage controlled oscillator 14 to the multiplier 11-1. The delayed oscillation output signal -cos (ωt + φ) is multiplied and the obtained signal is output to the low-pass filter 12-2.

  The low-pass filter 12-1 removes the high-frequency component of the signal supplied from the multiplier 11-1, and obtains the obtained signal from the demodulated data D (t) ("~" in the figure is from the reader / writer. Output to the outside as data corresponding to the transmitted data (D (t)), indicating that it is the data reproduced from the received signal), and the phase comparison result between the PSK modulation signal and the oscillation output signal (I arm To the multiplier 13 as a signal representing the result of phase comparison).

  The low-pass filter 12-2 removes the high frequency component of the signal supplied from the multiplier 11-2, and the obtained signal is compared with the phase comparison result of the PSK modulation signal and the oscillation output signal (Q arm phase comparison). The result is output to the multiplier 13 as a signal.

  The multiplier 13 multiplies the signal supplied from the low-pass filter 12-1 and the signal supplied from the low-pass filter 12-2, and uses the obtained signal D (t) φ as a control signal. Output to the voltage controlled oscillator 14.

  Based on the control signal D (t) φ supplied from the multiplier 13, the voltage controlled oscillator 14 supplies the oscillation output signal sin (ωt + φ) to the multiplier 11-1 and the oscillation output signal −cos (ωt + φ). Each is output to the multiplier 11-2.

  FIG. 3 is a diagram showing an example in which the Costas loop of FIG. 2 is digitized.

  The multipliers 11-1 and 11-2 in FIG. 2 are used as EX-OR circuits (exclusive OR circuits), the low-pass filters 12-1 and 12-2 are used as digital filters, and the voltage-controlled oscillator 14 is connected as an NCO. The Costas loop can be digitized by substituting (Numerical Controlled Oscillator) and tabulating the multiplication result of the multiplier 13 (control rule of the voltage controlled oscillator).

  The hard limiter 21 binarizes the PSK modulation signal and outputs the obtained binarized signal to the EX-OR circuits 22-1 and 22-2, respectively. Note that the description in “” in FIG. 3 shows specific examples of values and the like when the Costas loop of FIG. 3 is applied to FeliCa (registered trademark) which is one of the non-contact IC chips. For example, the PSK modulation signal input to the hard limiter 21 is a signal representing data with a transfer rate of 211 Kbps. In the hard limiter 21, one period of the PSK modulation signal is binarized into data of 8 samples.

  The EX-OR circuit 22-1 performs an exclusive OR operation of the binarized signal supplied from the hard limiter 21 and the oscillation output signal supplied from the NCO 27 (frequency division ratio variable frequency divider 32). And outputs the calculation result to the low-pass filter 23-1. A variable frequency division type frequency divider 32 supplies a signal having a frequency substantially the same as the frequency of the PSK modulation signal input to the Costas loop of FIG.

  The EX-OR circuit 22-2 performs an exclusive OR operation on the binarized signal supplied from the hard limiter 21 and the oscillation output signal supplied from the NCO 27, and the operation result is converted to a low-pass filter 23-. Output to 2. The variable divider ratio type frequency divider 32 is a signal having substantially the same frequency as the frequency of the PSK modulation signal input to the Costas loop of FIG. 3, and is based on the signal supplied to the EX-OR circuit 22-1. As a result, a signal whose phase is delayed by π / 2 is supplied.

  The low-pass filter 23-1 obtains a moving average of the output of the EX-OR circuit 22-1, and outputs the obtained moving average to the ternary circuit 24-1 as a phase comparison result of the I arm. For example, if one period of a PSK modulation signal is binarized into 8 sample data, a moving average is obtained for the half period (4 sample data), and a signal representing the moving average with 5 values is obtained. The data is output to the ternary circuit 24-1.

  The low-pass filter 23-2 calculates a moving average of the output of the EX-OR circuit 22-2, and outputs the calculated moving average to the ternary circuit 24-2 as a phase comparison result of the Q arm.

  The ternary circuit 24-1 converts the moving average supplied from the low-pass filter 23-1 into, for example, a ternary value and outputs the ternized moving average to the table management unit 25.

  The ternary circuit 24-2 converts the moving average supplied from the low-pass filter 23-2 into, for example, a ternary value and outputs the ternized moving average to the table management unit 25.

  The table management unit 25 associates the control direction of the division ratio of the variable division ratio type frequency divider 32 with the phase comparison result (moving average) obtained by the low-pass filters 23-1, 23-2 and the like. The control table is managed, the control direction is determined based on the moving average supplied from the ternary circuits 24-1 and 24-2, and the control signal is output to the standardization circuit 26.

  The standardization circuit 26 removes the influence of noise by standardizing the control signal supplied from the table management unit 25 (such as averaging the edge position), and divides the standardized control signal into a variable division ratio type. Output to the device 32. The standardization of the control signal is performed, for example, every 8 samples of data that is data for one period, and represents a standardized control direction.

  The NCO 27 includes an oscillator 31 and a variable dividing ratio type frequency divider 32. The oscillator 31 outputs an oscillation output signal having a predetermined frequency (N × Frate) to the frequency division variable frequency divider 32. For example, a signal of 13.56 MHz (64 × 211 Kbps) is output from the oscillator 31.

  The variable dividing ratio type frequency divider 32 determines the dividing ratio based on the sign of the control signal supplied from the standardization circuit 26, and divides the oscillation output signal of the oscillator 31 by the determined ratio (N ± 1). Go around. The variable division ratio type frequency divider 32 outputs the obtained oscillation output signal (a signal having a frequency substantially the same as the frequency of the PSK modulation signal input to the Costas loop of FIG. 3) to the EX-OR circuit 22-1. At the same time, an oscillation output signal whose phase is delayed by π / 2 with respect to the signal output to the EX-OR circuit 22-1 is output to the EX-OR circuit 22-2. The value of the frequency division ratio N is 64, for example.

  4A to 4E are diagrams showing examples of signals handled in the Costas loop of FIG. 3 having the above-described configuration.

  The waveform of FIG. 4A represents data (clock signal) input to the Costas loop of FIG.

  The upper waveform of FIG. 4B shows the division ratio when the phase difference between the oscillation output signal supplied from the variable division ratio divider 32 to the EX-OR circuit 22-1 and the clock signal is zero. This represents an oscillation output signal supplied from the variable frequency divider 32 to the EX-OR circuit 22-1. The number shown on the upper side with reference to the position of the 0th level of the waveform (0 in the upper stage of FIG. 4B) represents the calculation result of the oscillation output signal and the clock signal performed by the EX-OR circuit 22-1, and the 0th level position The number shown on the lower side as a reference (0 in the upper part of FIG. 4B) represents the moving average of the calculation results by the EX-OR circuit 22-1. However, the notation is four times the moving average. The moving average is obtained for four samples of data that are half a cycle.

  That is, when the phase difference from the clock signal is 0, a signal that continues to have a 0 level is output as an operation result from the EX-OR circuit 22-1 to the low-pass filter 23-1, and the data of 4 samples in a half cycle is obtained. A signal representing 0 which is a moving average obtained as a target is output from the low-pass filter 23-1 to the ternary circuit 24-1.

  In addition to the waveforms in the lower stage of FIG. 4B, in the waveforms of FIGS. 4C to 4E, the numbers shown on the upper side and the lower side with respect to the position of the 0 level are respectively the exclusive OR operation of the oscillation output signal and the clock signal. Results and moving averages are represented.

  The waveform in the lower part of FIG. 4B shows the division ratio when the phase difference between the oscillation output signal supplied from the variable division ratio divider 32 to the EX-OR circuit 22-2 and the clock signal is zero. This represents an oscillation output signal (a signal delayed in phase by π / 2 with reference to the upper signal in FIG. 4B) supplied from the variable frequency divider 32 to the EX-OR circuit 22-2. As shown in the lower part of FIG. 4B, in this case, a signal that repeats “00110011” for each period is output as an operation result from the EX-OR circuit 22-2 to the low-pass filter 23-2, and four samples of a half period are obtained. A signal representing 2 which is a moving average obtained for data is output from the low-pass filter 23-2 to the ternary circuit 24-2.

  The upper waveform of FIG. 4C shows the division when the phase difference between the oscillation output signal and the clock signal supplied from the variable division ratio divider 32 to the EX-OR circuit 22-1 is π / 2. An oscillation output signal supplied from the variable frequency ratio type frequency divider 32 to the EX-OR circuit 22-1 is shown. As shown in the upper part of FIG. 4C, in this case, a signal that repeats “00110011” for each period is output from the EX-OR circuit 22-1 to the low-pass filter 23-1 as a calculation result, and four samples of a half period are obtained. A signal representing 2 which is a moving average obtained for data is output from the low-pass filter 23-1 to the ternary circuit 24-1.

  The waveform in the lower part of FIG. 4C shows the division when the phase difference between the oscillation output signal supplied from the variable division ratio divider 32 to the EX-OR circuit 22-2 and the clock signal is π / 2. It represents an oscillation output signal (a signal delayed in phase by π / 2 with reference to the upper signal in FIG. 4C) supplied from the variable frequency divider 32 to the EX-OR circuit 22-2. As shown in the lower part of FIG. 4C, in this case, a signal having one level is output as an operation result from the EX-OR circuit 22-2 to the low-pass filter 23-2, and the data of four samples in a half cycle is obtained as an object. A signal representing the obtained moving average of 4 is output from the low-pass filter 23-2 to the ternarization circuit 24-2.

  The upper waveform in FIG. 4D shows the division ratio when the phase difference between the oscillation output signal supplied from the variable division ratio divider 32 to the EX-OR circuit 22-1 and the clock signal is π. This represents an oscillation output signal supplied from the variable frequency divider 32 to the EX-OR circuit 22-1. As shown in the upper part of FIG. 4D, in this case, a signal having one level is output from the EX-OR circuit 22-1 to the low-pass filter 23-1 as a calculation result, and the data of four samples in a half cycle is obtained as an object. A signal representing the obtained moving average of 4 is output from the low-pass filter 23-1 to the ternary circuit 24-1.

  The lower waveform of FIG. 4D shows the frequency division ratio when the phase difference between the oscillation output signal and the clock signal supplied from the variable frequency division ratio divider 32 to the EX-OR circuit 22-2 is π. This represents an oscillation output signal (a signal delayed in phase by π / 2 from the upper signal in FIG. 4D) supplied from the variable frequency divider 32 to the EX-OR circuit 22-2. As shown in the lower part of FIG. 4D, in this case, a signal that repeats “11001100” for each cycle is output from the EX-OR circuit 22-2 to the low-pass filter 23-2 as a calculation result, and four samples of a half cycle are output. A signal representing 2 which is a moving average obtained for data is output from the low-pass filter 23-2 to the ternary circuit 24-2.

  The waveform in the upper part of FIG. 4E is obtained when the phase difference between the oscillation output signal and the clock signal supplied from the variable division ratio divider 32 to the EX-OR circuit 22-1 is 3π / 2. An oscillation output signal supplied from the variable frequency ratio type frequency divider 32 to the EX-OR circuit 22-1 is shown. As shown in the upper part of FIG. 4E, in this case, a signal that repeats “11001100” for each period is output from the EX-OR circuit 22-1 to the low-pass filter 23-1 as a calculation result, and four samples of a half period are output. A signal representing 2 which is a moving average obtained for data is output from the low-pass filter 23-1 to the ternary circuit 24-1.

  The waveform in the lower part of FIG. 4E shows the division when the phase difference between the oscillation output signal supplied from the variable division ratio divider 32 to the EX-OR circuit 22-2 and the clock signal is 3π / 2. This represents an oscillation output signal (a signal delayed in phase by π / 2 from the upper stage signal in FIG. 4E) supplied from the variable frequency ratio divider 32 to the EX-OR circuit 22-2. As shown in the lower part of FIG. 4E, in this case, a signal that continues to have a zero level is output as an operation result from the EX-OR circuit 22-2 to the low-pass filter 23-2, and is obtained from data of four samples in a half cycle. A signal representing 0, which is the moving average, is output from the low-pass filter 23-2 to the ternary circuit 24-2.

  The moving average obtained in this way is -1 in the ternary circuits 24-1 and 24-2, such that the moving average 0 is -1, the moving average 2 is 0, and the moving average 4 is 1. 0,1) and a signal representing each value is output to the table management unit 25.

  FIG. 5 is a graph showing a result of plotting the phase comparison results of the I arm and Q arm, with the horizontal axis representing the phase difference and the vertical axis representing the ternary value (moving average). In FIG. 5, the solid line represents the phase comparison result of the upper I arm in FIGS. 4B to 4E, and the dotted line represents the phase comparison result of the lower Q arm in FIGS.

  The table management unit 25 has a graph as shown in FIG. 5, and the moving average of the phase comparison results of the I arm supplied from the ternary circuit 24-1 and the ternary circuit 24-2. By monitoring the moving average of the phase comparison results of the supplied Q arm, it is possible to determine how much the phase has shifted with respect to the clock signal.

  For example, the moving average of the phase comparison result of the I arm is 2 (0 when ternary is obtained by -1, 0, 1), and the moving average of the phase comparison result of the Q arm is 4 (three values are -1, 0, 1). In the case of 1), the table management unit 25 finds a phase difference that takes both values in the graph of FIG. 5, and can determine that the phase difference from the clock signal is now π / 2. it can.

  As a result, the table management unit 25 can change the divider ratio variable frequency divider from the current state to make it synchronized with the clock signal (to make the phase difference zero). It is possible to determine how to control the frequency division ratio of 32. FIG. 6 shows a control rule table in which the phase difference and the control direction of the division ratio are associated with each other. In FIG. 6, the control direction is indicated by + and-.

Thus, according to the rules of the control table prepared in advance, the Costas loop that controls the frequency division ratio of the frequency divider based on the positive / negative of the phase comparison result by the transmission output signal whose phase is shifted by π / 2 is patented. It is disclosed in Document 1.
JP 11-274919 A

  By the way, in the conventional method for ensuring the phase synchronization with the clock signal by controlling the frequency dividing ratio of the frequency divider as described above, there is a limit to the resolution of the phase to be controlled in order to follow the clock signal. There was a problem.

That is, since the frequency of the oscillation output signal supplied from the NCO (frequency divider) to the EX-OR circuit is expressed by the following equation (2), communication between the reader / writer and the non-contact IC chip can be performed at a higher transfer rate. to do is to reduce the value of N _div, where it is necessary to increase the frequency F _nco of the oscillation output signal, reducing the value of N _div, to ensure a sufficient resolution in order to control the phase It becomes difficult.

For example, as shown in FIG. 3, if the value of the division ratio N of the variable division ratio divider 32 is about 64, the phase can be controlled with a resolution of 2π / 64. as shown, while the frequency F _mclk of the oscillator of 13.56 MHz, the reader-writer - contactless IC 847KHz transfer rate of the communication between chips in order to (a frequency F 847KHz the _nco) value of the frequency division ratio N _div In this case, the phase can be controlled only with a particle size of 2π / 16, that is, with a particle size of about 1/4 compared to when the value of the frequency division ratio is 64.

This becomes more pronounced as the value of the frequency division ratio _Ndiv is decreased in order to further increase the communication transfer rate between the reader / writer and the non-contact IC chip.

On the other hand, in order to increase the transfer rate, it is conceivable to increase the value of the frequency F _mclk of the oscillator. However, it is possible to receive an electromagnetic wave from a reader / writer and drive based on a power source generated from the received electromagnetic wave. From the viewpoint of the oscillator of the contact IC chip, it is not preferable to increase the value of the frequency F _mclk .

  The present invention has been made in view of such a situation, and makes it possible to increase the communication transfer rate without increasing the frequency of the oscillator provided in the non-contact IC chip.

The oscillator of the first PLL circuit of the present invention is provided for each of the first waveform and the second waveform, the first waveform, and the second waveform, which are two repetitive waveforms having different phases from each other. A multiplication result of a first multiplier and a second multiplier which are set in association with a predetermined variable and are different from each other; a multiplication result of the first waveform and the first multiplier; and a second waveform The sum of the multiplication results with the second multiplier, the multiplication result between the first waveform and the second multiplier, and the difference between the multiplication results between the second waveform and the first multiplier are used as phase comparison results, respectively. An oscillator output is obtained by calculating and controlling a phase of the oscillator by changing a predetermined variable and changing a setting of the first multiplier and the second multiplier according to the relationship between the sum and difference as a phase comparison result. An oscillator is provided.

The second PLL circuit of the present invention and the PLL circuit provided in the IC chip of the present invention are set in association with a predetermined variable, a first signal set in association with a predetermined variable, and have a predetermined frequency Generating means for generating a second signal which is a signal whose phase is shifted by π / 2 with reference to a first signal obtained by dividing the oscillation output signal by a predetermined frequency dividing ratio; A first phase comparison result that is a result of phase comparison between the first output signal and a multiplication result of a PSK (Phase Shift Keying) modulation signal obtained by demodulating the oscillation output signal of the signal and an external electromagnetic wave; A second phase comparison which is a result of phase comparison between the second oscillation output signal whose phase is shifted by π / 2 with respect to the first oscillation output signal and the PKS modulation signal and the second signal. the result, the first signal generated by the generating means, the first oscillation output signal and PK The multiplication result of the S signal, the sum of the multiplication results of the second signal, the second oscillation output signal, and the PKS signal, the multiplication result of the first signal, the second oscillation output signal, and the PKS signal, and the first 2 based on the first and second phase comparison results obtained by the calculation by the calculation means, the calculation means performing the calculation as represented by the difference between the two signals, the first oscillation output signal, and the multiplication result of the PKS signal. And a control means for controlling a predetermined variable for setting the first and second signals generated by the generating means.

The control means manages the information indicating the control content of the generating means in association with the first and second phase comparison results obtained by the calculation by the calculation means, and refers to the information managed , The phase of the first and second signals generated by the generating means can be controlled by changing the variable .

The first signal and the second signal can be C and S represented by C = cos φ and S = sin φ , respectively , and φ is a predetermined variable composed of the phase of the required repetitive waveform. Can

In the first PLL circuit of the present invention, the first waveform and the second waveform, and the first waveform and the second waveform, which are two repetitive waveforms having different phases from each other, are predetermined. The multiplication result of the first multiplier and the second multiplier which are different from each other and are set in correspondence with each other variable is obtained, the multiplication result of the first waveform and the first multiplier, and the second waveform and the second multiplier. The sum of the multiplication results with the multiplier of 2 and the difference between the multiplication results of the first waveform and the second multiplier and the multiplication results of the second waveform and the first multiplier are respectively calculated as phase comparison results. A predetermined variable is changed according to the relation between the sum and the difference as the phase comparison result, and the phase of the oscillator is controlled by changing the setting of the first multiplier and the second multiplier , An oscillator output is obtained.

In the second PLL circuit of the present invention and the PLL circuit provided in the IC chip of the present invention, the first signal set in association with the predetermined variable, and set in association with the predetermined variable, And a second signal that is a signal whose phase is shifted by π / 2 with respect to the first signal, and a first oscillation obtained by dividing the oscillation output signal of a predetermined frequency by a predetermined frequency division ratio. The multiplication result of the output signal and the PSK modulation signal obtained by demodulating the electromagnetic wave from the outside , the first phase comparison result that is the phase comparison result of the first signal, and the first oscillation output signal As a reference, the multiplication result of the second oscillation output signal whose phase is shifted by π / 2 and the PKS modulation signal and the second phase comparison result which is the phase comparison result of the second signal are the first signal, the multiplication result of the first oscillation output signal and PKS signal, and a second signal, the Oscillation output signal, and the sum of the multiplication results of the PKS signal, a first signal, a second oscillating output signals, and the multiplication result of the PKS signal, and a second signal, the first oscillating output signal, and PKS signal The calculation is performed as represented by the difference between the multiplication results of. Further, the synchronization state is controlled by changing predetermined variables for setting the first and second signals based on the first and second phase comparison results obtained by the calculation.

  According to the present invention, the communication transfer rate can be increased without increasing the frequency of the oscillator provided in the non-contact IC chip.

  Embodiments of the present invention will be described below. The correspondence relationship between the invention described in this specification and the embodiments of the invention is exemplified as follows. This description is intended to assure that embodiments supporting the claimed invention are described in this specification. Therefore, although there is an embodiment which is described in the embodiment of the invention but is not described here as corresponding to the invention, it means that the embodiment is not It does not mean that it does not correspond to the invention. Conversely, even if an embodiment is described herein as corresponding to an invention, that means that the embodiment does not correspond to an invention other than the invention. Absent.

  Further, this description does not mean all the inventions described in this specification. In other words, this description is for the invention described in the present specification and not claimed in this application, i.e., the existence of an invention that will be filed in the future or added by amendment. There is no denial.

The oscillator of the PLL circuit according to claim 1 (for example, an oscillator having the configuration of FIG. 9) includes a first waveform and a second waveform, which are two repetitive waveforms having different phases, and a first waveform, For each of the second waveform and the second waveform, a multiplication result of a first multiplier and a second multiplier which are set in association with a predetermined variable and are different from each other is obtained, and the first waveform and the first multiplier are obtained. , The sum of the multiplication results of the second waveform and the second multiplier, the multiplication result of the first waveform and the second multiplier, and the second waveform and the first multiplier. The difference between the multiplication results is calculated as the phase comparison result , the predetermined variable is changed according to the relationship between the sum and difference as the phase comparison result, and the setting of the first multiplier and the second multiplier is changed to thereby change the oscillator. Provide an oscillator to obtain the oscillator output by controlling the phase of And features.

According to a second aspect of the present invention, the PLL circuit is set in association with a predetermined variable and a first signal set in association with a predetermined variable, and divides an oscillation output signal having a predetermined frequency by a predetermined frequency division ratio. Generating means (for example, the variable oscillator 110 of FIG. 12) that generates a second signal that is a signal that is shifted in phase by π / 2 with respect to the first signal obtained by the rotation; A first phase comparison result, which is a phase comparison result between the oscillation output signal and a PSK (Phase Shift Keying) modulation signal obtained by demodulating an external electromagnetic wave, and the first signal , A second phase comparison result which is a result of phase comparison between the second oscillation output signal whose phase is shifted by π / 2 with respect to the first oscillation output signal and the PKS modulation signal and the second signal. preparative, first signal generated by the generating means, the first oscillation output signal and PKS Multiplication result, and a second signal of the item, the second oscillating output signals, and the sum of the multiplication results of the PKS signal, a first signal, a second oscillating output signals, and PKS signal multiplication results, and the second , The first oscillation output signal, and the difference between the multiplication results of the PKS signals, for example, arithmetic means (for example, multipliers 103-1, 103-2, 104-1, 104- in FIG. 14). 2. First and second signals generated by the generating means are set on the basis of the first and second phase comparison results obtained by calculation by the adders 105-1 and 105-2) and the calculating means. Control means for controlling a predetermined variable (for example, the table management unit 108 in FIG. 14) is provided.

The control means of the PLL circuit according to claim 3 is information (control table) indicating the control contents of the generating means in association with the first and second phase comparison results obtained by the calculation by the calculating means. And the phase of the first and second signals generated by the generating means is controlled by changing a predetermined variable with reference to the managed information.

Also in the IC chip according to the fifth aspect, the embodiment (however, an example) to which each means corresponds is the same as the PLL circuit according to the first aspect.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 8 is a block diagram showing a configuration example of a part of the non-contact IC chip 51 to which the present invention is applied.

  The non-contact IC chip 51 is built in, for example, a card worn by a reader / writer of a ticket gate installed in a train station, and includes a demodulation circuit 61, a DPLL (Digital Phase Lock Loop) 62, and A CPU (Central Processing Unit) 63 is provided.

  The demodulating circuit 61 generates electric power necessary for the operation of the non-contact IC chip 51 based on an RF input signal supplied from an antenna (not shown) that has received an electromagnetic wave from the reader / writer, and the generated electric power is supplied to each unit. The demodulated data (PSK modulation signal) obtained by the demodulation is output to the DPLL 62 while being supplied.

  The DPLL 62 extracts data transmitted from the reader / writer based on the PSK modulation signal supplied from the demodulation circuit 61 and outputs a bit string (1, 0) representing the extracted data to the CPU 63.

  Based on the bit string supplied from the DPLL 62, the CPU 63 performs predetermined processing such as reading and writing of data stored in the nonvolatile memory.

  FIG. 9 is a diagram illustrating an example of a configuration provided in the DPLL 62 in FIG.

  The operation of this circuit is to multiply an input repetitive waveform of two different phases by C times and S times, respectively, and then perform linear addition to generate an output signal. The method of generating C and S at that time is calculated as C = cosφ and S = sinφ, where φ is the phase of the required repetitive waveform.

  Here, C and S are not necessarily calculated, and may be converted by a conversion table.

  The variable oscillator 71 changes the value of φ in accordance with a control signal from the outside (table management unit 108 and standardization circuit 109 in FIG. 12, which will be described later), and applies an oscillation output signal represented by cosφ to the multiplier 72-1. The oscillation output signal represented by sinφ is output to the multipliers 73-1 and 73-2 in 72-2, respectively. Here, φ is represented by f (cnt) (cnt: control content).

  The multiplier 72-1 multiplies the oscillation output signal cosφ supplied from the variable oscillator 71 by the supplied oscillation output signal sinωt (PSK · sinωt), and adds a signal representing the multiplication result to the adder 74-1. Output to. As will be described later, the multiplier 72-1 multiplies the oscillation output signal sinωt, which is generated by an oscillator that generates a signal having a fixed frequency, and is divided by a predetermined division ratio, and the PSK modulation signal. The signal PSK · sinωt, which is the signal obtained in this way, is supplied.

  The multiplier 72-2 multiplies the oscillation output signal cosφ supplied from the variable oscillator 71 and the supplied oscillation output signal cosωt, and outputs a signal representing the multiplication result to the adder 74-2. As will be described later, the multiplier 72-2 multiplies the oscillation output signal cosωt generated by an oscillator that generates a signal having a fixed frequency and obtained by frequency division at a predetermined frequency division ratio and the PSK modulation signal. The signal PSK · cosωt, which is the signal obtained in this way, is supplied.

  The multiplier 73-1 multiplies the oscillation output signal sinφ supplied from the variable oscillator 71 by the oscillation output signal cosωt (PSK · cosωt) which is the same signal as that supplied to the multiplier 72-2. A signal representing the multiplication result is output to adder 74-1.

  The multiplier 73-2 multiplies the oscillation output signal sinφ supplied from the variable oscillator 71 by the oscillation output signal sinωt that is the same signal as that supplied to the multiplier 72-1, and represents a multiplication result. The signal is output to the adder 74-2.

  The adder 74-1 adds the signal C · sinωt supplied from the multiplier 72-1 and the signal S · cosωt supplied from the multiplier 73-1, and a signal sin (ωt + φ) representing the addition result. Is output to a filter (low-pass filter 106-1 in FIG. 12) provided in the subsequent stage. C represents cosφ and S represents sinφ.

  That is, the output of the adder 74-1 is expressed by the following equation (3) (conversely, when the configuration for outputting the signal of sin (ωt + φ) is selected according to the equation (3), the multiplier 72-1 of FIG. , Multiplier 73-1 and adder 74-1 are selected).

  In the filter provided in the subsequent stage of the adder 74-1, the moving average of the output of the adder 74-1 is obtained in the same manner as the low-pass filter 23-1 in FIG. Based on the moving average obtained here and the moving average of the output of the adder 74-2, the control content of the variable oscillator 71 is determined as described with reference to FIGS.

  The adder 74-2 subtracts the signal S · sinωt supplied from the multiplier 73-2 from the signal C · cosωt supplied from the multiplier 72-2, and a signal cos (ωt + φ) representing the subtraction result. Is output to a filter (low-pass filter 106-2 in FIG. 12) provided in the subsequent stage.

  That is, the output of the adder 74-2 is expressed by the following expression (4) (conversely, when the configuration for outputting the signal of cos (ωt + φ) is selected according to the expression (4), the multiplier 72-2 in FIG. , Multiplier 73-2 and adder 74-2 are selected).

  The signal sin (ωt + φ) that is the output of the adder 74-1 and the signal cos (ωt + φ) that is the output of the adder 74-2 are signals that are out of phase by π / 2. It is determined how much the phase difference from the clock signal (PSK modulation signal) is. As described with reference to FIG. 3 and the like, the outputs of the EX-OR circuits 22-1 and 22-2 in FIG. 3 are out of phase by π / 2. Based on this output, A phase difference from the clock signal is determined.

  Further, it can be seen from equations (3) and (4) that a signal having a predetermined phase can be arbitrarily generated by setting predetermined values as the values of C and S. Therefore, by setting C and S in accordance with the control signal cnt, the variable oscillator 71 changes the frequency division ratio to generate the oscillation output signal. Compared to 32, it can be used as a VOC having higher resolution.

In addition, according to the frequency divider having the circuit configuration as described above, it is possible to freely create a repetitive waveform of all phases even when the value of the frequency division ratio _Ndiv is small.

  In the figure, the repetitive waveform is described as a two-input sine wave having a phase difference of 90 degrees (sin and cos). However, in principle, it is not necessary to have a phase difference of 90 degrees, and different phases ( Anything having an opposite phase) is applicable. Further, it is not necessary to be a sine wave, and can be applied to various types of repetitive waveforms such as a triangular wave and a rectangular wave. Therefore, in principle, it can be applied to an analog PLL VCO, and can also be easily applied to an NPL of a digital PLL in which an NCO having a rectangular wave output is used.

  Here, the operation principle of the circuit configuration of FIG. 9 will be further described.

  In this circuit configuration, since the inputs are sin and cos, the repetitive waveform of the output is mathematically transformed as shown in the above equations (3) and (4), and a sine wave having a changed φ phase is output. This means that if C ′ and S ′ that give φ ′ larger than the current phase φ are calculated and the circuit of FIG. 9 is applied, the frequency is temporarily increased, and conversely smaller than the current phase φ. When C ″ and S ″ giving φ ″ are given, it means that the frequency is temporarily lowered. That is, applying this principle to an oscillator indicates that a VCO or NCO can be configured. Further, it is shown that if C and S are generated with high accuracy, a repetitive waveform having an arbitrary phase can be output with any fine accuracy (granularity).

  Further, the configuration of FIG. 9 is shown as outputting two repetitive waveforms, but by using one of them, it can be widely applied not only to the Costas loop but also to a general PLL. .

  When the oscillator having the configuration of FIG. 9 is applied to the Costas loop, the block of the voltage controlled oscillator 14 of FIG. 2 or a part of the block of the NCO 27 of FIG. 3 may be replaced with the oscillator of the configuration of FIG. 10, see FIG. 1 can be applied to a normal PLL by replacing the controlled oscillator 3 of FIG. 1 with the NCO having the configuration of FIG. 9 (in this case, only the repetitive waveform on one side is used).

  FIG. 10 is a diagram showing a configuration example of a PLL in which the oscillator having the configuration of FIG. 9 is applied to the Costas loop of FIG. For example, the PLL shown in FIG. 10 is provided in the non-contact IC chip 51 in place of the DPLL 62 in FIG. The same components as those in FIGS. 2 and 9 are denoted by the same reference numerals. The voltage-controlled oscillator 14 shown in FIG. 10 has the configuration shown in FIG.

  The multiplier 11-1 (I multiplier) in FIG. 10 includes a PSK modulation signal Asin (ωt + D (t) π) input via an RF amplifier or the like provided at the subsequent stage of the antenna, and a voltage-controlled oscillator 14. The supplied oscillation output signal sin (ωt + φ) is multiplied, and the obtained signal is output to the low-pass filter 12-1.

  The multiplier 11-2 (Q multiplier) has a phase of π / 2 with reference to the PSK modulation signal Asin (ωt + D (t) π) and the signal supplied from the voltage controlled oscillator 14 to the multiplier 11-1. The delayed oscillation output signal -cos (ωt + φ) is multiplied and the obtained signal is output to the low-pass filter 12-2.

  The low-pass filter 12-1 removes the high frequency component of the signal supplied from the multiplier 11-1, outputs the obtained signal to the outside as demodulated data D (t), and outputs the PSK modulated signal and The signal is output to the multiplier 13 as a signal representing the phase comparison result (phase comparison result of the I arm) of the oscillation output signal.

  The low-pass filter 12-2 removes the high frequency component of the signal supplied from the multiplier 11-2, and the obtained signal is compared with the phase comparison result of the PSK modulation signal and the oscillation output signal (Q arm phase comparison). The result is output to the multiplier 13 as a signal.

  The multiplier 13 multiplies the signal supplied from the low-pass filter 12-1 and the signal supplied from the low-pass filter 12-2, and uses the obtained signal D (t) φ as a control signal. This is output to the variable oscillator 71 of the voltage controlled oscillator 14.

  Based on the control signal D (t) φ (corresponding to the control signal cnt in FIG. 9) supplied from the multiplier 13, the voltage controlled oscillator 14 multiplies the oscillation output signal sin (ωt + φ) by the multiplier 11-1. The oscillation output signal -cos (ωt + φ) is output to the multiplier 11-2.

  11 is a diagram showing a configuration example of a PLL in which the oscillator having the configuration of FIG. 9 is applied to the digital Costas loop of FIG. For example, the PLL shown in FIG. 11 is provided in the non-contact IC chip 51 in place of the DPLL 62 in FIG. The same components as those in FIGS. 3 and 9 are denoted by the same reference numerals. The NCO 27 shown in FIG. 11 includes the configuration shown in FIG. 9 and the oscillator 31 shown in FIG. 3, and a detailed description thereof will be omitted.

  The hard limiter 21 binarizes the PSK modulation signal and outputs the obtained binarized signal to the EX-OR circuits 22-1 and 22-2, respectively.

  The EX-OR circuit 22-1 is an exclusive logic of the binarized signal supplied from the hard limiter 21 and the oscillation output signal supplied from the binarized circuit 28-1 that binarizes the output of the NCO 27. The sum operation is performed, and the operation result is output to the low-pass filter 23-1.

  The EX-OR circuit 22-2 is an exclusive logic of the binarization signal supplied from the hard limiter 21 and the oscillation output signal supplied from the binarization circuit 28-2 that binarizes the output of the NCO 27. The sum operation is performed, and the operation result is output to the low-pass filter 23-2. From the binarization circuit 28-1, a signal whose phase is delayed by π / 2 with respect to the signal supplied to the EX-OR circuit 22-1 is supplied.

  The low-pass filter 23-1 obtains a moving average of the output of the EX-OR circuit 22-1, and outputs the obtained moving average to the ternary circuit 24-1 as a phase comparison result of the I arm. For example, if one period of a PSK modulation signal is binarized into 8 sample data, a moving average is obtained for the half period (4 sample data), and a signal representing the moving average with 5 values is obtained. The data is output to the ternary circuit 24-1.

  The low-pass filter 23-2 calculates a moving average of the output of the EX-OR circuit 22-2, and outputs the calculated moving average to the ternary circuit 24-2 as a phase comparison result of the Q arm.

  The ternary circuit 24-1 converts the moving average supplied from the low-pass filter 23-1 into, for example, a ternary value and outputs the ternized moving average to the table management unit 25.

  The ternary circuit 24-2 converts the moving average supplied from the low-pass filter 23-2 into, for example, a ternary value and outputs the ternized moving average to the table management unit 25.

  The table management unit 25 associates the control direction of the division ratio of the variable division ratio type frequency divider 32 with the phase comparison result (moving average) obtained by the low-pass filters 23-1, 23-2 and the like. The control table is managed, the control direction is determined based on the moving average supplied from the ternary circuits 24-1 and 24-2, and the control signal is output to the standardization circuit 26.

  The standardization circuit 26 removes the influence of noise by standardizing the control signal supplied from the table management unit 25 (such as averaging the edge position), and divides the standardized control signal into a variable division ratio type. Output to the device 32. The standardization of the control signal is performed, for example, every 8 samples of data that is data for one period, and represents a standardized control direction.

  The oscillator 31 constituting the NCO 27 outputs sinωt and cosωt, which are oscillation output signals having a predetermined frequency (N × Frate), to the multipliers 72-1 and 72-2 of the oscillator having the configuration shown in FIG.

  The binarization circuit 28-1 binarizes the signal sin (ωt + φ) supplied from the adder 74-1, and outputs the obtained binarization signal to the EX-OR circuit 22-1.

  The binarization circuit 28-2 binarizes the signal cos (ωt + φ) supplied from the adder 74-2, and outputs the obtained binarization signal to the EX-OR circuit 22-2.

  Next, a modified example of the DPLL 62 mounting the oscillator shown in FIG. 9 will be described.

  When the NCO having the configuration of FIG. 9 is applied to the Costas loop, a configuration of a modified version as shown in FIG. 14 can be considered. 12 and FIG. 13 are cut out configurations corresponding to the NCO 27, EX-ORs 22-1, 22-2, and low-pass filters 23-1, 23-2 in FIG. When the process of these configurations is expressed by mathematical expression excluding the low-pass filter process, the arithmetic expression is expressed by expressions (5) and (6) described later. Therefore, the circuit of FIG. 3 can be modified as the circuit of FIG. 14, but by implementing such a modification, the mounting on the logic circuit may be greatly simplified.

  As described above, each of the two signals whose phases are shifted by π / 2 and the moving average of the phase difference between the PSK modulation signals are used as a result of the phase comparison between the I arm and the Q arm. DPLL 62 can be realized if it is supplied to a management unit that manages

  FIG. 12 and FIG. 13 are diagrams schematically showing a configuration for outputting a phase comparison result between the I arm and the Q arm, respectively.

  In the configuration of FIG. 12, the signal sin (ωt + φ) generated according to the control signal and the PSK modulation signal supplied from the demodulation circuit 61 are multiplied to compare the phases of these signals. The resulting moving average is output from the low pass filter as the phase comparison result of the I arm. The calculation performed by the multiplier shown in FIG. C represents cosφ, and S represents sinφ.

  On the other hand, in the configuration of FIG. 13, the signal cos (ωt + φ) generated according to the control signal and the PSK modulation signal supplied from the demodulation circuit 61 are multiplied to compare their phases, and the comparison is made. The resulting moving average is output from the low pass filter as the Q arm phase comparison result. The calculation performed by the multiplier of FIG. 13 is shown in the following formula (6).

  A configuration equivalent to the configuration of FIG. 12 is selected according to equation (5), and a configuration equivalent to the configuration of FIG. 13 is selected according to equation (6). A configuration for outputting the result can be realized.

  FIG. 14 is a diagram illustrating a configuration example of the DPLL 62. When the PLL has such a configuration, the mounting on the logic circuit may be greatly simplified.

  The DPLL 62 in FIG. 14 includes a specific configuration for performing the calculations of the equations (5) and (6) according to the values of C and S as described with reference to FIGS.

  The hard limiter 101 binarizes the PSK modulation signal and outputs the binarized signal to the multipliers 102-1 and 102-2, respectively.

  The multiplier 102-1 multiplies the binarized signal supplied from the hard limiter 101 and the oscillation output signal sinωt supplied from the frequency divider 111, and the multiplication results are multiplied by the multipliers 103-1 and 104-. Output to 2. The calculation result of the multiplier 102-1 is expressed by PSK · sinωt.

  The multiplier 102-2 multiplies the binarized signal supplied from the hard limiter 101 and the oscillation output signal cosωt supplied from the frequency divider 111, and the multiplication results are multiplied by the multipliers 103-2 and 104-. Output to 1. The calculation result of the multiplier 102-2 is expressed by PSK · cosωt.

  The multiplier 103-1 multiplies the signal PSK · sinωt supplied from the multiplier 102-1 by the oscillation output signal cosφ supplied from the variable oscillator 110, and the multiplication result is sent to the adder 105-1. Output. The calculation result of the multiplier 103-1 is expressed by C · PSK · sinωt.

  The multiplier 103-2 multiplies the signal PSK · cosωt supplied from the multiplier 102-2 and the oscillation output signal cosφ supplied from the variable oscillator 110, and the multiplication result is sent to the adder 105-2. Output. The calculation result of the multiplier 103-2 is represented by C · PSK · cosωt.

  The multiplier 104-1 multiplies the signal PSK · cosωt supplied from the multiplier 102-2 by the oscillation output signal sinφ supplied from the variable oscillator 110, and the multiplication result is sent to the adder 105-1. Output. The calculation result of the multiplier 104-1 is represented by S · PSK · cosωt.

  The multiplier 104-2 multiplies the signal PSK · sinωt supplied from the multiplier 102-1 by the oscillation output signal sinφ supplied from the variable oscillator 110, and the multiplication result is sent to the adder 105-2. Output. The calculation result of the multiplier 104-2 is represented by S · PSK · sinωt.

  The adder 105-1 adds the signal C · PSK · sinωt supplied from the multiplier 103-1, and the signal S · PSK · cosωt supplied from the multiplier 104-1, and represents the addition result. Is output to the low-pass filter 106-1. The calculation result of the adder 105-1 is expressed by the following formula (7).

  The adder 105-2 subtracts the signal S · PSK · sinωt supplied from the multiplier 104-2 from the signal C · PSK · cosωt supplied from the multiplier 103-2, and represents a subtraction result. Is output to the low-pass filter 106-2. The calculation result of the adder 105-2 is expressed by the following equation (8).

  The low-pass filter 106-1 calculates the moving average of the output of the adder 105-1, and outputs the calculated moving average to the ternary circuit 107-1 as the phase comparison result of the I arm.

  The low-pass filter 106-2 calculates a moving average of the output of the adder 105-2, and outputs the calculated moving average to the ternary circuit 107-2 as a Q-arm phase comparison result.

  The ternary circuit 107-1 converts the moving average supplied from the low-pass filter 106-1 into, for example, a ternary value and outputs the ternized moving average to the table management unit 108.

  The ternary circuit 107-2 converts the moving average supplied from the low-pass filter 106-2 into, for example, a ternary value and outputs the ternary moving average to the table management unit 108.

  The table management unit 108 manages a control table in which the phase comparison results (moving average) obtained by the low-pass filters 106-1, 106-2, etc. are associated with the control content cnt (value of φ). Based on the moving average supplied from the ternary circuits 107-1 and 107-2, a control signal is output to the standardization circuit 109.

  The standardization circuit 109 removes the influence of noise by standardizing the control signal supplied from the table management unit 108, and outputs the standardized control signal to the variable oscillator 110.

  The variable oscillator 110 changes the value of φ in accordance with the control signal supplied from the standardization circuit 109, and oscillates the oscillation output signal represented by cosφ to the multipliers 103-1 and 103-2 and represented by sinφ. Output signals are output to multipliers 104-1 and 104-2, respectively.

The frequency divider 111 divides the oscillation output signal F _mclk supplied from an oscillator (not shown ₎ by a predetermined frequency division ratio N _div , and the oscillation output signal sinωt is supplied to the multiplier 102-1, and the oscillation output signal cosωt is Each is output to the multiplier 102-2.

  By configuring the DPLL 62 as described above, it is possible to increase the phase resolution and to ensure synchronization with the clock signal even when the frequency is high. Therefore, communication between the reader / writer can be realized at a higher transfer rate.

  In the above description, the oscillator having high resolution is realized by the configuration shown in FIG. 9, but may be realized by the configuration shown in FIG. 15, for example.

The variable dividing ratio type frequency divider 121 determines the _dividing ratio N _div according to the control signal from the outside, and the oscillation output signal F _mclk supplied from the oscillator (not shown) is determined with the determined _dividing ratio N _div. Divide the frequency.

The variable dividing ratio type frequency divider 121 outputs the obtained transmission output signal a to the multiplier 123-1, and the transmission whose phase is delayed by N · (2π / N _div ) with respect to the transmission output signal a. The output signal a ′ is output to the multiplier 124-1. Further, the variable dividing ratio type frequency divider 121 outputs a transmission output signal b whose phase is delayed by π / 2 with respect to the transmission output signal a to the multiplier 124-2, and also uses the transmission output signal b as a reference. The transmission output signal b ′ whose phase is delayed by N · (2π / N _div ) is output to the multiplier 123-2.

  The multiplier 123-1 multiplies the oscillation output signal a supplied from the variable division ratio divider 121 and the oscillation output signal A (A = f (cnt)) supplied from the variable oscillator 122. And outputs a signal representing the multiplication result to the adder 125-1. When the configuration of FIG. 15 is incorporated in the DPLL 62 of FIG. 14 in the same manner as the configuration of FIG. 9, the multiplier 123-1 is supplied with a signal obtained by multiplying the oscillation output signal a and the PSK modulation signal. It will be.

  The multiplier 123-2 multiplies the oscillation output signal b ′ supplied from the variable division ratio divider 121 and the oscillation output signal A supplied from the variable oscillator 122, and represents a multiplication result. The signal is output to the adder 125-2. When the configuration of FIG. 15 is incorporated into the DPLL 62, the multiplier 123-2 is supplied with a signal obtained by multiplying the oscillation output signal b 'and the PSK modulation signal.

  The multiplier 124-1 multiplies the transmission output signal a ′ supplied from the variable division ratio divider 121 and the oscillation output signal B supplied from the variable oscillator 122, and represents a multiplication result. The signal is output to the adder 125-1. When the configuration of FIG. 15 is incorporated in the DPLL 62, the multiplier 124-1 is supplied with a signal obtained by multiplying the oscillation output signal a ′ and the PSK modulation signal.

  The multiplier 124-2 multiplies the oscillation output signal b supplied from the variable division ratio divider 121 and the oscillation output signal B supplied from the variable oscillator 122, and represents a multiplication result. Is output to the adder 125-2. When the configuration of FIG. 15 is incorporated in the DPLL 62, the multiplier 124-2 is supplied with a signal obtained by multiplying the oscillation output signal b and the PSK modulation signal.

  The adder 125-1 adds the signal supplied from the multiplier 123-1 and the signal supplied from the multiplier 124-1, and a signal sin (ωt + φ) representing the addition result is provided in the subsequent stage. It outputs to a filter (low-pass filter 106-1 of FIG. 14).

  The adder 125-2 adds the signal supplied from the multiplier 123-2 and the signal supplied from the multiplier 124-2, and a signal cos (ωt + φ) representing the addition result is provided in the subsequent stage. It outputs to a filter (low-pass filter 106-2 of FIG. 14).

  That is, A is a function in which a value obtained by multiplying the transmission output signal a and the value obtained by multiplying the transmission output signal a ′ is represented by sin (ωt + φ). . B is a function such that a value obtained by multiplying the transmission output signal b and a value obtained by multiplying the transmission output signal b ′ is represented by cos (ωt + φ). The

  As described above, as a signal for phase comparison (a signal to be multiplied with the PSK modulation signal), not only the sin signal and the cos signal as shown in FIG. 9 but also the phase is shifted by a predetermined amount on the basis of the sin signal. The resolution of the phase can also be improved by preparing a signal and a signal whose phase is shifted by a predetermined amount with reference to the cos signal. That is, it is possible to interpolate a signal having a phase that cannot be obtained only by the sin signal and the cos signal.

  The configuration shown in FIG. 15 is included in the DPLL 62 instead of the portion corresponding to the configuration shown in FIG. 9 in the configuration shown in FIG. 15 is provided in the DPLL 62 in place of the frequency divider 111. This also makes it possible to increase the phase resolution and realize the DPLL 62 that can ensure synchronization with the clock signal even when the frequency is high.

It is a figure which shows the example of a PLL circuit. It is a figure which shows the example of a Costas loop. It is a figure which shows the example which digitized the Costas loop of FIG. It is a figure which shows the example of the signal handled by the Costas loop of FIG. It is a figure which shows what plotted the phase comparison result of I arm and Q arm. It is a figure which shows the example of a control table. It is a figure explaining the example of the output of a division ratio variable type frequency divider. It is a block diagram which shows the example of a structure of a part of non-contact IC chip to which this invention is applied. It is a figure which shows the example of a structure provided in DPLL of FIG. It is a figure which shows the structural example of PLL provided with the oscillator of FIG. FIG. 10 is a diagram illustrating another configuration example of a PLL including the oscillator of FIG. 9. It is the figure which showed typically the structure which outputs the phase comparison result of I arm. It is the figure which showed typically the structure which outputs the phase comparison result of Q arm. It is a figure which shows the structural example of DPLL of FIG. It is a figure which shows the other example of the structure provided in DPLL of FIG.

Explanation of symbols

  51 contactless IC chip, 61 demodulator, 62 DPLL, 63 CPU, 71 oscillator, 101 hard limiter, 102-1, 102-2 multiplier, 103-1, 103-2 multiplier, 104-1, 104-2 Multiplier, 105-1, 105-2 adder, 106-1, 106-2 low-pass filter, 107-1, 107-2 ternary circuit, 108 table management unit, 109 standardization circuit, 110 oscillator, 111 Divider

Claims (6)

The first waveform and the second waveform, which are two repetitive waveforms having different phases from each other, and the first waveform and the second waveform are set in association with predetermined variables, A multiplication result of the first multiplier and the second multiplier which are different from each other is obtained, a multiplication result of the first waveform and the first multiplier, and the second waveform and the second multiplier The sum of the multiplication results, the multiplication result of the first waveform and the second multiplier, and the difference between the multiplication results of the second waveform and the first multiplier are respectively calculated as phase comparison results. The phase of the oscillator is controlled by changing the predetermined variable according to the relationship between the sum and the difference as the phase comparison result, and changing the settings of the first multiplier and the second multiplier. Features an oscillator that obtains output PLL circuit. In PLL (Phase Lock Loop) circuit provided in non-contact IC (Integrated Circuit) chip,
A first signal set in association with a predetermined variable, and a second signal that is set in association with the predetermined variable and is a signal shifted in phase by π / 2 with respect to the first signal Generating means for generating
Multiplication result of the first oscillation output signal obtained by dividing the oscillation output signal of a predetermined frequency by a predetermined division ratio and the PSK (Phase Shift Keying) modulation signal obtained by demodulating the electromagnetic wave from the outside A first phase comparison result which is a phase comparison result with the first signal, a second oscillation output signal whose phase is shifted by π / 2 with respect to the first oscillation output signal, and the PKS modulation the multiplication result between the signal and a second phase comparison result is a phase comparison result between the second signal, the first signal generated by said generating means, said first oscillation output signal and The multiplication result of the PKS signal, the sum of the multiplication result of the second signal, the second oscillation output signal, and the PKS signal, the first signal, the second oscillation output signal, and the PKS Signal multiplication result, the second signal, and the first oscillation output signal. And arithmetic means for performing an operation to represent the difference between the PKS signal and the multiplication result of the PKS signal,
Control means for controlling the predetermined variable for setting the first and second signals generated by the generating means based on the first and second phase comparison results obtained by the calculation by the calculating means; A PLL circuit comprising: The control means manages information indicating the control content of the generating means in association with the first and second phase comparison results obtained by the calculation by the calculation means, and refers to the information managed. The PLL circuit according to claim 2, wherein the predetermined variable for setting the first and second signals generated by the generating unit is controlled. The first signal and the second signal are C and S represented by C = cosφ and S = sinφ, respectively, and φ is the predetermined variable composed of a phase of a required repetitive waveform. The PLL circuit according to claim 2, wherein: In an IC (Integrated Circuit) chip that communicates with a reader / writer in a contactless manner,
A first signal set in association with a predetermined variable, and a second signal that is set in association with the predetermined variable and is a signal shifted in phase by π / 2 with respect to the first signal Generating means for generating
Multiplication result of the first oscillation output signal obtained by dividing the oscillation output signal of a predetermined frequency by a predetermined division ratio and the PSK (Phase Shift Keying) modulation signal obtained by demodulating the electromagnetic wave from the outside A first phase comparison result which is a phase comparison result with the first signal, a second oscillation output signal whose phase is shifted by π / 2 with respect to the first oscillation output signal, and the PKS modulation the multiplication result between the signal and a second phase comparison result is a phase comparison result between the second signal, the first signal generated by said generating means, said first oscillation output signal and The multiplication result of the PKS signal, the sum of the multiplication result of the second signal, the second oscillation output signal, and the PKS signal, the first signal, the second oscillation output signal, and the PKS Signal multiplication result, the second signal, and the first oscillation output signal. And arithmetic means for performing an operation to represent the difference between the PKS signal and the multiplication result of the PKS signal,
Based on the first and second phase comparison results obtained by the calculation by the calculation means, the predetermined variable is changed to control the phases of the first and second signals generated by the generation means. An IC chip comprising a PLL (Phase Lock Loop) circuit having control means for performing The control means manages information indicating the control content of the generating means in association with the first and second phase comparison results obtained by the calculation by the calculation means, and refers to the information managed. The IC chip according to claim 5, wherein the phase of the first and second signals generated by the generating unit is controlled by changing the predetermined variable.

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