JPH07264161A - Demodulation circuit - Google Patents

Abstract

PURPOSE:To attain a stable operation of a synthesizer by providing a 2nd voltage controlled oscillator oscillating a reference signal and a sensitivity adjustment adder means cancelling a frequency change component of the 2nd voltage controlled oscillator with a frequency division output signal to the circuit. CONSTITUTION:A carrier reproduction section 3 gives difference data changing momentarily to a D/A converter 17. The D/A converter 17 converts the data into analog data, a sensitivity adjustment section 41 multiplies a preset value by the data and gives the product to a 1st voltage controlled oscillator 11 as a 1st frequency control signal via an adder section 42. Then a 1st output signal with a frequency corresponding to the 1st frequency control signal fed to the oscillator 11 is fed to a phase detection circuit 13 via a frequency divider 12. Furthermore, the analog signal is fed to a 2nd voltage controlled oscillator 15 as a 2nd frequency control signal via an LPF 16. Then the oscillator 15 gives a 2nd output signal with a corresponding frequency to the detection circuit 13 similarly. Thus, an AC component of the oscillator 15 is cancelled at an output side of the detection circuit 13 to avoid out of synchronism.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation circuit used in, for example, a wireless device. Recently, as an intermediate frequency of a wireless device, a frequency band having a relatively high frequency such as L band (950 MHz to 1450 MHz) and a wide band has been increasingly selected. Also, since the band is wide, there are multiple channels within the band (for example, about 2000 channels at 25 KHz intervals), and it is essential to switch the receiving channels by the frequency synthesizer in order to receive all of these channels.

At this time, it is necessary to reduce the size of the demodulation circuit and ensure stable operation of the frequency synthesizer as a constituent element.

[0003]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional example, and FIG. 7 is a block diagram of a carrier recovery circuit. In FIG. 6, (a) is a numerical process by digital processing, and (b) is a delay by digital processing. (C) is an explanatory diagram of the principle of (b) in the case of performing the binary determination of the lead.

6 and 7 will be described below. In FIG. 6, the frequency converter 63 converts the frequency of the received signal into the first intermediate frequency using the output (frequency f ₁ ) of the frequency synthesizer 62, and the frequency converter 63 via the bandpass filter 64.
Add to 65. The output signal of the frequency synthesizer 62 is synchronized with the reference signal sent from the reference oscillator 61.

The frequency converter 65 is a voltage controlled oscillator.
(Hereinafter abbreviated as VCO) Output signal sent by 66 (frequency
f ₂ ) is used to convert the frequency of the received signal to f ₃ ′, and the quadrature detector 22 is passed through the bandpass filter 67 and hybrid 21.
Add to a and 22b.

Since an output signal having a phase difference of 90 degrees sent from the oscillator 24 is applied to the quadrature detector, this detector is
22a and 22b take out Ich and Qch baseband signals from the received signals and send them to the corresponding discriminators 25a and 25b. As a result, demodulated data is obtained. However, when the modulated wave is 4PSK, only the polarity bit is extracted as the reproduced data to the outside.

All the Ich and Qch demodulated data are added to a carrier recovery circuit (hereinafter, abbreviated as a CR circuit) 3. Next, the CR circuit 3 has, for example, the configuration shown in FIGS. 7 (a) and 7 (b).

In FIG. 7 (a), discriminators 31a and 31b discriminate corresponding baseband signals, and MSB is multiplied by multipliers 32a and 32b.
Send to. Since the amplitude information of Qch and Ich is also added here, the multiplication result is added to the subtractor 34, and to what extent the current demodulated data deviates from the expected frequency (phase in the case of the phase discriminator). 6 is generated and sent to the VCO 66 of FIG. 6 as a frequency control signal via a D / A converter (not shown) and the low-pass filter 35. This allows
The VCO 66 controls the oscillation frequency so that the output frequency f ₃ ′ of the frequency converter 65 becomes f ₃ .

In FIG. 7B, input Ich and Qch
After changing the identification data of the above to the basic clock by the code converters 36a and 36b, the most significant bit of Ich and Qch is the polarity judgment part 37a, and the remaining bits are the amplitude absolute value judgment part 37.
Add to b.

Then, the EX-OR of the outputs of these judgment parts
The obtained signal is sent as a phase delay / advance signal, and the principle of judgment is as shown in Fig. 7 (c).
That is, there are orthogonal I-axis and Q-axis, and the dotted line forming an angle of 45 degrees with them is the phase delay / advance determination line, and the counterclockwise direction is the phase advance state. So in the first and third quadrants, Ich
Amplitude> Qch amplitude leads the phase (in the shaded area), and in the second and fourth quadrants, I <Q leads the phase (in the shaded area). Further, the polarities of Ich and Qch are the same in the first and third quadrants, but different in the second and fourth quadrants. From this, it is possible to detect the phase delay / advance based on the magnitude of the amplitude and the polarity information.

Therefore, this phase delay / advance information is set to the LPF.
The VCO 6 of FIG. 6 is used as a frequency control signal via (not shown).
Send to 6.

[0012]

FIG. 8 is a diagram for explaining the problem. As described above, when demodulating the PSK wave, the phase noise of the local oscillator signal used in the receiver affects the error rate of the demodulated signal, so the phase of the local oscillator signal must be fixed by the PLL circuit.

However, the PLL circuit has a frequency lower than the channel spacing (1 / N of the carrier spacing).
Since the frequency synthesizer using the reference frequency as the reference frequency is used, the multiplication order becomes high, and the loop gain becomes 1 / (multiplication order) as compared with the case where there is no multiplication, and the followability becomes slow.

In addition, from the viewpoint of cost, the high frequency part of the wireless device (circuit for frequency conversion from wireless frequency to intermediate frequency)
Is a frequency converter of the existing FM receiver (frequency stability of the local oscillator signal is poor, for example, about 10 ^-3 , and 1 MHz at 1 GHz.
The frequency fluctuation of the received signal is large.

As a method of absorbing this frequency fluctuation, AF
Although there is phase synchronization using C or PLL, PLL needs good response and wide frequency variable range.
It is difficult to get a PLL like this. So, in the past,
For example, since the frequency conversion is performed twice, the frequency is once converted to a low frequency, and the frequency fluctuation is absorbed in the frequency band in which the multiplication order becomes low, the circuit scale becomes large.

Therefore, in order to reduce the size thereof, the output signal of the voltage controlled oscillator 66 (corresponding to the voltage controlled oscillator 15 in FIG. 8) shown in FIG. 6 is applied to the phase detector 13 in FIG. 8 as a reference signal. With this configuration, the reference oscillator 61, the bandpass filter 64, and the frequency converter 65 can be eliminated, and the size can be reduced.

However, when operated in the configuration of FIG. 8, the frequency synthesizer within the dotted line cannot follow the frequency (phase) control signal generated by the CR circuit 3 with respect to the frequency change of the received signal, There was a case where the phase synchronization was lost. This is because the loop gain of the frequency synthesizer becomes 1 / (multiplication order) as described above, and the PLL cannot follow the frequency fluctuation of the received signal.

That is, with the configuration shown in FIG. 8, it is possible to make the circuit smaller than the circuit configuration of the conventional example, but there is a possibility that the PLL may be out of phase synchronization and become in an unstable operating state. There were challenges.

It is an object of the present invention to miniaturize a demodulation circuit and achieve a stable operation of a frequency synthesizer which is a constituent element of this circuit.

[0020]

FIG. 1 is a block diagram showing the principle of the first aspect of the present invention. In the figure, reference numeral 1 is a frequency synthesizer means for transmitting a phase detection output by a phase detector, using a divided output signal obtained by dividing the first output signal transmitted by the first voltage controlled oscillator and a reference signal input thereto. Reference numeral 2 denotes a detection portion for demodulating a reception signal using the first output signal, and then detecting / identifying the demodulation data by using the internally generated demodulation signal to extract demodulation data. Reference numeral 3 denotes a detection portion using the demodulation data. This is a carrier wave reproducing portion that generates phase difference data between an input received signal and a demodulation signal, then converts the phase difference data into an analog signal and sends it out.
Reference numeral 4 converts the phase difference data into an analog signal, adds the K-folded sensitivity adjustment signal to the output of the phase detection portion, and sends it as the first frequency control signal to the first voltage controlled oscillator. When the frequency synthesizer having a response speed slower than that of the controlled oscillator is out of synchronization, the frequency change component of the second voltage controlled oscillator appearing on the output side of the phase detector can be canceled by the divided output signal. Sensitivity adjusting / adding means 15 for giving such a value to K, and 15 is a second voltage controlled oscillator for sending out an output signal whose frequency changes corresponding to the inputted analog signal as the reference signal.

[0021]

2 is an explanatory view of the operation of FIG. Here, it is assumed that the response speed of the frequency synthesizer is lower than the fluctuation speed of the second voltage controlled oscillator. In addition, the reference numerals on the left side of FIG.
The waveform of the same code part inside is shown.

First, in the case where the sensitivity adjusting / adding means 4 in FIG. 1 is not provided, the analog signal (D / A converted and averaged) of the analog signal transmitted by the carrier wave reproducing portion 3 is sent. It is assumed that by adding the second frequency control signal to the second voltage control oscillator 15, the frequency fluctuation of the output signal of this oscillator is as shown in FIG.

Further, it is assumed that the frequency variation of the frequency-divided output signal fluctuates only at a speed corresponding to the bandwidth of the PLL, so that it is as shown in FIG. The phase detector 13 has a 2-
Although a signal like that shown in Fig. 2 is input, it cannot follow as a PLL under the above conditions, so the frequency difference component as shown in Fig. 2 (almost the same as the frequency fluctuation component in Fig. 2) is output as the detector output. The alternating current component that it has appears.

Next, a sensitivity adjusting / adding means 4 is provided, and a signal obtained by multiplying the differential data from the carrier wave reproducing portion 3 by K (this is called a sensitivity adjusting signal; see FIG. 2) is sent to the first voltage controlled oscillator. When added, the frequency variation of the divided output signal obtained by dividing the output signal of this oscillator is as shown in Fig. 2-.

The frequency fluctuation of the output signal of the second voltage controlled oscillator is as shown in FIG.
If the frequency fluctuation of the output signal of the first voltage controlled oscillator follows this frequency fluctuation, the above-mentioned AC component does not appear in the output signal of the phase detector, and the PLL loop is always in a synchronized state. -,, see).

Here, since the second voltage controlled oscillator has the capture range determined by the carrier recovery section 3, it is possible to follow the input frequency fluctuation within this range. The control to be carried out in the present invention is the first for the frequency fluctuation that changes within this capture range.
It is possible to follow the voltage controlled oscillator of.

The problem is that the capture range of the synthesizer means is smaller than the capture range of the carrier reproducing portion. In this case, when the first voltage controlled oscillator does not follow the output fluctuation of the second voltage controlled oscillator, a voltage proportional to the frequency fluctuation of the second voltage controlled oscillator is output to the output of the phase detector. It In this case, the synthesizer means 1 is out of synchronization. So the first
Of the frequency of the second voltage controlled oscillator (change amount of the second voltage controlled oscillator / N) is applied to the input of the voltage controlled oscillator of the second voltage controlled oscillator. The noise component is not generated in the output of the phase detector by changing the frequency controlled oscillator by the amount that can be considered.

Further, K may be set to a value such that the frequency change component of the second voltage controlled oscillator appearing on the output side of the phase detector can be canceled by the divided output signal, but in practice, it is set to the first value. The value is set to a value that minimizes the phase noise of the spectrum of the output signal of the first voltage controlled oscillator, but this value is almost (modulation sensitivity of the first voltage controlled oscillator / modulation sensitivity of the second voltage controlled oscillator). Becomes

That is, with respect to the short-term frequency fluctuation of the second voltage controlled oscillator (the above-mentioned AC component due to the frequency fluctuation generated at the time of loss of synchronization), the first voltage controlled oscillator to which the sensitivity adjustment signal is applied is applied. Since the PLL follows frequency fluctuations, it is sufficient for the PLL to follow average frequency fluctuations that are not short-term, and the unstable operation due to loss of phase synchronization is eliminated.

[0030]

FIG. 3 is a block diagram of the first embodiment of the present invention, and FIG.
Is a block diagram of the second invention, and FIG. 5 is a block diagram of the third invention.

Here, the sensitivity adjusting portion 41 and the adding portion 42 are components of the sensitivity adjusting / adding means 4. In addition, the same reference numerals denote the same objects throughout the drawings. The operation of FIGS. 3 to 5 will be described below, but the portions described in detail above will be briefly described, and the portions of the present invention will be described in detail.

In FIG. 3, for example, the CR circuit 3 having the structure shown in FIG. 7A sends the difference data which changes instantaneously and instantaneously to the D / A converter 17. The D / A converter 17 converts the analog signal, then multiplies it by a preset value in the sensitivity adjustment section 41, and sends it to the first voltage control oscillator 11 as a first frequency control control signal via the addition section 42. Add.

Therefore, the first voltage controlled oscillator 11 applies the first output signal of the frequency corresponding to the applied first frequency control signal to the phase detector 13 via the frequency divider 12. Also,
The above analog signal is passed through the low pass filter 16 to the second
Is added to the second voltage controlled oscillator 15 as the frequency control signal. Therefore, the second voltage controlled oscillator 15 also applies the second output signal of the corresponding frequency to the phase detector 13.

As a result, as described above, the AC component of the second voltage controlled oscillator (frequency fluctuation occurring at the time of loss of synchronization) can be canceled on the output side of the phase detector, and the loss of synchronization is eliminated.

The sensitivity adjusting section 41 is for varying the amplitude of the analog signal, and may be, for example, a variable gain amplifier or a voltage dividing circuit using resistors. In FIG. 4, for example, in FIG.
The CR circuit 3 configured as shown in (b) sends a binary signal of delay / advance (for example, +5 V for delay, 0 V for advance) to the sensitivity adjustment section 41 and the low-pass filter 16. To do.

Therefore, the sensitivity adjusting section sends the output to the first voltage controlled oscillator as the first frequency control signal via the adding section only when there is a delay. In addition, low pass filter 16
Averages this binary signal and sends it to the second voltage controlled oscillator as the second frequency control signal.

In the phase locked state, the output voltage of the low pass filter is 0.25V, and when it is not synchronized, it shifts from 0.25V. In FIG. 5, the output of the CR circuit 3 input to the sensitivity adjustment section 41 is a delayed / advanced binary signal (same as in FIG. 4), and the second frequency control signal input to the second voltage controlled oscillator is a differential signal. The data is converted into an analog signal and passed through the low-pass filter (same as in FIG. 3). Since each operation is the same as that described in FIG. 3 and FIG. 4, description thereof will be omitted.

That is, since the output of the phase detector is always in the synchronous state, only the component close to the DC component appears, and the AC component appearing in the asynchronous state is suppressed by adding the data from the CR circuit (sensitivity). It is necessary to set the gain K of the adjusting part 41.) Therefore, the frequency synthesizer does not need to follow the response speed of the second voltage controlled oscillator, and the response speed of the frequency synthesizer can be set relatively freely. Also, since the PLL is a synthesizer, the input frequency of the phase detector is always a constant frequency, so even if the frequency of the output signal of the first voltage controlled oscillator is changed (by changing the division ratio, Also, it is not necessary to change the gain K of the sensitivity adjustment section 41.

[0039]

As described in detail above, the present invention has an object to miniaturize a demodulation circuit and to stably operate a frequency synthesizer which is a constituent element of this circuit.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a first present invention.

FIG. 2 is an operation explanatory diagram of FIG.

FIG. 3 is a configuration diagram of an embodiment of the first present invention.

FIG. 4 is a configuration diagram of the second invention.

FIG. 5 is a configuration diagram of the third present invention.

FIG. 6 is a configuration diagram of a conventional example.

FIG. 7 is an example of a configuration diagram of a carrier recovery circuit, where (a) is a case where a numerical operation is performed by digital processing, (b) is a case where a binary judgment of delay and advance is performed by a digital processing, (c) )
Is a diagram for explaining the principle of (b).

FIG. 8 is an explanatory diagram of a problem.

[Explanation of symbols]

1 frequency synthesizer means 2 detection part 3 carrier recovery part 4 sensitivity adjustment
Adder 11 First voltage controlled oscillator 13 Phase detector 15 Second voltage controlled oscillator

Claims (2)

[Claims] 1. A phase detector (13) outputs a phase detection output by using a divided output signal obtained by dividing a first output signal sent from a first voltage controlled oscillator (11) and a reference signal inputted. And a frequency synthesizer means (1) for sending out the received signal, and a detection part for demodulating the received signal by using the first output signal, and detecting and identifying the demodulated data by using the internally generated demodulated signal.
(2) and, using the demodulated data, a carrier recovery part that generates phase difference data between the received signal input to the detection part and the demodulation signal, and then converts it to an analog signal for transmission
In a demodulation circuit having (3), a second voltage controlled oscillator (15) for transmitting an output signal whose frequency changes in response to the input analog signal as the reference signal, and the phase difference data as an analog signal. Converted to
The sensitivity adjustment signal multiplied by K (K is a positive or negative number) is added to the output of the phase detection portion and is sent to the first voltage controlled oscillator as the first frequency control signal. When the frequency synthesizer having a response speed slower than the response speed is out of synchronization, the frequency change component of the second voltage controlled oscillator appearing on the output side of the phase detector can be canceled by the divided output signal. A demodulation circuit characterized in that it is provided with a sensitivity adjusting / adding means (4) for giving various values to K. 2. When the phase difference data generated in the carrier wave reproducing portion is a binary signal with phase delay / advance, the amplitude of the binary signal is multiplied by K to obtain a sensitivity adjustment signal. The demodulation circuit according to claim 1.