JPH07263678A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH07263678A JPH07263678A JP4945694A JP4945694A JPH07263678A JP H07263678 A JPH07263678 A JP H07263678A JP 4945694 A JP4945694 A JP 4945694A JP 4945694 A JP4945694 A JP 4945694A JP H07263678 A JPH07263678 A JP H07263678A
- Authority
- JP
- Japan
- Prior art keywords
- side wall
- semiconductor substrate
- semiconductor
- insulating material
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＭＯＳ型電界効果トラ
ンジスタ（以後、ＭＯＳ型ＦＥＴと呼ぶ）等の半導体装
置の構造およびその製造方法に関し、特に、積み上げ構
造を有する半導体装置の構造およびその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device such as a MOS field effect transistor (hereinafter referred to as a MOS FET) and a method of manufacturing the same, and more particularly to a structure of a semiconductor device having a stacked structure and its manufacture. Regarding the method.
【０００２】[0002]
【従来の技術】この種の半導体装置においては、そのチ
ャネル長が短くなるのに伴って、しきい値電圧が低下す
る問題（いわゆる短チャンネル効果）がある。一般に、
短チャネル効果を抑えるためには、ソース部およびドレ
イン部における不純物領域を浅くすることが有効であ
る。例えば、チャネル長が０．１μｍ以下の場合には、
深さ０．０５μｍ程度以下の不純物領域を形成する必要
がある。ところが、従来のイオン注入技術のみでは、
０．０５μｍ程度以下のかなり浅い不純物領域を形成す
ることは困難である。これに対して、ソース・ドレイン
部にシリコンを成長させて、ＬＤＤ（Lightly Doped Dr
ain ）構造の半導体装置を形成することによって実効的
に不純物領域の深さを小さくする手段が提案されてい
る。例えば、特開昭63-263767 号公報や特開昭63-28706
4 号公報には、ＬＤＤ構造の半導体装置が記載されてい
る。特開昭63-287064 号公報にはまた、ＬＤＤ構造を改
良した構造である積み上げ構造や埋め込み構造の半導体
装置も記載されている。2. Description of the Related Art In this type of semiconductor device, there is a problem that the threshold voltage is lowered as the channel length is shortened (so-called short channel effect). In general,
In order to suppress the short channel effect, it is effective to make the impurity regions in the source part and the drain part shallow. For example, when the channel length is 0.1 μm or less,
It is necessary to form an impurity region having a depth of about 0.05 μm or less. However, with the conventional ion implantation technology alone,
It is difficult to form a fairly shallow impurity region of about 0.05 μm or less. In contrast, LDD (Lightly Doped Dr
Means for effectively reducing the depth of the impurity region by forming a semiconductor device having an ain) structure have been proposed. For example, JP-A-63-263767 and JP-A-63-28706.
Japanese Unexamined Patent Publication (Kokai) No. 4 discloses a semiconductor device having an LDD structure. Japanese Patent Laid-Open No. 63-287064 also describes a semiconductor device having a stacked structure or a buried structure which is an improved structure of the LDD structure.
【０００３】図４（ａ）〜（ｄ）は、積み上げ構造を有
する従来の半導体装置の製造方法の一例を示す工程図で
ある。以下、図４（ａ）〜（ｄ）を参照して、この製造
方法を説明する。FIGS. 4A to 4D are process diagrams showing an example of a method of manufacturing a conventional semiconductor device having a stacked structure. Hereinafter, this manufacturing method will be described with reference to FIGS.
【０００４】まず、図４（ａ）に示すように、LOCOS 法
等によってｐ型シリコン基板４０１の一部にフィールド
絶縁膜４０２を形成した後、このｐ型シリコン基板４０
１の一部を熱酸化してゲート絶縁膜４０３を形成し、ゲ
ート絶縁膜４０３上に多結晶シリコンから成るゲート電
極４０４を形成し、さらに、ゲート電極４０４の周辺に
酸化シリコン（ＳｉＯx （ｘ＞０））から成る絶縁膜４
０５を形成する。First, as shown in FIG. 4A, after forming a field insulating film 402 on a part of the p-type silicon substrate 401 by the LOCOS method or the like, the p-type silicon substrate 40 is formed.
1 is thermally oxidized to form a gate insulating film 403, a gate electrode 404 made of polycrystalline silicon is formed on the gate insulating film 403, and silicon oxide (SiO x (x > 0)) insulating film 4
Form 05.
【０００５】次に、超高真空中で８５０℃程度の熱処理
を行ってソースおよびドレインとなるｐ型シリコン基板
４０１表面の自然酸化膜やその他の汚染物質を除去す
る。これに続いて、図４（ｂ）に示すように、露出した
ｐ型シリコン基板４０１にシリコン層４０６を選択的に
エピタキシャル成長させる。Next, a heat treatment at about 850 ° C. is performed in an ultrahigh vacuum to remove the natural oxide film and other contaminants on the surface of the p-type silicon substrate 401 which will be the source and drain. Subsequently to this, as shown in FIG. 4B, a silicon layer 406 is selectively epitaxially grown on the exposed p-type silicon substrate 401.
【０００６】次いで、図４（ｃ）に示すように、シリコ
ン層４０６に砒素イオンを注入し、さらに燐イオンを注
入した後、図４（ｄ）のように、熱処理を施して砒素と
燐の拡散係数の差を利用して主に砒素を含む高濃度不純
物領域４０７と、その下に主に燐を含む低濃度不純物領
域４０８を形成する。高濃度不純物領域４０７は、低濃
度不純物領域４０８よりも高濃度に不純物を含んでい
る。Next, as shown in FIG. 4C, arsenic ions are implanted into the silicon layer 406, and phosphorus ions are further implanted. Then, as shown in FIG. 4D, heat treatment is performed to remove arsenic and phosphorus. A high-concentration impurity region 407 mainly containing arsenic and a low-concentration impurity region 408 mainly containing phosphorus are formed therebelow by utilizing the difference in diffusion coefficient. The high-concentration impurity region 407 contains impurities at a higher concentration than the low-concentration impurity region 408.
【０００７】この後、図示はしないが、上部に層間絶縁
膜を滞積し、不純物の活性化のために熱処理し、さらに
コンタクト開口部を開け、バリアメタルとこの上に形成
したシリコンを含むアルミニウムにより上部配線を形成
することで、半導体装置が完成される。After that, although not shown, an interlayer insulating film is deposited on the upper portion, heat treatment is performed to activate impurities, a contact opening is further opened, and a barrier metal and aluminum containing silicon formed on the barrier metal are formed. A semiconductor device is completed by forming an upper wiring by.
【０００８】[0008]
【発明が解決しようとする課題】以上説明した半導体装
置において、低濃度不純物領域４０８の横方向の形成長
（拡散長）は、ゲート電極４０４を覆う絶縁膜４０５の
膜厚に対して、同じかあるいは長くする必要がある。こ
れは、仮に、低濃度不純物領域４０８の形成端（拡散
端）がゲート電極４０４（ゲート絶縁膜４０３）に覆わ
れた下部領域にまで達さない場合、チャネルの両端に反
転しない領域が形成されることになり、チャネル・コン
ダクタンスが著しく低下してしまうからである。一方、
低濃度不純物領域４０８の深さ方向の拡散と横方向の拡
散とは互いに同じ拡散度で進行するため、低濃度不純物
領域４０８の横方向の拡散長を絶縁膜４０５の膜厚に対
して同じかあるいは長くする場合には、低濃度不純物領
域４０８の拡散深さはこれに見合う深さとなる。これら
のことを換言すれば、低濃度不純物領域４０８の深さ
は、絶縁膜４０５の膜厚に依存するといえる。In the semiconductor device described above, the lateral formation length (diffusion length) of the low concentration impurity region 408 is the same as the film thickness of the insulating film 405 covering the gate electrode 404. Or it needs to be long. This is because, if the formation end (diffusion end) of the low-concentration impurity region 408 does not reach the lower region covered with the gate electrode 404 (gate insulating film 403), non-inverted regions are formed at both ends of the channel. This is because the channel conductance is significantly reduced. on the other hand,
Since the diffusion in the depth direction and the diffusion in the lateral direction of the low-concentration impurity region 408 proceed with the same degree of diffusion, whether the diffusion length in the lateral direction of the low-concentration impurity region 408 is the same as the film thickness of the insulating film 405. Alternatively, when the length is increased, the diffusion depth of the low-concentration impurity region 408 becomes a depth commensurate with this. In other words, it can be said that the depth of the low concentration impurity region 408 depends on the film thickness of the insulating film 405.
【０００９】他方、選択エピタキシャル成長の方法とし
ては、超高真空気相成長法（ＵＨＶ−ＣＶＤ）が一般的
であるが、この方法を用いる場合には、図４（ｂ）に示
したごとくｐ型シリコン基板４０１にシリコン層４０６
を成長させる前に、ｐ型シリコン基板４０１表面の自然
酸化膜等を除去するために、超高真空中にて熱処理を行
わなければならない。この際に、ゲート電極４０４を覆
っている絶縁膜４０５が昇華しないためには、絶縁膜４
０５を十分な膜厚にしなければならない。例えば、従来
より通常用いられているＳｉＯ2 膜の場合には、およそ
５０ｎｍ以上の膜厚が必要である。仮に、絶縁膜４０５
の膜厚を５０ｎｍ程度よりも薄くすると、超高真空中で
の加熱の際に、膜の一部または全部が昇華してしまう虞
がある。On the other hand, as a method of selective epitaxial growth, an ultra-high vacuum vapor phase growth method (UHV-CVD) is generally used. When this method is used, p-type is used as shown in FIG. 4 (b). Silicon layer 406 on silicon substrate 401
Before growing the Pt, the heat treatment must be performed in an ultrahigh vacuum in order to remove the natural oxide film and the like on the surface of the p-type silicon substrate 401. At this time, in order that the insulating film 405 covering the gate electrode 404 does not sublime, the insulating film 4
05 must have a sufficient film thickness. For example, in the case of a SiO 2 film which has been conventionally used, a film thickness of about 50 nm or more is required. If the insulating film 405
If the film thickness is less than about 50 nm, a part or the whole of the film may be sublimated during heating in an ultrahigh vacuum.
【００１０】ここで、前述した事実を併せ考えると、低
濃度不純物領域４０８の横方向の拡散長さは絶縁膜４０
５の厚さ５０ｎｍ以上に応じた長さよりも短くすること
はできず、この結果、低濃度不純物領域４０８の深さも
横方向の拡散長に見合った深さより浅くすることはでき
ない。Considering the facts described above, the diffusion length in the lateral direction of the low concentration impurity region 408 is determined by the insulating film 40.
5 cannot be made shorter than the length corresponding to the thickness of 50 nm or more, and as a result, the depth of the low concentration impurity region 408 cannot be made shallower than the depth corresponding to the lateral diffusion length.
【００１１】以上説明したように、従来の半導体装置で
は、そのゲート電極を覆う絶縁膜の膜厚を十分に確保し
なければならないという実情によって、ソース部および
ドレイン部における低濃度不純物領域を浅くしようとし
てもその層深さが制約され、ひいては短チャネル効果を
抑止することが十分にできないという問題点がある。As described above, in the conventional semiconductor device, the low-concentration impurity regions in the source part and the drain part are made shallow due to the fact that the film thickness of the insulating film covering the gate electrode must be sufficiently secured. However, there is a problem in that the layer depth is restricted, and thus the short channel effect cannot be sufficiently suppressed.
【００１２】本発明の課題は、短チャネル効果が十分に
抑止された半導体装置を提供することである。An object of the present invention is to provide a semiconductor device in which the short channel effect is sufficiently suppressed.
【００１３】本発明の他の課題は、上記半導体装置を比
較的簡単な製造工程で製造できる半導体装置の製造方法
を提供することである。Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can manufacture the semiconductor device by a relatively simple manufacturing process.
【００１４】[0014]
【課題を解決するための手段】本発明によれば、一導電
型の半導体基板の表面上にゲート絶縁膜を介して形成さ
れたゲート電極と、絶縁材料から成り前記ゲート電極の
側面に形成された側壁と、前記側壁の外側の前記半導体
基板の表面上に形成された反対導電型の半導体層とを含
む半導体装置において、前記絶縁材料は、窒素成分を必
須成分として含むシリコン材料であることを特徴とする
半導体装置が得られる。According to the present invention, a gate electrode is formed on the surface of a semiconductor substrate of one conductivity type via a gate insulating film, and is formed on a side surface of the gate electrode made of an insulating material. In a semiconductor device including a side wall and a semiconductor layer of opposite conductivity type formed on the surface of the semiconductor substrate outside the side wall, the insulating material is a silicon material containing a nitrogen component as an essential component. A characteristic semiconductor device can be obtained.
【００１５】本発明によればまた、一導電型の半導体基
板の表面上にゲート絶縁膜を介して形成されたゲート電
極と、第１の絶縁材料から成り前記ゲート電極の側面に
形成された第１の側壁と、前記第１の側壁の外側の前記
半導体基板の表面上に形成された反対導電型の半導体層
と、第２の絶縁材料から成り前記第１の側壁の側面に形
成された第２の側壁と、少なくとも前記ゲート絶縁膜に
よって覆われる下部領域に接し、かつ、前記第２の側壁
によって覆われる下部領域の途中にわたって形成された
低濃度不純物領域と、前記低濃度不純物領域に接し、か
つ、前記低濃度不純物領域の外側領域に形成され、前記
低濃度不純物領域よりも高濃度の不純物を含む高濃度不
純物領域とを含む半導体装置において、前記第１の絶縁
材料は、窒素成分を必須成分として含むシリコン材料で
あり、前記第２の絶縁材料は、酸化シリコンである半導
体装置が得られる。According to the present invention, a gate electrode is formed on the surface of a semiconductor substrate of one conductivity type via a gate insulating film, and a first insulating material is formed on a side surface of the gate electrode. A first sidewall, a semiconductor layer of opposite conductivity type formed on the surface of the semiconductor substrate outside the first sidewall, and a second insulating material formed on a side surface of the first sidewall. A low-concentration impurity region that is in contact with at least the second sidewall and a lower region covered with the gate insulating film, and is formed in the middle of the lower region covered with the second sidewall, and a low-concentration impurity region, In a semiconductor device including a high-concentration impurity region formed outside the low-concentration impurity region and containing a higher concentration of impurities than the low-concentration impurity region, the first insulating material is a nitrogen component. A silicon material comprising as essential components, wherein the second insulating material, the semiconductor device can be obtained a silicon oxide.
【００１６】本発明によればさらに、上記各半導体装置
の製造方法が得られる。According to the present invention, further, a method of manufacturing each of the above semiconductor devices can be obtained.
【００１７】[0017]
【実施例】以下、図面を参照して、本発明の実施例によ
る半導体装置およびその製造方法を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described below with reference to the drawings.
【００１８】［実施例１］図１（ａ）〜（ｄ）は、本発
明の実施例１による半導体装置の製造方法を説明するた
めの工程図である。[Embodiment 1] FIGS. 1A to 1D are process diagrams for explaining a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention.
【００１９】以下、製造方法の説明によって、半導体装
置の構造をも説明する。The structure of the semiconductor device will be described below by explaining the manufacturing method.
【００２０】まず、図１（ａ）に示すように、LOCOS 法
等によってｐ型シリコン基板１０１の一部にフィールド
絶縁膜１０２を形成した後、このｐ型シリコン基板１０
１の一部を熱酸化してゲート絶縁膜１０３を形成し、ゲ
ート絶縁膜１０３上に、多結晶シリコンのゲート電極材
料と酸化シリコンの絶縁材料を被着形成した後にパター
ニングしてゲート電極１０４と絶縁膜１０５の積層構造
を形成する。First, as shown in FIG. 1A, after forming a field insulating film 102 on a part of a p-type silicon substrate 101 by the LOCOS method or the like, the p-type silicon substrate 10 is formed.
1 is thermally oxidized to form a gate insulating film 103, and a gate electrode material of polycrystalline silicon and an insulating material of silicon oxide are deposited on the gate insulating film 103 and then patterned to form a gate electrode 104. A laminated structure of the insulating film 105 is formed.
【００２１】次に、図１（ｂ）に示すように、窒化シリ
コンから成る絶縁材料を気相成長法等によって１０〜５
０ｎｍ程度被着形成した後に異方性エッチングしてゲー
ト電極１０４に接する側壁１０６を形成する。尚、側壁
１０６を形成する絶縁材料としては、窒化シリコンに限
らず、ＳｉＯx Ｎy （ただし、０≦ｘ≦２、かつ０＜
ｙ）等、窒素成分を必須成分として含むシリコン材料で
あればよい。このシリコン材料は、そのいわゆる昇華点
が酸化シリコンよりも高い。Next, as shown in FIG. 1 (b), an insulating material made of silicon nitride is deposited by 10 to 5 by a vapor phase growth method or the like.
After depositing and forming about 0 nm, anisotropic etching is performed to form the sidewall 106 in contact with the gate electrode 104. The insulating material forming the sidewall 106 is not limited to silicon nitride, but SiO x N y (where 0 ≦ x ≦ 2 and 0 <
Any silicon material such as y) containing a nitrogen component as an essential component may be used. The so-called sublimation point of this silicon material is higher than that of silicon oxide.
【００２２】次に、超高真空中で８５０℃程度の熱処理
を行ってソースおよびドレインとなるｐ型シリコン基板
１０１表面の自然酸化膜やその他の汚染物質を除去す
る。尚、窒化シリコンを含め、窒素成分を必須成分とす
るシリコン材料は、いわゆる昇華点が酸化シリコンに比
べて非常に高いため、側壁１０６の形成厚が１０ｎｍ程
度に薄くても、上記熱処理によって昇華してしまうこと
はない。Next, a heat treatment at about 850 ° C. is performed in an ultrahigh vacuum to remove the natural oxide film and other contaminants on the surface of the p-type silicon substrate 101 which will be the source and drain. Since silicon materials including nitrogen nitride as an essential component, including silicon nitride, have a so-called sublimation point much higher than that of silicon oxide, even if the thickness of the side wall 106 is thinned to about 10 nm, it is sublimated by the heat treatment. There is no end.
【００２３】これに続いて、図１（ｃ）に示すように、
露出したシリコン基板にシリコン層１０７を１００〜３
００ｎｍ程度の膜厚で選択的にエピタキシャル成長させ
る。尚、本発明では、露出したシリコン基板に成長させ
るシリコン層として、予めシリコン基板と反対導電型の
ものを形成してもよい。この場合には、後述する不純物
の注入工程は不要となる。Following this, as shown in FIG.
A silicon layer 107 is formed on the exposed silicon substrate by 100 to 3
Selectively epitaxially grows with a film thickness of about 00 nm. In the present invention, as the silicon layer to be grown on the exposed silicon substrate, a silicon layer having a conductivity type opposite to that of the silicon substrate may be formed in advance. In this case, the step of implanting impurities, which will be described later, becomes unnecessary.
【００２４】次に、図１（ｃ）に示すように、シリコン
層１０７に砒素イオンを注入し、さらに燐イオンを注入
した後、図１（ｄ）のように、熱処理を施して燐と砒素
の拡散係数の差を利用して主に砒素を含む高濃度不純物
領域１０８と、その下に主に燐を含む低濃度不純物領域
１０９を形成する。高濃度不純物領域１０８は、低濃度
不純物領域１０９よりも高濃度に不純物を含んでいる。Next, as shown in FIG. 1 (c), arsenic ions are implanted into the silicon layer 107, and phosphorus ions are further implanted. Then, as shown in FIG. 1 (d), heat treatment is performed to perform phosphorus and arsenic. A high-concentration impurity region 108 mainly containing arsenic and a low-concentration impurity region 109 mainly containing phosphorus are formed below the high-concentration impurity region 108 mainly utilizing arsenic. The high concentration impurity region 108 contains impurities at a higher concentration than the low concentration impurity region 109.
【００２５】尚、実施例１では、シリコン層１０７の表
面からゲート絶縁膜１０３の下までの領域に、高濃度不
純物領域１０８と低濃度不純物領域１０９との二種類か
らなる不純物領域を形成するが、本発明では、例えば、
砒素イオンのみを注入後熱処理して高濃度不純物領域の
みからなる不純物領域を形成してもよい。In the first embodiment, two types of impurity regions, the high concentration impurity region 108 and the low concentration impurity region 109, are formed in the region from the surface of the silicon layer 107 to the bottom of the gate insulating film 103. In the present invention, for example,
After implanting only arsenic ions, heat treatment may be performed to form an impurity region including only high-concentration impurity regions.
【００２６】この後、図示はしないが、上部に層間絶縁
膜を滞積し、不純物の活性化のために熱処理し、さらに
コンタクト開口部を開け、バリアメタルとこの上に形成
したシリコンを含むアルミニウムにより上部配線を形成
することで、本発明の実施例１による半導体装置が完成
される。After that, although not shown, an interlayer insulating film is deposited on the upper portion, heat treatment is performed to activate impurities, a contact opening is further opened, and a barrier metal and aluminum containing silicon formed on the barrier metal are formed. By forming the upper wiring by the above, the semiconductor device according to the first embodiment of the present invention is completed.
【００２７】また、実施例１による半導体装置は、ｎチ
ャネルＭＯＳ型ＦＥＴであるが、本発明によれば、ｐチ
ャネルＭＯＳ型ＦＥＴを製造することも可能であること
はいうまでもない。Although the semiconductor device according to the first embodiment is an n-channel MOS type FET, it goes without saying that a p-channel MOS type FET can be manufactured according to the present invention.
【００２８】［実施例２］図２（ａ）〜（ｄ）および図
３（ａ）〜（ｃ）は、本発明の実施例２による半導体装
置の製造方法を説明するための工程図である。[Embodiment 2] FIGS. 2A to 2D and FIGS. 3A to 3C are process drawings for explaining a semiconductor device manufacturing method according to Embodiment 2 of the present invention. .
【００２９】以下、製造方法の説明によって、半導体装
置の構造をも説明する。The structure of the semiconductor device will be described below by describing the manufacturing method.
【００３０】まず、図２（ａ）に示すように、LOCOS 法
等によってｐ型シリコン基板２０１の一部にフィールド
絶縁膜２０２を形成した後、このｐ型シリコン基板２０
１の一部を熱酸化してゲート絶縁膜２０３を形成し、ゲ
ート絶縁膜２０３上に、多結晶シリコンのゲート電極材
料と酸化シリコンの絶縁材料を被着形成した後にパター
ニングしてゲート電極２０４と絶縁膜２０５の積層構造
を形成する。First, as shown in FIG. 2A, after forming a field insulating film 202 on a part of the p-type silicon substrate 201 by the LOCOS method or the like, the p-type silicon substrate 20 is formed.
1 is thermally oxidized to form a gate insulating film 203, and a gate electrode material of polycrystalline silicon and an insulating material of silicon oxide are deposited and formed on the gate insulating film 203 and then patterned to form a gate electrode 204. A laminated structure of the insulating film 205 is formed.
【００３１】次に、図２（ｂ）に示すように、窒化シリ
コンから成る第１の絶縁材料を気相成長法等によって１
０〜５０ｎｍ程度被着形成した後に異方性エッチングし
てゲート電極２０４に接する第１の側壁２０６を形成す
る。尚、第１の側壁２０６を形成する第１の絶縁材料
も、実施例１における側壁１０６と同様に、窒化シリコ
ンに限らず、ＳｉＯx Ｎy （ただし、０≦ｘ≦２、かつ
０＜ｙ）等、窒素成分を必須成分として含むシリコン材
料であればよい。Next, as shown in FIG. 2 (b), a first insulating material made of silicon nitride is formed into 1 by a vapor phase growth method or the like.
After depositing about 0 to 50 nm, anisotropic etching is performed to form the first side wall 206 in contact with the gate electrode 204. The first insulating material forming the first side wall 206 is not limited to silicon nitride as in the case of the side wall 106 in the first embodiment, but may be SiO x N y (where 0 ≦ x ≦ 2 and 0 <y. ) Or the like as long as it is a silicon material containing a nitrogen component as an essential component.
【００３２】次に、超高真空中で８５０℃程度の熱処理
を行ってソースおよびドレインとなるｐ型シリコン基板
２０１表面の自然酸化膜やその他の汚染物質を除去す
る。尚、第１の側壁２０６も、窒化シリコンの昇華点が
高いことにより、形成厚が１０ｎｍ程度に薄くても、上
記熱処理によって昇華してしまうことはない。これに続
いて、図２（ｃ）に示すように、露出したシリコン基板
にシリコン層２０７を２０〜１００ｎｍ程度の膜厚で選
択的にエピタキシャル成長させる。尚、露出したシリコ
ン基板に成長させるシリコン層２０７についても、実施
例１と同様に、予めシリコン基板と反対導電型のものを
形成してもよい。この場合には、後述する第１の不純物
の注入工程は不要となる。Next, a heat treatment at about 850 ° C. is performed in an ultrahigh vacuum to remove the natural oxide film and other contaminants on the surface of the p-type silicon substrate 201 which will be the source and drain. Since the first side wall 206 also has a high sublimation point of silicon nitride, it does not sublime due to the above heat treatment even when the formed thickness is as thin as about 10 nm. Subsequently to this, as shown in FIG. 2C, a silicon layer 207 is selectively epitaxially grown on the exposed silicon substrate to a film thickness of about 20 to 100 nm. As for the silicon layer 207 to be grown on the exposed silicon substrate, a conductive type opposite to that of the silicon substrate may be formed in advance as in the first embodiment. In this case, the step of implanting a first impurity described later is unnecessary.
【００３３】以上の工程は、実施例１と同じである。The above steps are the same as in the first embodiment.
【００３４】次に、図２（ｄ）に示すように、シリコン
層２０７に第１の不純物としての燐イオンを５×１０14
／cm2 以下注入する。Next, as shown in FIG. 2D, 5 × 10 14 phosphorus ions as a first impurity are added to the silicon layer 207.
/ Cm 2 or less is injected.
【００３５】次に、図３（ａ）に示すように、第２の絶
縁材料としての酸化シリコン（ＳｉＯ2 ）を気相成長法
等によって５０〜２００ｎｍ程度被着形成した後に異方
性エッチングして、第１の側壁２０６に接する第２の側
壁２０８を形成する。尚、第２の絶縁材料としての酸化
シリコンは、例えば、窒化シリコンに比べては勿論、シ
リコンに比べてもいわゆる剛性率が低いため、後述する
熱処理を施した際に、酸化シリコンと窒化シリコンやシ
リコンとの間において各々の熱膨張係数差により生ずる
歪みを吸収する。したがって、シリコン中の結晶欠陥の
発生等が防止され、半導体装置としての信頼性に優れ
る。Next, as shown in FIG. 3 (a), silicon oxide (SiO 2 ) as a second insulating material is deposited to a thickness of about 50 to 200 nm by a vapor phase growth method or the like, and then anisotropically etched. Then, the second side wall 208 which is in contact with the first side wall 206 is formed. Since silicon oxide as the second insulating material has a lower so-called rigidity rate than, for example, not only silicon nitride but also silicon, when silicon oxide and silicon nitride or silicon nitride are used when heat treatment described later is performed. It absorbs the strain caused by the difference in the coefficient of thermal expansion between the silicon and silicon. Therefore, the occurrence of crystal defects in silicon is prevented, and the reliability of the semiconductor device is excellent.
【００３６】次に、図２（ｂ）に示すように、シリコン
層２０７に第２の不純物としての砒素イオンを１×１０
15／cm2 以上注入する。尚、本実施例では、第１の不純
物として燐イオンを注入する一方、第２の不純物として
砒素イオンを注入しているが、本発明では、第１および
第２の不純物は、それぞれ燐イオンあるいは砒素イオン
とは異なる物質でもよく、また、互いに同じ物質とする
ことも可能である。Next, as shown in FIG. 2B, arsenic ions as a second impurity are added to the silicon layer 207 by 1 × 10.
Inject at least 15 / cm 2 . In the present embodiment, phosphorus ions are implanted as the first impurities while arsenic ions are implanted as the second impurities. However, in the present invention, the first and second impurities are phosphorus ions or A substance different from arsenic ion may be used, or the same substance may be used.
【００３７】次に、図３（ｃ）に示すように、この工程
体を熱処理し、主に燐を含んだ低濃度不純物領域２１０
と、主に砒素を含んだ高濃度不純物領域２０９を形成す
る。高濃度不純物領域２０９は、低濃度不純物領域２１
０よりも高濃度に不純物を含んでいる。Next, as shown in FIG. 3C, this process body is heat-treated to form a low concentration impurity region 210 mainly containing phosphorus.
Then, a high concentration impurity region 209 mainly containing arsenic is formed. The high concentration impurity region 209 is the low concentration impurity region 21.
Impurities are contained in a concentration higher than zero.
【００３８】この後、図示はしないが、上部に層間絶縁
膜を滞積し、不純物の活性化のために熱処理し、さらに
コンタクト開口部を開け、バリアメタルとこの上に形成
したシリコンを含むアルミニウムにより上部配線を形成
することで、本発明の実施例２による半導体装置が完成
される。Thereafter, although not shown, an interlayer insulating film is deposited on the upper portion, heat treatment is performed to activate impurities, a contact opening is further opened, and a barrier metal and aluminum containing silicon formed thereon are formed. By forming the upper wiring by the above, the semiconductor device according to the second embodiment of the present invention is completed.
【００３９】以上説明した実施例２においては、側壁が
第１の側壁２０６と第２の側壁２０８との２段構造であ
るため、形成厚の薄い第１の側壁２０６によって不純物
領域の深さを浅くできることは勿論、高濃度不純物領域
２０９がゲート電極２０４から横方向に離れて形成され
るので、シリコン層２０７を十分に薄くすることができ
る。よって、積み上げ構造に特有のゲート電極とソース
およびドレインとの間の寄生容量の増加を最小限に抑え
ることができ、半導体装置としての動作速度の高速化に
有利である。また、比較的厚い第２の側壁２０８が低い
剛性率を持つ酸化シリコンから成るため、熱処理の際の
各部間の歪が吸収されてシリコン中の結晶欠陥の発生等
が防止され、半導体装置としての信頼性に優れる。In the second embodiment described above, since the side wall has a two-step structure of the first side wall 206 and the second side wall 208, the depth of the impurity region is reduced by the thin first side wall 206. The high-concentration impurity region 209 is formed laterally away from the gate electrode 204 as well as being shallow, so that the silicon layer 207 can be made sufficiently thin. Therefore, an increase in parasitic capacitance between the gate electrode and the source and drain, which is peculiar to the stacked structure, can be suppressed to a minimum, which is advantageous in increasing the operating speed of the semiconductor device. Further, since the relatively thick second side wall 208 is made of silicon oxide having a low rigidity, strain between the respective parts during heat treatment is absorbed and generation of crystal defects in silicon is prevented, and the semiconductor device as a semiconductor device is obtained. Excellent reliability.
【００４０】尚、実施例２による半導体装置もｎチャネ
ルＭＯＳ型ＦＥＴであるが、本発明によれば、ｐチャネ
ルＭＯＳ型ＦＥＴを製造することも可能であることは勿
論である。Although the semiconductor device according to the second embodiment is also an n-channel MOS type FET, it is of course possible to manufacture a p-channel MOS type FET according to the present invention.
【００４１】[0041]
【発明の効果】本発明による半導体装置においては、選
択エピタキシャル成長前に形成される側壁が酸化シリコ
ン等よりもいわゆる昇華点の高い絶縁材料から成るた
め、側壁形成後結晶成長直前の熱処理の影響に拘らず側
壁厚を薄くすることが可能になり、不純物領域の深さを
例えば１０〜３０ｎｍときわめて浅くしてもその拡散端
がチャネルに届く。したがって、電流駆動能力を犠牲に
することなく、短チャネル効果を抑えることができる。In the semiconductor device according to the present invention, the sidewall formed before selective epitaxial growth is made of an insulating material having a higher so-called sublimation point than silicon oxide or the like. Therefore, the side wall thickness can be reduced, and even if the depth of the impurity region is extremely shallow, for example, 10 to 30 nm, the diffusion edge thereof reaches the channel. Therefore, the short channel effect can be suppressed without sacrificing the current driving capability.
【００４２】また、側壁を２段構造とすれば、形成厚の
薄い第１の側壁によって不純物領域の深さを浅くできる
ことは勿論、高濃度不純物領域がゲート電極から横方向
に離れて形成されるので、半導体層を十分に薄くするこ
とができる。よって、積み上げ構造に特有のゲート電極
とソースおよびドレインとの間の寄生容量の増加を最小
限に抑えることができ、半導体装置としての動作速度の
高速化に有利である。また、比較的厚い第２の側壁が低
い剛性率を持つ酸化シリコンから成るため、熱処理の際
の各部間の歪が吸収されてシリコン中の結晶欠陥の発生
等が防止され、半導体装置としての信頼性に優れる。Further, if the side wall has a two-step structure, the depth of the impurity region can be made shallow by the first side wall having a small formation thickness, and the high-concentration impurity region is formed laterally away from the gate electrode. Therefore, the semiconductor layer can be made sufficiently thin. Therefore, an increase in parasitic capacitance between the gate electrode and the source and drain, which is peculiar to the stacked structure, can be suppressed to a minimum, which is advantageous in increasing the operating speed of the semiconductor device. In addition, since the relatively thick second side wall is made of silicon oxide having a low rigidity, the strain between the respective parts during the heat treatment is absorbed and the occurrence of crystal defects in silicon is prevented, and the reliability of the semiconductor device is improved. Excellent in performance.
【００４３】さらに、本発明による半導体装置の製造方
法によれば、短チャネル効果を十分に抑えた上記半導体
装置を比較的簡単な製造工程で製造できる。Further, according to the method of manufacturing a semiconductor device of the present invention, the semiconductor device in which the short channel effect is sufficiently suppressed can be manufactured by a relatively simple manufacturing process.
【図１】本発明の実施例１による半導体装置およびその
製造方法を説明するための工程図である。FIG. 1 is a process diagram for explaining a semiconductor device and a method for manufacturing the same according to a first embodiment of the present invention.
【図２】本発明の実施例２による半導体装置およびその
製造方法を説明するための工程図である。FIG. 2 is a process drawing for explaining a semiconductor device and a method for manufacturing the same according to a second embodiment of the present invention.
【図３】本発明の実施例２による半導体装置およびその
製造方法を説明するための工程図である。FIG. 3 is a process diagram for explaining a semiconductor device and a method for manufacturing the same according to a second embodiment of the present invention.
【図４】従来例による半導体装置およびその製造方法を
説明するための工程図である。FIG. 4 is a process diagram for explaining a semiconductor device and a method for manufacturing the same according to a conventional example.
１０１、２０１、４０１ ｐ型シリコン基板 １０２、２０２、４０２ フィールド絶縁膜 １０３、２０３、４０３ ゲート絶縁膜 １０４、２０４、４０４ ゲート電極 １０５、２０５、４０５ 絶縁膜 １０６ 側壁 ２０６ 第１の側壁 ２０８ 第２の側壁 １０７、２０７、４０６ シリコン層 １０８、２０９、４０７ 高濃度不純物領域 １０９、２１０、４０８ 低濃度不純物領域 101, 201, 401 p-type silicon substrate 102, 202, 402 field insulating film 103, 203, 403 gate insulating film 104, 204, 404 gate electrode 105, 205, 405 insulating film 106 side wall 206 first side wall 208 second Side walls 107, 207, 406 Silicon layers 108, 209, 407 High concentration impurity regions 109, 210, 408 Low concentration impurity regions
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/78 ３０１ Ｓ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 29/78 301 S
Claims (6)
絶縁膜を介して形成されたゲート電極と、絶縁材料から
成り前記ゲート電極の側面に形成された側壁と、前記側
壁の外側の前記半導体基板の表面上に形成された反対導
電型の半導体層とを含む半導体装置において、前記絶縁
材料は、窒素成分を必須成分として含むシリコン材料で
あることを特徴とする半導体装置。1. A gate electrode formed on the surface of a semiconductor substrate of one conductivity type via a gate insulating film, a sidewall formed of an insulating material on a side surface of the gate electrode, and the outside of the sidewall. A semiconductor device including a semiconductor layer of opposite conductivity type formed on a surface of a semiconductor substrate, wherein the insulating material is a silicon material containing a nitrogen component as an essential component.
絶縁膜を介して形成されたゲート電極と、第１の絶縁材
料から成り前記ゲート電極の側面に形成された第１の側
壁と、前記第１の側壁の外側の前記半導体基板の表面上
に形成された反対導電型の半導体層と、第２の絶縁材料
から成り前記第１の側壁の側面に形成された第２の側壁
と、少なくとも前記ゲート絶縁膜によって覆われる下部
領域に接し、かつ、前記第２の側壁によって覆われる下
部領域の途中にわたって形成された低濃度不純物領域
と、前記低濃度不純物領域に接し、かつ、前記低濃度不
純物領域の外側領域に形成され、前記低濃度不純物領域
よりも高濃度の不純物を含む高濃度不純物領域とを含む
半導体装置において、前記第１の絶縁材料は、窒素成分
を必須成分として含むシリコン材料であり、前記第２の
絶縁材料は、酸化シリコンである半導体装置。2. A gate electrode formed on the surface of a semiconductor substrate of one conductivity type via a gate insulating film, and a first side wall made of a first insulating material and formed on a side surface of the gate electrode. A semiconductor layer of opposite conductivity type formed on the surface of the semiconductor substrate outside the first side wall, and a second side wall made of a second insulating material and formed on a side surface of the first side wall, A low-concentration impurity region formed at least in contact with the lower region covered with the gate insulating film and formed in the middle of the lower region covered with the second sidewall, and in contact with the low-concentration impurity region, In a semiconductor device including a high-concentration impurity region formed in an outer region of the impurity region and having a higher concentration of impurities than the low-concentration impurity region, the first insulating material contains a nitrogen component as an essential component. A semiconductor device, which is a silicon material and the second insulating material is silicon oxide.
絶縁膜を介して形成されたゲート電極と、絶縁材料から
成り前記ゲート電極の側面に形成された側壁と、前記側
壁の外側の前記半導体基板の表面上に形成された反対導
電型の半導体層とを含む半導体装置を製造する半導体装
置の製造方法において、窒素成分を必須成分として含む
シリコン材料を前記絶縁材料として用いて前記側壁を形
成する工程と、前記側壁を形成した後、前記半導体基板
を真空中で熱処理して前記半導体基板の表面を清浄化す
る工程と、前記側壁の外側の前記半導体基板の表面上に
反対導電型の半導体層を形成する工程とを有することを
特徴とする半導体装置の製造方法。3. A gate electrode formed on a surface of a semiconductor substrate of one conductivity type via a gate insulating film, a side wall made of an insulating material on a side surface of the gate electrode, and the outside of the side wall. In a method of manufacturing a semiconductor device including a semiconductor layer of opposite conductivity type formed on a surface of a semiconductor substrate, a silicon material containing a nitrogen component as an essential component is used as the insulating material to form the sidewall. A step of cleaning the surface of the semiconductor substrate by heat-treating the semiconductor substrate in a vacuum after forming the side wall, and a semiconductor of opposite conductivity type on the surface of the semiconductor substrate outside the side wall. And a step of forming a layer.
て、前記側壁の外側の前記半導体基板の表面上に反対導
電型の半導体層を形成する前記工程は、前記側壁の外側
の前記半導体基板の表面上に同一導電型の半導体層およ
び真性半導体層のうちのいずれかの半導体層を形成する
前工程と、前記半導体層に不純物を注入して該半導体層
を反対導電型とする後工程とから成ることを特徴とする
半導体装置の製造方法。4. The method of manufacturing a semiconductor according to claim 3, wherein the step of forming a semiconductor layer of an opposite conductivity type on the surface of the semiconductor substrate outside the sidewall is performed on the semiconductor substrate outside the sidewall. From a pre-step of forming a semiconductor layer of the same conductivity type or an intrinsic semiconductor layer on the surface, and a post-step of injecting an impurity into the semiconductor layer to make the semiconductor layer have an opposite conductivity type. A method of manufacturing a semiconductor device, comprising:
絶縁膜を介してゲート電極を形成する工程と、前記ゲー
ト電極の側面に第１の絶縁材料から成る第１の側壁を形
成する工程と、前記第１の側壁を形成した後、前記半導
体基板を真空中で熱処理して前記半導体基板の表面を清
浄化する工程と、前記第１の側壁の外側の前記半導体基
板の表面上に反対導電型の半導体層を形成する工程と、
前記第１の側壁の側面に第２の絶縁材料から成る第２の
側壁を形成する工程と、前記第２の側壁の外側の前記半
導体層に不純物を注入する工程と、前記第２の側壁の外
側の前記半導体層に不純物を注入した後、前記半導体基
板を熱処理して該半導体基板内の不純物を活性化する工
程とを有する半導体装置の製造方法において、前記第１
の絶縁材料には、窒素成分を必須成分として含むシリコ
ン材料を用い、前記第２の絶縁材料には、酸化シリコン
を用いることを特徴とする半導体装置の製造方法。5. A step of forming a gate electrode on the surface of a semiconductor substrate of one conductivity type via a gate insulating film, and a step of forming a first side wall made of a first insulating material on a side surface of the gate electrode. And, after forming the first side wall, heat treating the semiconductor substrate in vacuum to clean the surface of the semiconductor substrate, and the step of disposing on the surface of the semiconductor substrate outside the first side wall. A step of forming a conductive type semiconductor layer,
Forming a second side wall made of a second insulating material on a side surface of the first side wall; implanting an impurity into the semiconductor layer outside the second side wall; A step of injecting impurities into the outer semiconductor layer and then heat-treating the semiconductor substrate to activate the impurities in the semiconductor substrate.
2. The method of manufacturing a semiconductor device, wherein the insulating material is a silicon material containing a nitrogen component as an essential component, and the second insulating material is silicon oxide.
て、前記第１の側壁の外側の前記半導体基板の表面上に
反対導電型の半導体層を形成する前記工程は、前記第１
の側壁の外側の前記半導体基板の表面上に同一導電型の
半導体層および真性半導体層のうちのいずれかの半導体
層を形成する前工程と、前記半導体層に不純物を注入し
て該半導体層を反対導電型とする後工程とから成ること
を特徴とする半導体装置の製造方法。6. The method of manufacturing a semiconductor according to claim 5, wherein the step of forming a semiconductor layer of opposite conductivity type on the surface of the semiconductor substrate outside the first sidewall includes the first
A step of forming a semiconductor layer of one of a semiconductor layer of the same conductivity type and an intrinsic semiconductor layer on the surface of the semiconductor substrate outside the side wall of the semiconductor layer, and implanting an impurity into the semiconductor layer to form the semiconductor layer. A method of manufacturing a semiconductor device, which comprises a post-process of setting the opposite conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6049456A JP2904253B2 (en) | 1994-03-18 | 1994-03-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6049456A JP2904253B2 (en) | 1994-03-18 | 1994-03-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07263678A true JPH07263678A (en) | 1995-10-13 |
| JP2904253B2 JP2904253B2 (en) | 1999-06-14 |
Family
ID=12831649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6049456A Expired - Fee Related JP2904253B2 (en) | 1994-03-18 | 1994-03-18 | Method for manufacturing semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP2904253B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000043199A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Fabrication method of transistor of semiconductor device |
| KR100326248B1 (en) * | 1999-06-24 | 2002-03-08 | 박종섭 | Method of fabricating slash type semiconductor memory device including plugs formed by selective epitaxial growth |
| JP2007067425A (en) * | 2006-10-05 | 2007-03-15 | Toshiba Corp | Method for manufacturing semiconductor device |
| US7579231B2 (en) | 1999-01-29 | 2009-08-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US8084338B2 (en) | 2003-06-20 | 2011-12-27 | Fujitsu Semiconductor Limited | Semiconductor device and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61176125A (en) * | 1985-01-31 | 1986-08-07 | Toshiba Corp | Defect reducing method for thin silicon thermally oxided film |
| JPH02309647A (en) * | 1989-05-24 | 1990-12-25 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1994
- 1994-03-18 JP JP6049456A patent/JP2904253B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61176125A (en) * | 1985-01-31 | 1986-08-07 | Toshiba Corp | Defect reducing method for thin silicon thermally oxided film |
| JPH02309647A (en) * | 1989-05-24 | 1990-12-25 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000043199A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Fabrication method of transistor of semiconductor device |
| US7579231B2 (en) | 1999-01-29 | 2009-08-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| KR100326248B1 (en) * | 1999-06-24 | 2002-03-08 | 박종섭 | Method of fabricating slash type semiconductor memory device including plugs formed by selective epitaxial growth |
| US8084338B2 (en) | 2003-06-20 | 2011-12-27 | Fujitsu Semiconductor Limited | Semiconductor device and manufacturing method thereof |
| JP2007067425A (en) * | 2006-10-05 | 2007-03-15 | Toshiba Corp | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2904253B2 (en) | 1999-06-14 |
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