JPH07263446A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07263446A JPH07263446A JP4623894A JP4623894A JPH07263446A JP H07263446 A JPH07263446 A JP H07263446A JP 4623894 A JP4623894 A JP 4623894A JP 4623894 A JP4623894 A JP 4623894A JP H07263446 A JPH07263446 A JP H07263446A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- pad
- aluminum
- refraction material
- tungsten
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
係り, 特にパッドに接続する配線構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a wiring structure connected to a pad.
【０００２】近年, 半導体装置の高集積化により配線の
微細化が進み, アルミニウム(Al)配線のエレクトロマイ
グレーションが問題になっている。そのために, エレク
トロマイグレーション耐性の高い配線構造が要望され
る。In recent years, wiring has become finer due to higher integration of semiconductor devices, and electromigration of aluminum (Al) wiring has become a problem. Therefore, a wiring structure with high electromigration resistance is required.
【０００３】[0003]
【従来の技術】従来の半導体装置の配線構造では，外部
導出端子となるパッドに接続する配線は, パッドと同一
層の配線膜を用いて形成している。2. Description of the Related Art In the conventional wiring structure of a semiconductor device, a wiring connected to a pad serving as an external lead terminal is formed by using a wiring film in the same layer as the pad.
【０００４】ところが, パッドは大面積のパターンであ
るので，通電にともない移動するアルミニウムの量が多
くなる。そのため，電子の流れが配線からパッドに向か
う場合, パッドに接続する配線においてもアルミニウム
移動量が多くなり，この配線にリフラクトリ材料のプラ
グを介したコンタクトがあると, その部分のアルミニウ
ムがなくなり，ボイドを生じやすくなっていた。However, since the pad is a pattern having a large area, the amount of aluminum that moves with energization increases. Therefore, when the flow of electrons goes from the wiring to the pad, the amount of aluminum migration also increases in the wiring connected to the pad. If this wiring has a contact through the plug of the refraction material, the aluminum in that portion disappears and the void is eliminated. Was likely to occur.
【０００５】[0005]
【発明が解決しようとする課題】従って, 今後さらに配
線の微細化が進むと，特にエレクトロマイグレーション
を起こしやすい配線, 特にパッドに接続する配線のエレ
クトロマイグレーション耐性を高くする必要がある。Therefore, as wirings are further miniaturized in the future, it is necessary to increase the electromigration resistance of wirings that are particularly prone to electromigration, especially wirings connected to pads.
【０００６】本発明は, パッドに接続する配線のエレク
トロマイグレーション耐性を高くすることを目的とす
る。An object of the present invention is to increase the electromigration resistance of wirings connected to pads.
【０００７】[0007]
【課題を解決するための手段】上記課題の解決は（図１
参照）， １）アルミニウム含有金属からなる配線11b と, アルミ
ニウム含有金属からなり且つ外部導出端子となるパッド
13a とが, 該配線あるいは該パッドと異なる層に形成さ
れたリフラクトリ材料からなる配線11a を介して接続さ
れている半導体装置，あるいは ２）前記リフラクトリ材料からなる配線11a と前記配線
11b あるいは前記パッド13a とが，リフラクトリ材料か
らなるプラグ12a を介して接続されている前記１記載の
半導体装置，あるいは ３）前記リフラクトリ材料がチタン，タングステン，
銀，タンタル，モリブデン，コバルト，銅，チタンタン
グステン合金，あるいはこれらの窒化物もしくは珪化物
である前記１あるいは２記載の半導体装置により達成さ
れる。[Means for Solving the Problems]
1) Wiring 11b made of aluminum-containing metal, and pad made of aluminum-containing metal and serving as an external lead terminal.
13a is connected via a wiring 11a made of a refraction material formed in a layer different from the wiring or the pad, or 2) the wiring 11a made of the refraction material and the wiring
11b or the pad 13a is connected via a plug 12a made of a refraction material, or 3) the refraction material is titanium, tungsten,
This is achieved by the semiconductor device described in 1 or 2 above, which is silver, tantalum, molybdenum, cobalt, copper, titanium-tungsten alloy, or a nitride or silicide thereof.
【０００８】[0008]
【作用】図１(A),(B) は本発明の原理説明図で, 図１
(A) は平面図, 図１(B) は断面図である。1 (A) and 1 (B) are explanatory views of the principle of the present invention.
(A) is a plan view and FIG. 1 (B) is a sectional view.
【０００９】図において， 1は半導体基板, 2は層間絶
縁膜, 11a はリフラクトリ材料の配線, 11b はアルミニ
ウムを主成分とし，パッドに接続する配線, 12a は層間
絶縁膜を貫通するスルーホールに埋め込まれたタングス
テン(W) プラグ, 13a はアルミニウムを主成分とするパ
ッドである。In the figure, 1 is a semiconductor substrate, 2 is an interlayer insulating film, 11a is a wiring of a refraction material, 11b is a wiring mainly composed of aluminum and is connected to a pad, and 12a is embedded in a through hole penetrating the interlayer insulating film. The tungsten (W) plug, 13a is a pad whose main component is aluminum.
【００１０】パッドに接続する配線11b は, パッド13a
に直接接続されないで，タングステンプラグ12a , リフ
ラクトリ材料の配線11a , タングステンプラグ12a を経
由してパッド13a に接続されている。The wiring 11b connected to the pad is the pad 13a
Instead of being directly connected to the pad 13a, it is connected to the pad 13a via the tungsten plug 12a, the wiring 11a of the refraction material, and the tungsten plug 12a.
【００１１】いま，仮に電子の流れをパッドに接続する
配線11b からパッド13a に流れるとすると，移動するア
ルミニウムの流れも配線11b からパッド13a に流れる。
本発明の構造によると, エレクトロマイグレーション耐
性の優れたリフラクトリ材料で形成された配線からパッ
ドに接続することにより，パッドのアルミニウム移動の
影響が配線11b に及ばなくなり，また反対に配線11b か
らリフラクトリ材料配線11a へのコンタクト部でのエレ
クトロマイグレーションも防ぐことができる。従って,
パッドに接続する配線11b でのエレクトロマイグレーシ
ョンを防止できる。Now, assuming that the flow of electrons flows from the wiring 11b connecting to the pad to the pad 13a, the moving aluminum flow also flows from the wiring 11b to the pad 13a.
According to the structure of the present invention, since the wiring formed of the refractory material having excellent electromigration resistance is connected to the pad, the influence of the aluminum movement of the pad does not affect the wiring 11b, and conversely, the wiring is formed from the wiring 11b to the refractory material wiring. Electromigration at the contact portion to 11a can also be prevented. Therefore,
Electromigration in the wiring 11b connected to the pad can be prevented.
【００１２】[0012]
【実施例】図２(A),(B) は本発明の実施例の説明図で,
図２(A) は平面図, 図２(B) は断面図である。EXAMPLE FIGS. 2A and 2B are explanatory views of an example of the present invention.
2A is a plan view and FIG. 2B is a sectional view.
【００１３】図において， 1は半導体基板, 2，3 は層
間絶縁膜, 21a はタングステンからなる第１層配線, 21
b はアルミニウム合金からなる第２層配線, 21c はアル
ミニウム合金からなり，パッドに接続する第３層配線,
22a, 22bは層間絶縁膜を貫通するスルーホールに埋め込
まれたタングステンプラグ, 23a はアルミニウム合金か
らなる第３層配線膜で形成されたパッドである。In the figure, 1 is a semiconductor substrate, 2 and 3 are interlayer insulating films, 21a is a first layer wiring made of tungsten, 21
b is the second layer wiring made of aluminum alloy, 21c is the third layer wiring made of aluminum alloy and connected to the pad,
22a and 22b are tungsten plugs embedded in through holes penetrating the interlayer insulating film, and 23a is a pad formed of a third layer wiring film made of an aluminum alloy.
【００１４】パッドに接続する第３層配線21c は, パッ
ド23a に直接接続されないで，タングステンプラグ22b
, 第２層配線21b , タングステンプラグ22a , リフラ
クトリ材料配線21a , タングステンプラグ22a , 第２層
配線21b , タングステンプラグ22b を経由してパッド23
a に接続されている。The third layer wiring 21c connected to the pad is not directly connected to the pad 23a, but is connected to the tungsten plug 22b.
, The second layer wiring 21b, the tungsten plug 22a, the refraction material wiring 21a, the tungsten plug 22a, the second layer wiring 21b, the tungsten plug 22b, and the pad 23.
connected to a.
【００１５】ここで, 電子の流れをパッドに接続する第
３層配線21c から第３層配線膜からなるパッド23a に流
れるとした場合, 実施例の構造によると, エレクトロマ
イグレーション耐性の優れたリフラクトリ材料の配線を
介することにより大面積のパッドのアルミニウムの移動
を防ぐことができ，かつ，パッドに接続される第３層配
線21c からリフラクトリ材料配線21a へのコンタクト部
でのエレクトロマイグレーションも防ぐことができる。
従って, パッドに接続する配線21c でのエレクトロマイ
グレーションを防止できる。Here, when the electron flow is assumed to flow from the third layer wiring 21c connecting to the pad to the pad 23a formed of the third layer wiring film, according to the structure of the embodiment, the refraction material excellent in electromigration resistance is obtained. It is possible to prevent the movement of aluminum in a pad having a large area by using the wiring of (1) and also to prevent electromigration at the contact portion from the third layer wiring (21c) connected to the pad to the refractory material wiring (21a). .
Therefore, electromigration in the wiring 21c connected to the pad can be prevented.
【００１６】ここで，パッドに接続する第３層配線21c
がその他の配線とリフラクトリ材料のプラグでコンタク
トをとっている場合に，従来はこのコンタクト部にボイ
ドが生じやすかったので，本発明の効果が特に顕著であ
る。Here, the third layer wiring 21c connected to the pad
When the other wiring and the plug made of the refraction material are in contact with each other, voids are apt to occur in this contact portion in the related art, and the effect of the present invention is particularly remarkable.
【００１７】実施例ではリフラクトリ材料としてタング
ステンを用いたが，この他に，チタン，銀，タンタル，
モリブデン，銅，チタンタングステン合金，あるいはこ
れらの窒化物もしくわ珪化物を用いても同様の効果があ
る。In the embodiment, tungsten is used as the refraction material, but in addition to this, titanium, silver, tantalum,
The same effect can be obtained by using molybdenum, copper, titanium-tungsten alloy, or their nitrides or silicides.
【００１８】[0018]
【発明の効果】本発明によれば, パッドに接続する配線
のエレクトロマイグレーション耐性を向上することがで
き，デバイスの信頼性の向上に寄与できる。According to the present invention, the electromigration resistance of the wiring connected to the pad can be improved, and the reliability of the device can be improved.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明の実施例の説明図FIG. 2 is an explanatory diagram of an embodiment of the present invention.
1 半導体基板 2, 3 層間絶縁膜 11a リフラクトリ材料の配線 11b パッドに接続するアルミニウム配線 12a 層間絶縁膜を貫通するタングステンプラグ 13a アルミニウムのパッド 21a タングステンからなる第１層配線 21b アルミニウム合金からなる第２層配線 21c アルミニウム合金からなり，パッドに接続する第
３層配線 22a, 22b 層間絶縁膜を貫通するタングステンプラグ 23a アルミニウム合金からなる第３層配線膜で形成さ
れたパッド1 Semiconductor substrate 2, 3 Interlayer insulating film 11a Wiring of refraction material 11b Aluminum wiring connected to pad 12a Tungsten plug penetrating interlayer insulating film 13a Aluminum pad 21a First layer wiring made of tungsten 21b Second layer made of aluminum alloy Wiring 21c Third layer wiring 22a, 22b made of aluminum alloy and connected to the pad Tungsten plug penetrating interlayer insulating film 23a Pad formed of third layer wiring film made of aluminum alloy
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/90 Ｂ Continuation of front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/90 B
Claims (3)
b) と, アルミニウム含有金属からなり且つ外部導出端
子となるパッド(13a) とが, 該配線(11b) あるいは該パ
ッド(13a) と異なる層に形成されたリフラクトリ材料か
らなる配線(11a) を介して接続されていることを特徴と
する半導体装置。1. A wiring (11) made of a metal containing aluminum.
b) and a pad (13a) made of an aluminum-containing metal and serving as an external lead-out terminal, via the wiring (11b) or the wiring (11a) made of a refraction material formed in a layer different from the pad (13a). A semiconductor device characterized by being connected together.
a) と前記配線(11b)あるいは前記パッド(13a) とが，リ
フラクトリ材料からなるプラグ(12a) を介して接続され
ていることを特徴とする請求項１記載の半導体装置。2. A wiring (11) made of the refraction material.
2. The semiconductor device according to claim 1, wherein a) and the wiring (11b) or the pad (13a) are connected via a plug (12a) made of a refraction material.
ステン，銀，タンタル，モリブデン，コバルト，銅，チ
タンタングステン合金，あるいはこれらの窒化物もしく
は珪化物であることを特徴とする請求項１あるいは２記
載の半導体装置。3. The semiconductor according to claim 1, wherein the refraction material is titanium, tungsten, silver, tantalum, molybdenum, cobalt, copper, titanium-tungsten alloy, or a nitride or silicide thereof. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4623894A JPH07263446A (en) | 1994-03-17 | 1994-03-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4623894A JPH07263446A (en) | 1994-03-17 | 1994-03-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07263446A true JPH07263446A (en) | 1995-10-13 |
Family
ID=12741558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4623894A Withdrawn JPH07263446A (en) | 1994-03-17 | 1994-03-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07263446A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6756675B1 (en) | 1996-08-20 | 2004-06-29 | Seiko Epson Corporation | Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal |
-
1994
- 1994-03-17 JP JP4623894A patent/JPH07263446A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6756675B1 (en) | 1996-08-20 | 2004-06-29 | Seiko Epson Corporation | Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal |
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