JPH0714874A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0714874A JPH0714874A JP5142467A JP14246793A JPH0714874A JP H0714874 A JPH0714874 A JP H0714874A JP 5142467 A JP5142467 A JP 5142467A JP 14246793 A JP14246793 A JP 14246793A JP H0714874 A JPH0714874 A JP H0714874A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- conductor layer
- hole
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
そのチップの電極構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an electrode structure of its chip.
【0002】[0002]
【従来の技術】従来より一般に利用されている、例えば
半導体集積回路チップの電極取り出し部の構造を図3
(a)の断面図及び図3(b)の平面図に示す。2. Description of the Related Art For example, a structure of an electrode lead-out portion of a semiconductor integrated circuit chip which has been generally used in the past is shown in FIG.
It is shown in the cross-sectional view of FIG. 3A and the plan view of FIG.
【0003】半導体基板8上に形成された絶縁膜10中
に内部回路の一部と電気的に接続された導体層であるパ
ッド9(ボンディング法により金属細線と接続される)
が設けられており、図3(c)で示すように、1チップ
上では、内部回路領域と同一面上に形成される構造とな
っている。A pad 9 which is a conductor layer electrically connected to a part of an internal circuit in an insulating film 10 formed on a semiconductor substrate 8 (connected to a fine metal wire by a bonding method)
Is provided, and as shown in FIG. 3C, the structure is formed on the same plane as the internal circuit region on one chip.
【0004】[0004]
【発明が解決しようとする課題】上述した従来の半導体
装置では、パッド7は図3(c)のように半導体基板8
の上部表面に設置され、図3(c)のように内部回路領
域とパッド領域が同一面上に形成されているため、小型
化をめざす高密度半導体装置の実現に対して大きな問題
点となっていた。In the conventional semiconductor device described above, the pad 7 is formed on the semiconductor substrate 8 as shown in FIG. 3 (c).
Since the internal circuit area and the pad area are formed on the same surface as shown in FIG. 3C, it is a big problem for realizing a high-density semiconductor device aiming at downsizing. Was there.
【0005】また実装する際にリード端子上の金属の突
起(バンプ)を介して半導体装置のパッドと接続するバ
ンプ法では、半導体装置のパッド面に覆いかぶせるよう
に裏返してのせるため、半導体装置を乗せるための基板
とはピン配線が逆になっていた。Further, in the bump method of connecting to a pad of a semiconductor device through a metal projection (bump) on a lead terminal at the time of mounting, since it is turned over so as to cover the pad surface of the semiconductor device, the semiconductor device is mounted. The pin wiring was opposite to the board on which the board was placed.
【0006】そのため半導体装置を乗せるための基板の
ピン配置を変更せずに実装するには、レイアウトデータ
を裏返し、ガラスマスクを再作成し、拡散をやり直して
ピン配置を合わせねばならず、よって同一機能の半導体
装置でもバンプ法とボンディング法で異なる半導体装置
を作らねばならないという問題点があった。Therefore, in order to mount the semiconductor device without changing the pin arrangement on the substrate, the layout data must be turned over, the glass mask must be recreated, and the diffusion must be performed again to match the pin arrangement. Even with a semiconductor device having a function, there is a problem that different semiconductor devices must be manufactured by the bump method and the bonding method.
【0007】本発明の目的は、従来の問題点を解消し、
小型化,高密度化が達成でき、またボンディング法、バ
ンプ法の実装にも容易に対応できる半導体装置を提供す
ることにある。The object of the present invention is to solve the problems of the prior art,
It is an object of the present invention to provide a semiconductor device that can achieve miniaturization and high density and that can easily be mounted by a bonding method or a bump method.
【0008】[0008]
【課題を解決するための手段】本発明の第1の発明の半
導体装置は、半導体基板に穴を設け、該穴に設けられた
内部回路の一部と電気的に接続された導体層が半導体基
板の表面,裏面の両面に露出していることを特徴として
構成される。According to a first aspect of the present invention, a semiconductor device is provided with a hole in a semiconductor substrate, and a conductor layer electrically connected to a part of an internal circuit provided in the hole is a semiconductor. It is characterized by being exposed on both front and back surfaces of the substrate.
【0009】また本発明の第2の発明の半導体装置は、
半導体基板に穴を設け、該穴に設けられた内部回路の一
部と電気的に接続された導体層が半導体基板の内部回路
が形成された面と異なる面に導出露出していることを特
徴として構成される。The semiconductor device of the second invention of the present invention is
A hole is formed in the semiconductor substrate, and a conductor layer electrically connected to a part of the internal circuit provided in the hole is exposed and exposed on a surface different from the surface of the semiconductor substrate on which the internal circuit is formed. Configured as.
【0010】[0010]
【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例の電極取りだし部の断面図
及び平面図並びに半導体装置の断面図である。The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view and a plan view of an electrode lead-out portion and a sectional view of a semiconductor device according to an embodiment of the present invention.
【0011】図に示すように、半導体基板1を酸化し、
表面及び裏面に酸化膜を形成し、両面の酸化膜に窓開け
を行い、この酸化膜をマスクとして両面からシリコンエ
ッチングを行い穴をあける。As shown in the figure, the semiconductor substrate 1 is oxidized,
An oxide film is formed on the front and back surfaces, windows are opened in both oxide films, and silicon oxide is punched from both surfaces using this oxide film as a mask.
【0012】次に図1(a)に示すように、穴部と半導
体基板1の表面を絶縁膜3で覆い、その中に導体層2を
形成する。この導体層2は半導体基板1の表面と裏面の
両面に露出しパッドとすることができる。Next, as shown in FIG. 1A, the hole and the surface of the semiconductor substrate 1 are covered with an insulating film 3, and a conductor layer 2 is formed therein. The conductor layer 2 is exposed on both the front surface and the back surface of the semiconductor substrate 1 and can be used as a pad.
【0013】このようにして、1チップにおいては図1
(c)に示すように半導体基板1の表面と裏面にパッド
を設けることができ、1チップでボンディング法、及び
バンプ法の何れにも対応できると共に小型、高密度化を
達成することができる。In this way, one chip is shown in FIG.
As shown in (c), pads can be provided on the front surface and the back surface of the semiconductor substrate 1, and one chip can be used for both the bonding method and the bump method and can be made compact and highly densified.
【0014】図2は本発明の他の実施例の電極取り出し
部の断面図及びその平面図並びに半導体チップの断面図
である。FIG. 2 is a sectional view of an electrode lead-out portion according to another embodiment of the present invention, a plan view thereof, and a sectional view of a semiconductor chip.
【0015】先ず、半導体基板1を酸化し、表面及び裏
面に酸化膜を形成し、両面の酸化膜に窓開けを行い、こ
の酸化膜をマスクとして両面からシリコンエッチングを
行い、穴を開ける。First, the semiconductor substrate 1 is oxidized to form an oxide film on the front surface and the back surface, windows are opened in both surfaces of the oxide film, and silicon is etched from both surfaces using the oxide film as a mask to form holes.
【0016】その後図1(a)のように穴部と半導体基
板1の表面を絶縁膜3で覆い、その中に導体層2を形成
する。又、裏面は、パッド用のガラスマスクを用い穴部
の導体層と接続したパッド7aを設け、半導体基板の裏
面に露出させることが実現できる。Thereafter, as shown in FIG. 1A, the hole and the surface of the semiconductor substrate 1 are covered with an insulating film 3, and a conductor layer 2 is formed therein. Further, the back surface can be exposed on the back surface of the semiconductor substrate by providing a pad 7a connected to the conductor layer of the hole using a glass mask for the pad.
【0017】図1(c)のように1チップにおいては、
半導体基板1の表面上に内部回路領域、半導体基板1の
裏面にはパット領域を形成することができるので半導体
装置の小型化を実現できる。In one chip as shown in FIG. 1C,
Since the internal circuit area can be formed on the front surface of the semiconductor substrate 1 and the pad area can be formed on the back surface of the semiconductor substrate 1, miniaturization of the semiconductor device can be realized.
【0018】なお本実施例では穴部の導体層に接続して
パット部を設けたが、パット部を設けることなく穴部の
裏面部を第1の実施例のように、接続部として用いるこ
とができ、半導体装置の小型化を達成できる。In this embodiment, the pad portion is provided by connecting to the conductor layer of the hole portion. However, the back surface portion of the hole portion is used as the connecting portion as in the first embodiment without providing the pad portion. Therefore, the size of the semiconductor device can be reduced.
【0019】[0019]
【発明の効果】以上説明したように、本発明の半導体装
置では、半導体基板の表面及び裏面の両面に露出したパ
ッドが形成されているのでボンディング法にて実装する
ときは半導体装置の表面の電極取り出し部を、又、バン
プ法にて実装する場合は、裏面の電極取り出し部を用い
て実装できるので同一半導体チップでどちらの実装にも
対応できる。また小型化も達成できる。As described above, in the semiconductor device of the present invention, since the exposed pads are formed on both the front surface and the back surface of the semiconductor substrate, the electrodes on the surface of the semiconductor device are mounted when mounting by the bonding method. When the lead-out portion is mounted by the bump method, the electrode lead-out portion on the back surface can be used for mounting, so that the same semiconductor chip can be used for either mounting. In addition, miniaturization can be achieved.
【0020】また裏面にパッドを設けることにより表面
領域の部品密度をおとすことなく小型化、高密度化の進
んだ半導体装置を得ることができる。Further, by providing the pad on the back surface, it is possible to obtain a semiconductor device having a small size and a high density without reducing the density of parts in the front surface region.
【図1】本発明の一実施例における電極取り出し部の断
面図およびその平面図並びに半導体装置の断面図であ
る。FIG. 1 is a cross-sectional view of an electrode lead-out portion and a plan view thereof and a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
【図2】本発明の他の実施例における電極取り出し部の
断面図およびその平面図、並びに半導体装置の断面図で
ある。2A and 2B are a cross-sectional view and a plan view of an electrode lead-out portion and a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
【図3】従来の半導体装置の一例の電極取り出し部の断
面図および平面図並びに半導体装置の断面図である。FIG. 3 is a cross-sectional view and a plan view of an electrode lead-out portion of a conventional semiconductor device, and a cross-sectional view of the semiconductor device.
1,6 半導体基板 2,7,7a 導体層 3,8 絶縁膜 4,9,9a パッド用導体 5,10,10a パッド開口部 11 導体配線 12 導体配線(基板穴あけ部) 1,6 Semiconductor substrate 2,7,7a Conductor layer 3,8 Insulating film 4,9,9a Pad conductor 5,10,10a Pad opening 11 Conductor wiring 12 Conductor wiring (board hole)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/41 7376−4M H01L 29/44 C ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication location H01L 29/41 7376-4M H01L 29/44 C
Claims (3)
体層を有する半導体装置において、半導体基板に穴を設
け該穴に設けられ内部回路の一部と電気的に接続された
導体層が半導体基板の表面、裏面の両面に露出している
ことを特徴とする半導体装置。1. A semiconductor device having a conductor layer electrically connected to a part of an internal circuit, wherein a conductor layer is provided in the semiconductor substrate and is electrically connected to a part of the internal circuit. Is exposed on both the front surface and the back surface of the semiconductor substrate.
体層を有する半導体装置において、半導体基板に穴を設
け、該穴に設けられ内部回路の一部と電気的に接続され
た導体層が半導体基板の内部回路が形成された面と異な
る面に導出露出していることを特徴とする半導体装置。2. A semiconductor device having a conductor layer electrically connected to a part of an internal circuit, wherein a hole is provided in a semiconductor substrate, and a conductor provided in the hole and electrically connected to a part of the internal circuit. A semiconductor device, wherein a layer is exposed and exposed on a surface of the semiconductor substrate different from a surface on which an internal circuit is formed.
基板表面を絶縁膜で覆い裏面は穴部の導体層と接続した
パッドが露出して設けられていることを特徴とする請求
項2記載の半導体装置。3. The surface of the hole in which the conductor layer is formed and the surface of the substrate are covered with an insulating film, and a pad connected to the conductor layer of the hole is exposed on the back surface. 2. The semiconductor device according to 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5142467A JPH0714874A (en) | 1993-06-15 | 1993-06-15 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5142467A JPH0714874A (en) | 1993-06-15 | 1993-06-15 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0714874A true JPH0714874A (en) | 1995-01-17 |
Family
ID=15315999
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5142467A Withdrawn JPH0714874A (en) | 1993-06-15 | 1993-06-15 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0714874A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998044319A1 (en) * | 1997-04-03 | 1998-10-08 | Yamatake Corporation | Circuit board and detector, and method for manufacturing the same |
US6113927A (en) * | 1997-01-06 | 2000-09-05 | Mitsubishi Gas Chemical Company, Inc. | Package and packaging method for aqueous liquid materials |
-
1993
- 1993-06-15 JP JP5142467A patent/JPH0714874A/en not_active Withdrawn
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6113927A (en) * | 1997-01-06 | 2000-09-05 | Mitsubishi Gas Chemical Company, Inc. | Package and packaging method for aqueous liquid materials |
WO1998044319A1 (en) * | 1997-04-03 | 1998-10-08 | Yamatake Corporation | Circuit board and detector, and method for manufacturing the same |
US6353262B1 (en) | 1997-04-03 | 2002-03-05 | Yamatake Corporation | Circuit substrate, detector, and method of manufacturing the same |
KR100337658B1 (en) * | 1997-04-03 | 2002-05-24 | 사토 요시하루 | Circuit board and detector, and method for manufacturing the same |
US6475821B2 (en) | 1997-04-03 | 2002-11-05 | Yamatake Corporation | Circuit substrate, detector, and method of manufacturing the same |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000905 |