JPH05259306A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05259306A JPH05259306A JP5331192A JP5331192A JPH05259306A JP H05259306 A JPH05259306 A JP H05259306A JP 5331192 A JP5331192 A JP 5331192A JP 5331192 A JP5331192 A JP 5331192A JP H05259306 A JPH05259306 A JP H05259306A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- base
- semiconductor device
- external circuit
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に係り、特
に、パッケージの２以上の面に端子が配設されてパッケ
ージが回路基板に平行に実装される半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which terminals are provided on two or more surfaces of a package and the package is mounted parallel to a circuit board.
【０００２】近年、半導体装置の高集積化、高機能化に
伴いその端子数が増加した結果、パッケージの２以上の
外側面に外部回路基板と導通可能に多数の端子が配設さ
れ、回路基板に平行にパッケージが実装される半導体装
置が広く使用されている。これらの半導体装置は、回路
基板をより小型化するために回路基板上での専有面積の
小さなものが要求されている。In recent years, the number of terminals has increased as semiconductor devices have become highly integrated and highly functionalized. As a result, a large number of terminals are arranged on two or more outer surfaces of the package so as to be electrically conductive to an external circuit board, and the circuit board is provided. A semiconductor device in which a package is mounted in parallel with is widely used. These semiconductor devices are required to have a small occupied area on the circuit board in order to further miniaturize the circuit board.
【０００３】[0003]
【従来の技術】図２は従来の半導体装置の一例の構成図
である。図２（Ｂ）は底面図であり、図２（Ａ）は図２
（Ｂ）中II−II′線における縦断面図である。なお、図
２（Ａ）は、ＬＣＣ(Leadless Chip Carrier) パッケー
ジにより構成される半導体装置１が、回路基板１０に実
装された状態を表す。2. Description of the Related Art FIG. 2 is a block diagram of an example of a conventional semiconductor device. 2 (B) is a bottom view, and FIG. 2 (A) is shown in FIG.
FIG. 7B is a vertical sectional view taken along the line II-II ′ in FIG. Note that FIG. 2A shows a state in which the semiconductor device 1 configured by an LCC (Leadless Chip Carrier) package is mounted on the circuit board 10.
【０００４】ベース３はプリント板プラスチック或いは
積層セラミックで構成されたもので平板状の形状であ
り、上面中央部には凹部３ａが形成され、また四方の外
側面１５1,１５2,１５3,１５4 には夫々複数のＵ字溝４
（以下、サイドノッチと称する）が形成されており、そ
の底面３ｂは平坦面とされている。凹部３ａには半導体
チップ２が接着剤により固着され、半導体チップ２とメ
タライズ層５はワイヤ６によりワイヤボンディングされ
接続されている。メタライズ層５はベース３の表面が金
属化されてなり、ベース３の上面よりサイドノッチ４内
を経由してベース３の底面３ｂの外縁部までに形成され
ている。底面３ｂにはメタライズ層５により略長方形の
パッド７が形成される。The base 3 is made of printed circuit board plastic or laminated ceramics and has a flat plate shape. A concave portion 3a is formed in the central portion of the upper surface, and the four outer surfaces 15 1 , 15 2 , 15 3 , 15 4 has a plurality of U-shaped grooves 4 respectively
(Hereinafter, referred to as side notch) is formed, and its bottom surface 3b is a flat surface. The semiconductor chip 2 is fixed to the recess 3a with an adhesive, and the semiconductor chip 2 and the metallized layer 5 are connected by wire bonding with a wire 6. The metallized layer 5 is formed by metallizing the surface of the base 3, and is formed from the upper surface of the base 3 through the inside of the side notch 4 to the outer edge of the bottom surface 3b of the base 3. The metallization layer 5 forms a substantially rectangular pad 7 on the bottom surface 3b.
【０００５】パッド７は回路基板実装時の半田付け用端
子であり、回路基板１０にはパッド７の位置に対応して
端子１１が配置されている。端子１１にクリーム半田を
塗布して半導体装置１を載置しリフロー半田付けするこ
とにより、回路基板１０に半導体装置１が実装される。The pad 7 is a terminal for soldering when the circuit board is mounted, and the terminal 11 is arranged on the circuit board 10 in correspondence with the position of the pad 7. The semiconductor device 1 is mounted on the circuit board 10 by applying cream solder to the terminals 11 and mounting the semiconductor device 1 and performing reflow soldering.
【０００６】このとき、メタライズ層５はサイドノッチ
４内に形成されているためベース３の外側面１５1,１５
2,１５3,１５4 から突出しない。したがって、回路基板
１０上で半導体装置１に近接して他の電気部品を配置し
てたとえ接触しても、メタライズ層５がショートするこ
とがない。At this time, since the metallized layer 5 is formed in the side notch 4, the outer surface 15 1 , 15 of the base 3 is formed.
It does not protrude from 2 , 15 3 and 15 4 . Therefore, even if another electric component is arranged close to the semiconductor device 1 on the circuit board 10 and comes into contact with the semiconductor device 1, the metallized layer 5 is not short-circuited.
【０００７】なお、ベース３がプリント板プラスチック
の場合、半導体チップ２とワイヤ６とは樹脂製の封止材
８に覆われて封止されるが、このときに封止材８が流れ
出さないように枠状の突出部９が、ベース３の上面に形
成されている。また、ベース３がセラミックの場合、半
導体チップ２を擁する凹部３ａを密封するためのキャッ
プの接着面として枠状の突出部９をベース３の上面に形
成する。When the base 3 is a printed circuit board plastic, the semiconductor chip 2 and the wires 6 are covered with a sealing material 8 made of resin to be sealed, but at this time, the sealing material 8 does not flow out. Thus, the frame-shaped protruding portion 9 is formed on the upper surface of the base 3. When the base 3 is ceramic, a frame-shaped protruding portion 9 is formed on the upper surface of the base 3 as an adhesive surface of a cap for sealing the recess 3a holding the semiconductor chip 2.
【０００８】ところで、図２においては簡単のために半
導体装置１は２２端子構成としたが、マイクロコンピュ
ータ、ＡＳＩＣ（Application Specific Integrated Ci
rcuit)等のロジック部を有するＬＳI(Large Scale Inte
gration)チップを搭載する半導体装置は入出力信号用の
端子(I／Ｏ端子）の数が多く、例えば２万ゲートのゲー
トアレイの場合、その数は３００端子近くにも及ぶ。In FIG. 2, the semiconductor device 1 has a 22-terminal structure for simplification, but a microcomputer and an ASIC (Application Specific Integrated Ci
LSI (Large Scale Inte) which has logic part such as rcuit)
A semiconductor device having a gration) chip has a large number of input / output signal terminals (I / O terminals). For example, in the case of a gate array of 20,000 gates, the number reaches nearly 300 terminals.
【０００９】またこれらの半導体装置は回路基板実装用
の端子以外にも多数の試験用の端子を有しており、近
年、半導体装置の高集積化、高機能化にともない半導体
装置の端子数は益々増加する傾向にある。Further, these semiconductor devices have a large number of terminals for testing in addition to the terminals for mounting on a circuit board. In recent years, the number of terminals of the semiconductor device has been increased due to higher integration and higher functionality of the semiconductor device. It tends to increase more and more.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら上記従来
の半導体装置によれば、ベース３の底面３ｂは平坦とさ
れているために、図２（Ａ）に示す回路基板実装状態で
は回路基板１０の表面とベース３の底面３ｂとの間には
殆ど隙間がない。このため、回路基板１０に電気部品を
半田付けした後にこれを洗浄する際に洗浄液が回路基板
１０の表面とベース３の底面３ｂとの間に流入すること
が困難であり、この部分は活性剤、フラックス等の残渣
により汚れたままとされていた。したがって、回路基板
の洗浄後に熱処理すると活性剤中のハロゲン元素がイオ
ン化することにより回路基板上の金属導体が腐食して絶
縁抵抗が低下し、回路基板の特性が劣化する問題があ
る。However, according to the above-mentioned conventional semiconductor device, since the bottom surface 3b of the base 3 is flat, the surface of the circuit board 10 in the circuit board mounted state shown in FIG. 2 (A). There is almost no gap between the base and the bottom surface 3b of the base 3. For this reason, it is difficult for the cleaning liquid to flow between the surface of the circuit board 10 and the bottom surface 3b of the base 3 when the electrical parts are soldered to the circuit board 10 and then washed. It was left unclean by residues such as flux. Therefore, when the heat treatment is performed after cleaning the circuit board, the halogen element in the activator is ionized to corrode the metal conductor on the circuit board, lowering the insulation resistance and deteriorating the characteristics of the circuit board.
【００１１】また、ベース３の底面３ｂの外縁部に一列
に半田付け用のパッド７（端子）が形成されるので、半
導体チップ２が高集積化されて端子数が増加するに連れ
て、半導体チップ２の寸法は小さくてもパッケージ寸法
は端子数に応じた大きなものにしなければならず、回路
基板の高密度化の妨げとなる問題がある。Further, since the pads 7 (terminals) for soldering are formed in a line on the outer edge portion of the bottom surface 3b of the base 3, the semiconductor chips 2 are highly integrated and the number of terminals is increased. Even if the size of the chip 2 is small, the package size must be large according to the number of terminals, which poses a problem of impeding the high density of the circuit board.
【００１２】上記の点に鑑み本発明では、回路基板に実
装した際、回路基板の洗浄を確実に行えてその特性を劣
化させることがなく、また端子数が増加してもパッケー
ジ寸法を徒に増大させずに回路基板の高密度化の妨げと
なることのない半導体装置を提供することを目的とす
る。In view of the above points, according to the present invention, when mounted on a circuit board, the circuit board can be reliably washed without deteriorating its characteristics, and the package size is reduced even if the number of terminals is increased. It is an object of the present invention to provide a semiconductor device which does not hinder high density of a circuit board without increasing the number.
【００１３】[0013]
【課題を解決するための手段】上記の問題は以下のとお
り構成することにより解決される。The above-mentioned problems can be solved by the following constitution.
【００１４】すなわち、請求項１の発明では、半導体チ
ップが載置されるベースと一端を半導体チップと電気的
に接続され他端がベースの外部と導通可能となるようベ
ースの２以上の外側面に配設された導電部材とを具備し
た半導体装置において、導電部材の他端が外部回路基板
と導通可能なよう外部回路基板にベースを配設した時に
外部回路基板に当接して外部回路基板とベースの外部回
路基板に対向する底面との間にベースの外側と連通する
空隙部を構成するようベースの底面より突出して設けら
れた段部を設けた。That is, according to the first aspect of the invention, the base on which the semiconductor chip is mounted and one end thereof are electrically connected to the semiconductor chip, and the other end thereof is electrically connected to the outside of the base so that two or more outer surfaces of the base are electrically connected. In a semiconductor device including a conductive member disposed on the external circuit board, when the base is arranged on the external circuit board so that the other end of the conductive member can be electrically connected to the external circuit board, A step portion provided so as to project from the bottom surface of the base is provided between the bottom surface of the base facing the external circuit board and a space communicating with the outside of the base.
【００１５】また、請求項２の発明では、上記半導体装
置において、導電部材の他端が外部回路基板と導通可能
なよう外部回路基板にベースを配設した時にベースの外
部回路基板に対向する底面に、一端が半導体チップと電
気的に接続され他端がベースの外部と導通可能とされる
テスト用端子を更に設けた。According to a second aspect of the present invention, in the above semiconductor device, a bottom surface of the base facing the external circuit board when the base is arranged on the external circuit board so that the other end of the conductive member can be electrically connected to the external circuit board. In addition, a test terminal having one end electrically connected to the semiconductor chip and the other end electrically connected to the outside of the base is further provided.
【００１６】[0016]
【作用】請求項１の発明によれば、半導体装置を外部回
路基板に例えば半田付けして実装した際に回路基板と半
導体装置のベースの外部回路基板に対向する底面との間
に空隙部が構成され、この空隙部はベースの外側と連通
しているために、例えば回路基板の洗浄液等がベースの
外側から上記空隙部に流入可能となる。According to the invention of claim 1, when the semiconductor device is mounted on the external circuit board by soldering, for example, a space is provided between the circuit board and the bottom surface of the base of the semiconductor device facing the external circuit board. Since this void is communicated with the outside of the base, for example, a cleaning liquid for the circuit board can flow into the void from the outside of the base.
【００１７】また請求項２の発明によれば、ベースが外
部回路基板上に配設される際に外部回路基板と導通され
る導電部材はベースの外側面に配設され、これにより半
導体チップと外部回路基板と導通して信号が入出力さ
れ、一方、半導体チップと電気的に接続されてべースの
外部と導通可能な半導体チップのテスト用端子はべース
の外部回路基板に対向する底面に配設される。According to the second aspect of the present invention, the conductive member, which is electrically connected to the external circuit board when the base is arranged on the external circuit board, is arranged on the outer surface of the base. The test terminals of the semiconductor chip, which are electrically connected to the semiconductor chip and can be electrically connected to the outside of the base, are opposed to the external circuit board of the base. It is arranged on the bottom.
【００１８】[0018]
【実施例】図１は本発明の一実施例の構成図である。図
１（Ｂ）は底面図であり、図１（Ａ）は図１（Ｂ）中Ｉ
−Ｉ′線における縦断面図である。なお、図１（Ａ）
は、ＬＣＣパッケージにより構成される半導体装置１２
が回路基板１０に実装された状態を表す。両図におい
て、図２に示した従来の半導体装置１と同一構成部分に
は同一符号を付してある。1 is a block diagram of an embodiment of the present invention. 1 (B) is a bottom view, and FIG. 1 (A) is I in FIG. 1 (B).
It is a longitudinal cross-sectional view taken along the line -I '. Note that FIG. 1 (A)
Is a semiconductor device 12 including an LCC package.
Represents the state of being mounted on the circuit board 10. In both figures, the same components as those of the conventional semiconductor device 1 shown in FIG. 2 are designated by the same reference numerals.
【００１９】ベース１３はプリント板プラスチック或い
は積層セラミックで構成されたものであり、上面中央部
には凹部１３ａが形成され、四方の外側面１５1,１５2,
１５ 3,１５4 には夫々複数のサイドノッチ４が形成さ
れ、またベース１３の底面１３ｂの四方の外縁部には段
部１４1,１４2,１４3,１４4 が形成されている。各段部
は、図２に示した平板状のベース３の底面の四隅及び中
央部を平坦に切削加工することにより形成され、各段部
の底面はもちろん平坦とされている。The base 13 is a printed board plastic or
Is composed of laminated ceramics
The recess 13a is formed in the1, 152,
15 3, 15FourEach side has a plurality of side notches 4.
In addition, a step is formed on the four outer edges of the bottom surface 13b of the base 13.
Part 141, 142, 143, 14FourAre formed. Each step
Are the four corners and the center of the bottom surface of the flat base 3 shown in FIG.
It is formed by cutting the central part flat, and each step
The bottom of the is of course flat.
【００２０】これによりベース１３の底面１３ｂの四隅
には、段部１４1,１４2 の間に流入通路１７1 が、段部
１４2,１４3 の間に流入通路１７2 が、段部１４3,１４
4 の間に流入通路１７3 が、段部１４4,１４1 の間に流
入通路１７4 が形成される。各流入通路はベース１３の
底面１３ｂの中央部を介し連通している。また、各流入
通路は図示の通りベース１３の外側にしだい拡大する開
口を有している。[0020] The four corners of this the bottom 13b of the base 13, the stepped portion 14 1, 14 inflow passage 17 1 between the 2, inlet passage 17 2 between the stepped portions 14 2, 14 3, stepped portions 14 Three , fourteen
An inflow passage 17 3 is formed between the step portions 14 4 and 14 1 , and an inflow passage 17 4 is formed between the step portions 14 4 and 14 1 . The respective inflow passages communicate with each other through the central portion of the bottom surface 13b of the base 13. Further, each inflow passage has an opening that gradually expands to the outside of the base 13 as shown.
【００２１】ワイヤ６により半導体チップ２と接続され
たメタライズ層５は、ベース３の上面よりサイドノッチ
４内を経由してベース３の底面に形成された段部１４1,
１４ 2,１４3,１４4 に到り、各段部にはメタライズ層５
により略長方形のパッド７が夫々形成される。パッド７
が回路基板１０に配設された端子１１に半田付けされ
て、図１（Ａ）に示すとおり半導体装置１２が回路基板
１０に実装される。Connected to the semiconductor chip 2 by the wire 6.
The metallization layer 5 has side notches from the upper surface of the base 3.
Stepped portion 14 formed on the bottom surface of the base 3 via the inside of 41,
14 2, 143, 14FourAnd metallization layer 5 on each step
Thus, substantially rectangular pads 7 are formed. Pad 7
Is soldered to the terminals 11 arranged on the circuit board 10.
As shown in FIG. 1A, the semiconductor device 12 is a circuit board.
It is implemented in 10.
【００２２】この基板実装状態でベース１３の底面１３
ｂの段部１４1,１４2,１４3,１４4が回路基板１０に当
接することにより、回路基板１０とベース１３との間に
空隙部１６が形成される。この空隙部１６は、流入通路
１７1,１７2,１７3,１７4 を介してベース１３の外側の
空間と連通する。In this board-mounted state, the bottom surface 13 of the base 13 is
The step portions 14 1 , 14 2 , 14 3 , 14 4 of b are brought into contact with the circuit board 10 to form a space 16 between the circuit board 10 and the base 13. The space 16 communicates with the space outside the base 13 via the inflow passages 17 1 , 17 2 , 17 3 , 17 4 .
【００２３】したがって、半導体装置１２が回路基板１
０に実装された状態で、流入通路１７1,１７2,１７3,１
７4 を介してベース１３の外側から回路基板１０とベー
ス１３の底面１３ｂとの間の空隙部１６に洗浄液が流入
することができる。このため、回路基板１０のベース１
３の下となる部分を洗浄することができるので、この部
分に金属導体パターンが配設されていても金属導体パタ
ーンが基板の熱処理により腐食することがなく回路基板
の特性も劣化しない。Therefore, the semiconductor device 12 is connected to the circuit board 1.
0, the inflow passages 17 1 , 17 2 , 17 3 , 1,
7 4 can cleaning liquid flowing into the gap portion 16 between the outer base 13 of the bottom surface 13b of the circuit board 10 and the base 13 via a. Therefore, the base 1 of the circuit board 10
Since the portion below 3 can be washed, even if the metal conductor pattern is provided in this portion, the metal conductor pattern is not corroded by the heat treatment of the substrate and the characteristics of the circuit board are not deteriorated.
【００２４】またベース１３の底面１３ｂには、段部１
４1 の図中右側及び段部１４3 の図中左側に夫々複数の
テスト用端子１８が設けられている。テスト用端子１８
は、ベース１３上面より底面１３ｂに貫通して設けられ
たスルーホール１９を介してベース１３上面のメタライ
ズ層５と導通している。メタライズ層５はワイヤ６によ
り半導体チップ２と接続されているので、テスト用端子
１８は半導体チップ２と導通しており、半導体チップ２
よりのテスト信号をテスト用端子１８より取り出すこと
ができる。On the bottom surface 13b of the base 13, the stepped portion 1
A plurality of test terminals 18 are provided on the right side of 4 1 and the left side of step 14 3 in the figure, respectively. Test terminal 18
Is electrically connected to the metallized layer 5 on the upper surface of the base 13 through a through hole 19 formed so as to penetrate from the upper surface of the base 13 to the bottom surface 13b. Since the metallized layer 5 is connected to the semiconductor chip 2 by the wire 6, the test terminal 18 is electrically connected to the semiconductor chip 2 and the semiconductor chip 2
The test signal can be taken out from the test terminal 18.
【００２５】このように本実施例では、ベース１３の外
縁部に底面１３ｂより突出して設けられた段部１４1,１
４2,１４3,１４4 に回路基板１０と半導体チップ２間の
信号の入出力を行うための導電部材であるパッド７を配
設し、ベース１３の底面１３ｂに半導体チップ２よりテ
スト用信号を取り出すテスト用端子１８を配設している
ので、ベース１３の外側部に全ての端子を配設していた
従来の半導体装置に比べると、端子数が増大してもパッ
ケージの寸法を徒に大きくすることがない。よって、回
路基板の高密度化に寄与することができる特長がある。As described above, in this embodiment, the step portions 14 1 and 1 provided on the outer edge of the base 13 so as to project from the bottom surface 13 b.
Pads 7 which are conductive members for inputting / outputting signals between the circuit board 10 and the semiconductor chip 2 are arranged on 4 2 , 14 3 and 14 4 , and a test signal from the semiconductor chip 2 is provided on the bottom surface 13 b of the base 13. Since the test terminals 18 for taking out the terminals are arranged, the size of the package can be reduced even if the number of terminals is increased as compared with the conventional semiconductor device in which all the terminals are arranged on the outer side of the base 13. It never grows. Therefore, there is a feature that it can contribute to higher density of the circuit board.
【００２６】なお、本実施例ではＬＣＣパッケージの半
導体装置について説明したが、端子がパッケージの２以
上の面に配設されてパッケージが外部回路基板と平行
に、すなわちパッケージの底面が基板面に当接して実装
される構成の半導体装置であれば本発明を適用すること
ができる。Although the semiconductor device of the LCC package has been described in this embodiment, the terminals are arranged on two or more surfaces of the package so that the package is parallel to the external circuit board, that is, the bottom surface of the package contacts the board surface. The present invention can be applied to any semiconductor device configured to be mounted in contact.
【００２７】[0027]
【発明の効果】上述の如く請求項１の発明によれば、半
導体装置を外部回路基板に実装した際に回路基板と装置
のベース底面に構成される空隙部にベースの外側から洗
浄液を流入させて装置の下に位置する回路基板面を洗浄
できる特長がある。また請求項２の発明によれば、半導
体チップのテスト用端子はべースの底面に配設され外部
回路基板と導通される導電部材だけがベースの外側面に
配設されるので、従来の半導体装置に比べるとベースの
寸法を大きくすることなく回路基板に実装できる特長が
ある。As described above, according to the first aspect of the invention, when the semiconductor device is mounted on the external circuit board, the cleaning liquid is caused to flow from the outside of the base into the space formed between the circuit board and the base bottom surface of the device. The feature is that the surface of the circuit board located under the device can be cleaned. According to the invention of claim 2, the test terminal of the semiconductor chip is provided on the bottom surface of the base, and only the conductive member which is electrically connected to the external circuit board is provided on the outer surface of the base. Compared to semiconductor devices, it has the feature that it can be mounted on a circuit board without increasing the dimensions of the base.
【図１】本発明の一実施例の構成図であり、図１（Ａ）
は縦断面図、図１（Ｂ）は底面図である。FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG.
Is a longitudinal sectional view, and FIG. 1B is a bottom view.
【図２】従来の半導体装置の一例の構成図であり、図２
（Ａ）は縦断面図、図２（Ｂ）は底面図である。FIG. 2 is a configuration diagram of an example of a conventional semiconductor device.
FIG. 2A is a vertical sectional view and FIG. 2B is a bottom view.
２ 半導体チップ ５ メタライズ（導電部材） ７ パッド（導電部材） １０ 回路基板 １２ 半導体装置 １３ ベース １３ｂ 底面 １４1,１４2,１４3,１４4 段部 １５1,１５2,１５3,１５4 外側面 １６ 空隙部 １８ テスト用端子2 semiconductor chip 5 metallization (conductive member) 7 pad (conductive member) 10 circuit board 12 semiconductor device 13 base 13b bottom surface 14 1 , 14 2 , 14, 3 and 14 4 steps 15 1 , 15 2 , 15, 3 3 , 15 4 outside Side 16 Void 18 Test terminal
───────────────────────────────────────────────────── フロントページの続き (72)発明者 原口 隆 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Haraguchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited
Claims (3)
（１３）と一端を該半導体チップ（２）と電気的に接続
され他端が該ベース（１３）の外部と導通可能となるよ
う該ベース（１３）の２以上の外側面（１５1,１５2,１
５3,１５4)に配設された導電部材（５，７）とを具備し
た半導体装置において、 該導電部材（５）の該他端（７）が外部回路基板（１
０）と導通可能なよう該外部回路基板（１０）に該ベー
ス（１３）を配設した時に該外部回路基板（１０）に当
接して該外部回路基板（１０）と該ベース（１３）の該
外部回路基板（１０）に対向する底面（１３ｂ）との間
に該ベース（１３）の外側と連通する空隙部（１６）を
構成するよう該ベース（１３）の底面（１３ｂ）より突
出して設けられた段部（１４1,１４2,１４3,１４4)を具
備したことを特徴とする半導体装置（１２）。1. A base (13) on which a semiconductor chip (2) is mounted and one end of which is electrically connected to the semiconductor chip (2) and the other end of which can be electrically connected to the outside of the base (13). Two or more outer side surfaces (15 1 , 15 2 , 1, 1) of the base (13)
5 3 , 15 4 ), the other end (7) of the conductive member (5) is connected to the external circuit board (1).
0) when the base (13) is arranged on the external circuit board (10) so as to be electrically connected to the external circuit board (10), the external circuit board (10) contacts the external circuit board (10) and the base (13). It projects from the bottom surface (13b) of the base (13) so as to form a space (16) communicating with the outside of the base (13) between the bottom surface (13b) facing the external circuit board (10). A semiconductor device (12) comprising the provided step portions (14 1 , 14 2 , 14 3 , 14 4 ).
（１３）と一端を該半導体チップ（２）と電気的に接続
され他端が該ベース（１３）の外部と導通可能となるよ
う該ベース（１３）の２以上の外側面（１５1,１５2,１
５3,１５4)に配設された導電部材（５，７）とを具備し
た半導体装置において、 該導電部材（５）の該他端（７）が外部回路基板（１
０）と導通可能なよう該外部回路基板（１０）に該ベー
ス（１３）を配設した時に該ベース（１３）の該外部回
路基板（１０）に対向する底面（１３ｂ）に、一端が該
半導体チップ（２）と電気的に接続され他端が該ベース
（１３）の外部と導通可能とされるテスト用端子（１
８）を更に具備したことを特徴とする半導体装置（１
２）。2. A base (13) on which the semiconductor chip (2) is mounted and one end of which is electrically connected to the semiconductor chip (2) and the other end of which can be electrically connected to the outside of the base (13). Two or more outer side surfaces (15 1 , 15 2 , 1, 1) of the base (13)
5 3 , 15 4 ), the other end (7) of the conductive member (5) is connected to the external circuit board (1).
0) when the base (13) is arranged on the external circuit board (10) so as to be electrically connected to the external circuit board (10), one end of the base (13) is provided on the bottom surface (13b) facing the external circuit board (10). A test terminal (1) that is electrically connected to the semiconductor chip (2) and has the other end electrically connected to the outside of the base (13).
8) The semiconductor device further comprising (1)
2).
は、前記テスト用端子（１８）が具備される前記ベース
（１３）の前記底面（１３ｂ）より突出して設けられる
ことを特徴とする請求項１記載の半導体装置（１２）。3. The step portion (14 1 , 14 2 , 14 3 , 14 4 )
The semiconductor device (12) according to claim 1, wherein is provided so as to project from the bottom surface (13b) of the base (13) provided with the test terminal (18).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5331192A JPH05259306A (en) | 1992-03-12 | 1992-03-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5331192A JPH05259306A (en) | 1992-03-12 | 1992-03-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05259306A true JPH05259306A (en) | 1993-10-08 |
Family
ID=12939178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5331192A Withdrawn JPH05259306A (en) | 1992-03-12 | 1992-03-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05259306A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09129770A (en) * | 1995-10-31 | 1997-05-16 | Nec Corp | Integrated circuit device |
| WO2005071743A1 (en) * | 2004-01-22 | 2005-08-04 | Renesas Technology Corp. | Semiconductor package and semiconductor device |
| US7067741B2 (en) | 2000-09-05 | 2006-06-27 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument |
| WO2006114986A1 (en) * | 2005-04-25 | 2006-11-02 | Sony Corporation | Electronic component mounting board and electronic device using same |
| US7141819B2 (en) | 2003-05-19 | 2006-11-28 | Oki Electric Industry Co., Ltd. | Semiconductor package |
| US7184276B2 (en) | 2000-09-05 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument |
-
1992
- 1992-03-12 JP JP5331192A patent/JPH05259306A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09129770A (en) * | 1995-10-31 | 1997-05-16 | Nec Corp | Integrated circuit device |
| US7067741B2 (en) | 2000-09-05 | 2006-06-27 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument |
| US7129420B2 (en) | 2000-09-05 | 2006-10-31 | Seiko Epson Corporation | Semiconductor device and method for manufacture thereof, circuit board, and electronic instrument |
| US7184276B2 (en) | 2000-09-05 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument |
| US7141819B2 (en) | 2003-05-19 | 2006-11-28 | Oki Electric Industry Co., Ltd. | Semiconductor package |
| WO2005071743A1 (en) * | 2004-01-22 | 2005-08-04 | Renesas Technology Corp. | Semiconductor package and semiconductor device |
| WO2006114986A1 (en) * | 2005-04-25 | 2006-11-02 | Sony Corporation | Electronic component mounting board and electronic device using same |
| JP2006303335A (en) * | 2005-04-25 | 2006-11-02 | Sony Corp | Electronic component mounting substrate, and electronic device using the same |
| US7808104B2 (en) | 2005-04-25 | 2010-10-05 | Sony Corporation | Substrate for mounting electronic component and electronic apparatus including the substrate |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |