GB2056772A

GB2056772A - Integrated circuit package and module

Info

Publication number: GB2056772A
Application number: GB8026184A
Authority: GB
Original assignee: Amdahl Corp
Current assignee: Fujitsu IT Holdings Inc
Priority date: 1980-08-12
Filing date: 1980-08-12
Publication date: 1981-03-18
Also published as: GB2056772B

Abstract

A package for an IC comprises an insulating plate having a recess in its top surface, the recess having a bottom surface 66 to which the chip 70 is bonded, a raised surface carrying tracks 64 to which the electrodes of the chip are wired, and a second raised surface to which a lid 36 is bonded. The top surface of the plate carries external contacts 50 connected by conductive tracks to the internal tracks 64. A heat sink may be bonded to the lower face of the package. The package is produced by assembling four green ceramic pieces the upper three pieces having apertures of successively increasing size. The pieces carry appropriate metallised areas so that when fired the resulting plate provides the required contacts and interconnections. A plurality of packages may be mounted on an interconnect plate having on one face bonding pads matching the contacts of the packages and the other face carrying leads for external connection. <IMAGE>

Description

SPECIFICATION Leadless integrated circuit package and module This invention relates generally to semiconductor integrated circuits, and more particularly the invention relates to integrated circuit carriers and interconnect modules.

The semiconductor integrated circuit has revolutionized the electronics industry by providing complex circuits in economical and reliable semiconductor chips. With large scale integration (LSI) and very large scale integration (VLSI) techniques the density of integrated circuits has progressed to allow fabrication of large circuit arrays in a single chip.

The effect is most notable in the computer industry where computer systems are increasing in computing speed and power while decreasing in physical size.

With the increasing circuit density-in integrated circuit chips, the need continues for chip packages which can effectively interconnect the chips and provide improved heat dissipation. Further, the packages should be economical and facilitate ease of fabrication, testing, and rework of packaged chips as necessary.

U. S. Patent No. 4,115,837, assigned to the present assignee, discloses a package for a semiconductor integrated circuit chip wherein a unitary ceramic package provides an interconnect means between the chip and other circuits mounted on a common board. A plurality of leads are attached to one side of the package, and heat sink means is attached to the opposite side and forms an integral part of the package. The ceramic package is made from a plurality of green ceramic pieces which have been selectively metallized, and the pieces are then formed in a unitary structure by the application of pressure and heat.

In an attempt to further increase circuit density, several chips have been mounted in a single package, thus reducing the lengths of interconnections and the physical size of the packaged array. However, testing of the individual circuits after mounting in the package is difficult. Moreover, fabrication rework necessitated by one defective chip often results in damage to the other chips.

Accordingly, an object of the present invention is an improved package for a semiconductor intregrated chip.

Another object of the invention is a compact module for a plurality of integrated circuit chips.

Still another object of the invention is an integrated circuit package and module with improved heat dissipation.

Another object of the invention is an integrated circuit package wherein integrated circuits are readily tested following fabrication.

Another object of the invention is an integrated circuit package and module which facilitates rework of a defective circuit chip.

Yet another object of the present invention is an integrated circuit package which is economical.

Briefly, in accordance with the present invention, a package for an integrated circuit chip includes a unitary carrier having a bottom surface, a top surface, and a cavity extending from the top surface inwardly and spaced from the bottom surface. The cavity includes a chip receiving surface, a first raised surface above the chip receiving surface and including a first plurality of contacts for interconnection with a semiconductor chip. A second raised surface above the first raised surface is provided for receiving a package cover.

The top surface includes a second plurality of contacts, and a plurality of conductive leads integral with the package interconnects the first plurality of contacts and the second plurality of contacts.

The chip receiving surface preferably includes means for receiving a chip in bonded contact, and the bottom surface of the package includes means for receiving a heat sink.

Thus, heat flow from a bonded semiconductor chip to the heat sink is facilitated through the bottom surface of the package.

A plurality of semiconductor chips are readily interconnected in a larger circuit module by providing a support plate having a plurality of sets of module contacts on one major surface and a plurality of leads extending from the plate with a plurality of interconnections within the plate interconnecting the sets of module contacts and the leads. Each set of module contacts is arranged to receive a semiconductor or chip package, and a plurality of semiconductor chip packages are mounted on the plurality of sets of module contacts. Thus, a larger circuit module is provided utilizing the package in accordance with the present invention and deriving the benefits thereof.

The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawing.

In the drawings, Figure 1 is a perspective view of a circuit module in accordance with one embodiment of the present invention.

Figure 2 is a plan view of the support plate in the module of Fig. 1 with circuit packages removed.

Figure 3 is a section view of the support plate of Fig. 2 taken along lines 3-3.

Figure 4 is an exploded perspective view of one embodiment of an integrated circuit chip package in accordance with the present invention.

Figure 5 is a plan view of the integrated circuit package of Fig. 4.

Figure 6 is a side view in section of the package of Fig. 5 taken along the lines 6-6.

Figure 7 is the side view in section shown in Fig. 6 with an integrated circuit chip mounted therein.

Referring now to the drawings, Fig. 1 is a perspective view of a circuit module in accordance with one embodiment of the present invention. The module includes a support plate 10 having a plurality of integrated circuit chip packages 12, 14, 16 and 18 mounted on one major surface thereof. Each circuit package includes a heat sink 20 mounted thereon for cooling of an integrated circuit chip mounted within the package. Extending from the opposite major surface of the support plate 10 are a plurality of electrical leads 22 which are interconnected with the circuits mounted within the packages through means of conductive leads within plate 10, as further illustrated in Fig. 3.

Fig. 2 is a plan view of the top surface of plate 10 with the integrated circuit packages removed therefrom. A plurality of sets of module contacts shown generally at 24, 26, 28 and 30 are provided on the top surface with each set of module contacts configured to mate with corresponding contacts on the integrated circuit package.

Fig. 3 is a side view in section of the support plate of Fig. 2 taken along the line 3-3 and illustrates the multilayer interconnection pattern within plate 10 as illustrated generally by the dotted lines 32. The supporting plate 10 is preferably made of ceramic material consisting of a plurality of ceramic layers with each layer having an interconnect layer defined thereon such as by tungsten paint. The plurality of layers are then stacked and fired to form a unitary ceramic body with the multilayer interconnect patterns defined therein, in accordance with conventional processing.

Referring now to Fig. 4, an exploded perspective view of the integrated circuit package in accordance with one embodiment of the invention is illustrated. The package includes a cover 36, a ceramic body portion shown generally at 38, and a sink 40. Cover 36 is made of Kovar or ceramic such as alumina and is of suitable configuration to mate with the body portion 38. Heat sink 40 comprises a suitable heat conductive material such as an aluminum alloy or copper alloy and is affixed to the body portion 38 by suitable means such as epoxy or tin-load solder.

The body portion 38 comprises a plurality of ceramic pieces 42, 44, 46 and 48 of a green ceramic such as alumina which, after the desired metallization is formed thereon, is stacked in array and formed into a single unitary structure by the application of pressure and temperature, in accordance with conventional techniques. For example, the body may be heated at a temperature of approximately 1 600' for approximately one-half hour during which time the metallization is fired into the ceramic material. Tungsten paint is preferably utilized for the metallization because a refractory metal must be provided which is able to withstand the high curing temperature used for the ceramic. The number of leads and contacts illustrated in the structure are limited in number for ease of illustration.However, in actual use a much larger number of leads and contacts likely are used.

The top ceramic body 42 has a plurality of contacts 50 on the top surface thereof with leads 52 extending from the contacts 50 and down the exterior side of the body. Opening 54 is of suitable dimensions to receive the cover 36. As above indicated, the contacts and metal interconnections are preferably made of tungsten, and the contacts and interconnections can further include nickel and gold plate to facilitate the subsequent formation of electrical contacts. In a preferred embodiment the tungsten pattern is defined by painting or silk screening and has a thickness of approximately one-half mil. Nickel is plated to a thickness of approximately 100 microinches, and gold is then plated to a thickness of approximately 70 micro-inches on the plated nickel. The units can be formed from large ceramic sheets in which holes are punched along adjacent sides of the units.

The holes are filled with tungsten ink, and subsequently the ceramic sheet is scribed and broken to form the individual units with the leads 52 resulting from the punched and inked holes.

Unit 44 has an external configuration which is essentially the same as the external configuration of unit 42 and has a plurality of leads 56 on the outside surface which mates with leads 52 of unit 42. An internal opening 58 is smaller in size than the opening 54 of unit 42 whereby the cover 36 will rest on the top surface of unit 44. The area 60 around the periphery of opening 58 is provided with a tungsten-nickel-gold pattern whereby the cover 36 can be soldered in position to form a hermetic seal. If cover 36 is ceramic, metallization pattern is provided on one surface to mate with the metallization pattern 60. Opening 58 is smaller than the opening 54 but is large enough to receive a semiconductor chip, Unit 46 has the same external configuration as does units 42 and 44, and internal opening 62 is provided to receive a semiconductor chip. On the top surface of unit 46 are a plurality of electrical contacts which extend from opening 62 to the exterior walls of unit 46 in a pattern which mates with the leads 52 and 56 of the units 42 and 44, respectively. Again, the ohmic lead pattern preferably comprises a tungsten-nickel-gold structure.

The opening 62 is smaller than opening 58 but is of suitable size for receiving a semiconductor chip. As will be discussed further hereinbelow, the leads 64 will be interconnected with a semiconductor chip by suitable means such as wire bonding.

Unit 48 is the bottom portion of the ceramic body and has an outer configuration which is substantially the same as the outer configuration of units 42, 44, and 46. Centrally disposed on the top surface of unit 48 is a metallized pattern 66 to facilitate the bonding of a semiconductor chip to the surface of unit 48. Again, the metallized pattern 66 preferably comprises tungsten-nickel-gold.

In fabricating the stacked array, only the tungsten is applied to the individual units.

After firing the stacked ceramic units and forming the unitary ceramic structure, the nickel and gold plating of the exposed metallization is performed. Contact to the metallized pattern 66 for the plating operation can be facilitated by providing a thin lead on the surface of unit 48 which can be contacted after the unitary structure is formed.

Fig. 5 is a plan view of the ceramic body portion 38 after the units 42, 44, 46 and 48 are laminated into a single unitary structure.

In this view, the contacts 50 on the top unit 42 are located on the outer periphery of the structure, and the metallized surface 60 on unit 44 receives the package cover. Contacts 64 are inside metallized pattern 62 and are provided for interconnection with the semiconductor chip which will be mounted on the metallized pattern 66 on the bottom unit 48.

The relatively positions of the metallized patterns are further illustrated in Fig. 6 which is a side view in section of the unitary ceramic structure in Fig. 5 taken along line 6-6. The contacts 50 are provided about the top surface of the structure, and the lid receiving metallized layer 60 is provided within the defined cavity and immediately below the top surface. Contacts 64 which will be electrically interconnected to the semi-conductor chip extend outwardly and interconnect with the top contacts 50 by the metallized pattern on the exterior of the structure. A semiconductor chip will be mounted on the bottom surface 66 of the cavity.

Fig. 7 is a side view in section as illustrated in Fig. 6 but with a semiconductor chip 70 affixed to the metallized pattern 66 and elect trically interconnected with contacts 64 by wire bonding. Cover 36 is hermetically sealed to metallized layer 60 within the cavity. Importantly, the cover is recessed below the top surface of the package whereby a test fixture can directly mate with the contacts 50. Further, contacts 50 can be bonded directly to the mating module contacts on plate 10. The semiconductor chip is preferably bonded to layer 60 by means of a gold-silicon eutectic paste, which is commercially available and conventionally employed in the semiconductor industry. Lid 36 is bonded to metallized pattern 60 by gold-tin solder.

A semiconductor package in accordance with the present invention is economical and facilitates fabrication, testing, and re-work of semiconductor chips. By attaching the semiconductor chip to a surface region immediately adjacent to the heat sink, heat transfer from the unit is facilitated. The recessed cover allows the top contacts to mate with a test fixture and facilitates direct bonding of the package to the module contacts. The electronic array in accordance with the invention is compact yet facilitates rework of defective package chips.

While the invention has been described with reference to specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Claims

1. A package for an integrated circuit chip comprising a unitary carrier having a bottom surface, a top surface, and a cavity extending from said top surface inwardly and spaced from said bottom surface, said cavity including a chip receiving surface, a first raised surface above said chip receiving surface and including a first plurality of contacts for interconnection with a chip, a second raised surface above said first raised surface for receiving a package cover, said top surface including a second plurality of contacts, and a plurality of conductive leads integral with said package and interconnecting said first plurality of contacts and said second plurality of contacts.

2. A package as defined by Claim 1 wherein said chip receiving surface includes means for receiving a chip in bonded contact.

3. A package as defined by Claim 2 and further increasing means on said bottom surface for receiving a heat sink.

4. A package as defined by Claim 3 and further including a heat sink bonded to said bottom surface.

5. A package as defined by Claim 1 or 4 wherein said carrier comprises ceramic material.

6. A package as defined by Claim 5 wherein said first plurality of contacts and said second plurality of contacts and said plurality of conductive leads comprise a metal selected from tungsten and molybdenum.

7. A package as defined by Claim 6 wherein said contacts further comprise nickel and gold.

8. A package as defined by Claim 1 or 4 and further including a package cover of configuration for hermetically sealing with said second raised surface with said cover being below said top surface.

9. A package as defined by Claim 8 and further including a semiconductor chip within said package and means for interconnecting said chip with said first plurality of contacts.

10. A circuit module comprising a support plate having a plurality of sets of module contacts on one major surface, a plurality of leads extending from said plate, a plurality of interconnections within said plate and interconnecting said sets of module contacts and said leads, each set of module contacts arranged to receive a semiconductor chip package, and a plurality of semiconductor chip packages mounted on said plurality of sets of module contacts.

11. A circuit module as defined by Claim 10 wherein each of said semiconductor chip packages comprises a unitary carrier having a bottom surface, a top surface, and a cavity extending from said top surface inwardly and spaced from said bottom surface, said cavity including a chip receiving surface, a first raised surface above said chip receiving surface and including a first plurality of package contacts for interconnection to a chip, a second raised surface above said first raised surface for receiving a package cover, said top surface including a second plurality of package contacts, and a plurality of conductive leads integral with said package and interconnecting said first plurality of package contacts and said second plurality of package contacts.

12. A circuit module as defined by Claim 11 wherein said chip receiving surface includes means for receiving a chip in bonded contact, and further including a semiconductor chip bonded to said chip receiving surface and means interconnecting said chip with said first plurality of package contacts.

13. A circuit module as defined by Claim 12 and further including a package cover of configuration for hermetically sealing with said second raised surface.

14. A circuit module as defined by Claim 13 and including a heat sink bonded to said bottom surface of each of said packages.

15. A circuit module package substantially as herebefore described with reference to and illustrated in any of the accompanying drawings.