JPH07262124A - Memory access method and semiconductor circuit device realizing this method - Google Patents

Abstract

PURPOSE:To effectively use address busses to access a memory by using the address bus, which corresponds to unsignificant bits of address data, as a data bus to access the memory. CONSTITUTION:For example, when a memory 3 is accessed by normal 16-bit data bus 16, a switching signal and an input/output control signal are supplied to switching circuits 33a to 33c from a switching signal line and an input/output control signal line respectively by execution of a switching instruction, which controls switching circuits 33a to 33c, to switch the internal connections. Address data is outputted onto an address bus 47 (48) by switching circuits 33a to 33c. That is, an address bus 55 in an MPU 2 is connected to the memory 3 through the address bus 47 (48) by switching circuits 33a to 33c, and address data is transmitted. In this case, data is transmitted to and received from the memory 3 through data busses 45 and 46 to access the memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access method for accessing a memory by substituting an address bus for a data bus, and a semiconductor circuit device for implementing the memory access method.

[0002]

2. Description of the Related Art FIG. 15 is an explanatory diagram showing a method of accessing an internal memory of a 16-bit microcomputer 1. In the figure, 2 is a micro processing unit (hereinafter referred to as MPU), 3 is a memory, 4 is an address bus for outputting address data, and 5 is a data bus for outputting data. When data is read, the address data output from the MPU 2 on the address bus 4 is sent to the memory 3, and the memory 3 reads the data stored at that address according to the address data and outputs it to the data bus 5 to output the MPU 2 Sent to. At the time of writing data, the data output from the MPU 2 to the data bus 5 is written in the address designated by the address data output to the address bus 4.

In the case of the 16-bit microcomputer 1, generally, 24 address buses can access memory addresses of 0 to 16 megabytes, and 16 data buses can access 16-bit data at a time. It is possible. 16 is an explanatory diagram showing a method of accessing the external memory by the 16-bit microcomputer 1. 16, parts that are the same as those shown in FIG. 15 are given the same reference numerals, and descriptions thereof will be omitted. In the figure, 11 and 13 are address decoders for decoding address data, and 12 is an address bus and a data bus connecting the address decoders 11 and 13. Reference numeral 14 is an address bus connecting the address decoder 13 and the external memory 16, and reference numeral 15 is a data bus connecting the address decoder 13 and the external memory 16 in the same manner.

The address decoder 11 and the address decoder 13 enable the connection between the microcomputer 1 having a small number of external terminals and the external memory 16 by switching the data bus and the address bus with respect to time. In this case, the data at the address specified by the address data output from the MPU 2 onto the address bus 4 is read from the external memory 16 when the data is read as in the internal memory access.
Is read out from the device, output to the data bus, and transmitted to the MPU 2. When writing data, the external memory 16 output on the address bus 4 and designated by the address data is output.
The data output from the MPU 2 to the data bus 5 is written in the address of.

FIG. 17 is an internal block diagram of the MPU 2. 17, parts that are the same as those shown in FIG. 15 are given the same reference numerals, and descriptions thereof will be omitted. In the figure, 21 is a bus interface unit, 22 is a code POM, 23 is an internal bus, 24 is a control signal, and 25 is an arithmetic control unit including a control circuit 25a, a register group 25b and an ALU 25c. Commands or data are transferred from the address bus 4 and the data bus 5 to the bus interface unit 21.
The address value related to the data and the instruction is taken into the MPU 2 via the and is output from the bus interface unit 21 to the internal bus 23. Further, the instruction is transmitted to the code ROM 22 as a code signal, and is decoded by the code ROM 22 to generate a corresponding control signal 24. With the control signal 24, the control circuit 25a, the register group 25b,
Control of the ALU 25c and the like is performed.

[0006]

By the way, by the memory access method as described above, for example, the address bus 24 is used.
When accessing the memory 3 with a book, SFR (S
This is a functional function register, which is a memory area in which registers for input / output ports or built-in peripheral devices such as timers, PWMs, A / D converters, etc. are arranged in a single-chip microcomputer, and usually addresses from "000000" to "0".
Address bus 24 for accessing a limited area such as a memory area up to 000FF)
All the books are not used and the upper 16 bits are always "0" at the time of memory access, and the address bus corresponding to this bit exists as an invalid address bus. Further, even when the 16-bit single-chip microcomputer is normally used alone, it is not necessary to set all the memory addresses from 0 to 16 megabytes to be accessible and only the actually used area may be accessible. Therefore, there is an unused or non-effective address bus.

As described above, in the conventional memory access method, the number of address buses is the number of bits of address data,
That is, although the number corresponding to the processing capacity of the microprocessor is provided, the address data on the address bus may include a lot of non-significant bits depending on the usage situation. There is a problem that it is hard to say that the address bus is being used effectively.

The present invention has been made to solve the above problems, and the invention of claim 1 is a memory access method capable of effectively utilizing an address bus to access a memory. Aim to get.

It is an object of the present invention to provide a memory access method capable of effectively utilizing the address bus and expanding the data bus width to enable memory access.

It is an object of the present invention to obtain a memory access method capable of accessing a memory by effectively utilizing an address bus.

It is an object of the present invention to provide a memory access method capable of effectively utilizing the address bus and further expanding the data bus width to enable memory access.

It is an object of the present invention to provide a memory access method capable of accessing a memory by effectively utilizing an address bus.

It is an object of the present invention to provide a memory access method capable of effectively utilizing the address bus and further expanding the data bus width to enable memory access.

According to a seventh aspect of the present invention, a memory access method is possible in which the address bus is effectively used to access the memory, or the address bus is effectively used and the data bus width is expanded to perform the memory access. Aim to get.

According to an eighth aspect of the present invention, a memory access method is possible in which the address bus is effectively used to access the memory, or the address bus is effectively used and the data bus width is expanded. Aim to get.

According to a ninth aspect of the present invention, a memory access method is possible in which the address bus is effectively used to access the memory, or the address bus is effectively used and the data bus width is expanded to perform the memory access. Aim to get.

According to a tenth aspect of the present invention, a memory access method is possible in which the address bus is effectively utilized to access the memory, or the address bus is effectively utilized and the data bus width is expanded to perform the memory access. Aim to get.

It is an object of the invention of claim 11 to obtain a memory access method capable of flexibly allocating an address bus and a data bus according to a use condition to perform memory access.

It is an object of the present invention to provide a memory access method in which the width of the address bus and the data bus is flexibly changed according to the use status to perform memory access.

It is an object of the invention of claim 13 to obtain a memory access method capable of flexibly changing the widths of the address bus and the data bus according to the use situation and performing the memory access.

It is an object of the present invention to provide a memory access method capable of performing memory access by flexibly changing the widths of the address bus and the data bus according to the use status.

It is an object of the present invention to provide a memory access method capable of flexibly changing the widths of the address bus and the data bus according to the use status.

It is an object of the invention of claim 16 to obtain a semiconductor circuit device capable of accessing a memory by effectively utilizing an address bus.

It is an object of the present invention to obtain a semiconductor circuit device capable of effectively utilizing the address bus and further expanding the data bus width to enable memory access.

It is an object of the present invention to provide a semiconductor circuit device capable of accessing a memory by effectively utilizing an address bus.

It is an object of the present invention to obtain a semiconductor circuit device in which the address bus can be effectively utilized and the data bus width can be expanded to enable memory access.

It is an object of the present invention to provide a semiconductor circuit device capable of accessing a memory by effectively utilizing an address bus.

It is an object of the invention of claim 21 to obtain a semiconductor circuit device capable of effectively utilizing an address bus and further expanding a data bus width to enable memory access.

According to a twenty-second aspect of the present invention, a semiconductor circuit device capable of effectively utilizing an address bus to access a memory, or effectively utilizing an address bus and expanding a data bus width to perform a memory access. Aim to get.

According to a twenty-third aspect of the present invention, a semiconductor circuit device capable of effectively utilizing an address bus to access a memory, or effectively utilizing an address bus and expanding a data bus width to perform a memory access. Aim to get.

According to a twenty-fourth aspect of the present invention, a semiconductor circuit device capable of effectively utilizing the address bus to access the memory, or effectively utilizing the address bus and expanding the data bus width to perform the memory access. Aim to get.

According to a twenty-fifth aspect of the present invention, a semiconductor circuit device capable of effectively utilizing the address bus to access the memory, or effectively utilizing the address bus and expanding the data bus width to perform the memory access. Aim to get.

It is an object of the invention of claim 26 to obtain a semiconductor circuit device capable of flexibly allocating an address bus and a data bus according to a use situation.

It is an object of the invention of claim 27 to obtain a semiconductor circuit device capable of flexibly allocating an address bus and a data bus according to a use situation.

It is an object of the present invention to provide a semiconductor circuit device capable of flexibly allocating an address bus and a data bus according to the use status.

It is an object of the present invention to provide a semiconductor circuit device capable of flexibly allocating an address bus and a data bus according to the use status.

A thirtieth aspect of the invention is to obtain a semiconductor circuit device in which an address bus and a data bus can be flexibly distributed according to a use situation.

[0038]

According to another aspect of the present invention, there is provided a memory access method, wherein an address bus corresponding to a non-significant bit of address data designating a memory area to be accessed is used as a data bus. It is to access.

According to another aspect of the memory access method of the present invention, the address bus corresponding to the non-significant bit of the address data designating the memory area to be accessed is used as the data bus and is used together with the original data bus. As a result, the original data bus width is expanded to access the memory.

According to a third aspect of the present invention, there is provided a memory access method, a bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, and a data transfer for transferring data corresponding to the predetermined number of bits. Based on the instruction, the address bus corresponding to the non-significant bit of the address data that specifies the memory area to be accessed is switched to the data bus, and data is transferred by the switched data bus to access the memory. is there.

According to a fourth aspect of the present invention, there is provided a memory access method, which corresponds to a bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, and the predetermined number of bits and the original number of bits of the data bus. Based on the data transfer instruction that transfers the data of the specified width,
The address bus corresponding to the non-significant bit of the address data that specifies the memory area to be accessed is switched to the data bus, and data is transferred by the switched data bus and the original data bus to access the memory. is there.

According to a fifth aspect of the present invention, there is provided a memory access method in which information of a bus switching information register for storing information indicating a bus switching state set in a memory to be accessed and a predetermined number of bits of a switched data bus are set. Based on a data transfer instruction for transferring corresponding data, the data is transferred through the data bus to access the memory.

According to another aspect of the memory access method of the present invention, information of a bus switching information register for storing information indicating a bus switching state set in a memory to be accessed and a predetermined number of bits switched to a data bus, Based on a data transfer instruction for transferring data corresponding to the original number of bits of the data bus, the data is transferred by the data bus to access the memory.

According to the memory access method of the seventh aspect of the present invention, the memory access is performed by switching the address bus corresponding to the predetermined number of bits of the address data to the data bus according to the mode set in the microprocessor.

According to another aspect of the present invention, there is provided a memory access method in which an address bus corresponding to a predetermined number of bits of address data is switched to a data bus based on a mode set in a microprocessor and information in a bus switching information register. Is to do.

According to the memory access method of the ninth aspect of the present invention, the memory access is performed by switching the address bus corresponding to the predetermined number of bits of the address data to the data bus based on the bus switching signal input from the external terminal. is there.

According to the memory access method of the tenth aspect of the present invention, based on the bus switching signal input from the external terminal,
The memory access is performed by switching the address bus corresponding to the predetermined number of bits of the address data to the data bus.

According to the memory access method of the eleventh aspect of the present invention, the address bus and the data bus are switched by the number of bits according to the use condition and distributed, the widths of the address bus and the data bus are changed according to the use condition, and the predetermined value is set. The memory is accessed by a data transfer instruction that handles bit data.

A memory access method according to a twelfth aspect of the present invention is a switching instruction for switching between an address bus and a data bus having a bit number according to a use condition, for switching the address bus and the data bus by a bit number according to the use condition. The memory access is performed by executing.

According to a thirteenth aspect of the present invention, there is provided a memory access method, wherein the number of bits according to a use condition is based on information of a bus switching information register which stores information indicating a bus switching state set in a memory to be accessed. The address bus and the data bus are switched to transfer data through the data bus to access the memory.

According to a fourteenth aspect of the present invention, in the memory access method, the address bus and the data bus having the number of bits corresponding to the use conditions are switched according to the mode set in the microprocessor to transfer the data by the data bus. It is used to access the memory.

According to a fifteenth aspect of the present invention, there is provided a memory access method based on a bus switching signal input from an external terminal.
The memory is accessed by switching between the address bus and the data bus having the number of bits according to the usage conditions, transferring the data through the data bus, and accessing the memory.

A semiconductor circuit device according to a sixteenth aspect of the present invention comprises bus switching means for switching an address bus corresponding to a non-significant bit of address data designating a memory area to be accessed to a data bus. .

A semiconductor circuit device according to a seventeenth aspect of the present invention is a bus switching means for switching an address bus corresponding to a non-significant bit of address data designating a memory area to be accessed to a data bus, and the bus switching means. By using the data bus switched from the address bus and the original data bus together, the memory access means for expanding the original data bus width and accessing the memory is provided.

A semiconductor circuit device according to an eighteenth aspect of the present invention is a data transfer which transfers a bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, and data corresponding to the predetermined number of bits. The bus switching means has an instruction and switches the address bus corresponding to the predetermined number of bits of the address data to the data bus by the bus switching instruction.

A semiconductor circuit device according to a nineteenth aspect of the present invention corresponds to a bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, and the predetermined number of bits and the original number of bits of the data bus. The bus switching means executes the bus switching instruction for the address bus corresponding to the non-significant bit of the address data that specifies the memory area to be accessed. It is designed to switch to the data bus.

A semiconductor circuit device according to a twentieth aspect of the present invention is provided with a bus switching information register which stores information indicating a bus switching state which is set in a memory to be accessed, and the information of the bus switching information register and switching information. A memory access unit for transferring data by the data bus to access a memory based on a data transfer instruction for transferring data corresponding to a predetermined number of bits of the data bus.

A semiconductor circuit device according to a twenty-first aspect of the present invention includes a bus switching information register which stores information indicating a bus switching state which is set in a memory to be accessed.
Based on the information of the bus switching information register and the data transfer instruction for transferring the data corresponding to the number of bus bits switched to the data bus and the original number of bits of the data bus, the data is transferred by the data bus to the memory. Memory access means for accessing the memory.

A semiconductor circuit device according to a twenty-second aspect of the present invention comprises mode setting means for setting a mode for switching an address bus corresponding to a predetermined number of bits of address data to a data bus.

A semiconductor circuit device according to a twenty-third aspect of the present invention comprises mode setting means for setting a mode for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, and the mode setting means sets the mode. The bus switching means is adapted to switch the address bus corresponding to the predetermined number of bits of the address data to the data bus.

A semiconductor circuit device according to a twenty-fourth aspect of the present invention includes an external terminal to which a bus switching signal is input, and the bus switching means determines a predetermined address data based on the bus switching signal input from the external terminal. The address bus corresponding to the number of bits is switched to the data bus.

A semiconductor circuit device according to a twenty-fifth aspect of the present invention is a data transfer command for transferring data corresponding to the predetermined number of bits when switching an address bus corresponding to the predetermined number of bits of address data to a data bus, or A data transfer instruction for transferring data of a width corresponding to the predetermined number of bits and the original number of bits of the data bus when switching the address bus corresponding to the predetermined number of bits of address data to the data bus, and a bus switching signal are input. The bus switching means switches the address bus corresponding to the predetermined number of bits of the address data to the data bus based on the bus switching signal input from the external terminal.

In the semiconductor circuit device according to the twenty-sixth aspect of the present invention, the address bus and the data bus are switched and assigned to the address bus and the data bus having the number of bits according to the use condition, and the width of the address bus and the data bus is used as the use condition. A bus changing means for changing the number of bits, a data transfer instruction for handling a predetermined bit of data, and a memory access means for accessing the memory by transferring data by the data bus according to the data transfer instruction. is there.

A semiconductor circuit device according to a twenty-seventh aspect of the present invention comprises a switching instruction for switching the address bus and the data bus to the address bus and the data bus having the number of bits according to the use conditions, and the bus changing means executes the switching instruction. By doing so, the address bus and the data bus having the number of bits corresponding to the usage conditions are switched.

A semiconductor circuit device according to a twenty-eighth aspect of the present invention comprises a bus switching information register for storing information indicating a bus switching state which is set in a memory to be accessed, and the bus changing means is the bus switching information register. Based on the information, the address bus and the data bus having the number of bits corresponding to the usage conditions are switched.

In the semiconductor circuit device according to the twenty-ninth aspect of the present invention, the address bus and the data bus are switched to the address bus and the data bus having the number of bits according to the use condition and distributed, and the width of the address bus and the data bus is used as the use condition. The bus changing means changes the widths of the address bus and the data bus according to the use condition based on the mode set by the mode setting means, and the memory access means. After the mode is set, a data transfer instruction is used to transfer data through the data bus to access the memory.

A semiconductor circuit device according to a thirtieth aspect of the present invention has an external terminal to which a bus switching signal is input, and the bus changing means is based on the bus switching signal input from the external terminal, and is adapted to meet the usage conditions. The address bus and the data bus having the same number of bits are switched, and the memory access means accesses the memory by transferring data by the data bus by a data transfer command after a bus switching signal is input from the external terminal. It was done like this.

[0068]

In the memory access method according to the present invention, the address bus corresponding to the non-significant bit of the address data is used as the data bus, and the memory access is performed, thereby effectively utilizing the address bus. Allows you to access.

According to another aspect of the memory access method of the present invention, the address bus corresponding to the non-significant bit of the address data is switched to the data bus and used together with the original data bus to realize effective use of the address bus. Further, the data bus width can be expanded.

In the memory access method according to the third aspect of the present invention, the address bus corresponding to the non-significant bit of the address data is switched to the data bus by the bus switching instruction for switching the address bus corresponding to the predetermined number of bits of the address data to the data bus. , And the data bus is switched by the switched data bus based on the data transfer instruction for transferring the data corresponding to the predetermined number of bits, and the memory is accessed to effectively utilize the address bus to access the memory. To be able to do.

According to another aspect of the present invention, in the memory access method, the address bus corresponding to the non-significant bit of the address data is switched to the data bus by a bus switching instruction for switching the address bus corresponding to the predetermined number of bits of the address data to the data bus. To the predetermined number of bits and the original number of bits of the data bus, and a data transfer instruction for transferring data having a width corresponding to the number of bits of the original data bus, data is transferred via the switched data bus and the original data bus. By performing the access, the address bus can be effectively used, and further, the data bus width can be expanded to enable the memory access.

According to a fifth aspect of the present invention, there is provided a memory access method, wherein a predetermined number of bits of a data bus switched based on information indicating a bus switching state set in a memory to be accessed stored in a bus switching information register. By executing the data transfer instruction for transferring the corresponding data, the data transfer is performed by the data bus to access the memory, and the address bus is effectively used to perform the memory access.

According to another aspect of the memory access method of the present invention, a predetermined number of bits switched to the data bus based on the information set in the memory to be accessed stored in the bus switching information register and indicating the bus switching state, and Effective use of the address bus is realized by transferring data through the data bus and accessing the memory by a data transfer instruction that transfers data corresponding to the number of bits of the original data bus. Acts to extend and access memory.

According to another aspect of the memory access method of the present invention, by setting the mode in the microprocessor, the address bus corresponding to the predetermined number of bits of the address data is switched to the data bus, and the address bus is effectively utilized to execute the memory access. Access, or effectively utilize the address bus and extend the data bus width to enable memory access.

According to the memory access method of the present invention, the address bus corresponding to the predetermined number of bits of the address data is switched to the data bus based on the mode set in the microprocessor and the information of the bus switching information register, and the memory access is performed. By doing so, it is possible to effectively utilize the address bus to access the memory, or to effectively utilize the address bus and expand the data bus width to perform the memory access.

In the memory access method according to the invention of claim 9, the address bus corresponding to the predetermined number of bits of the address data is switched to the data bus by the bus switching signal inputted from the external terminal, thereby effectively utilizing the address bus. It is possible to access the memory by utilizing the address bus or to effectively utilize the address bus and to extend the data bus width to perform the memory access.

According to the memory access method of the tenth aspect of the present invention, the address bus corresponding to the predetermined number of bits of the address data is switched to the data bus by the bus switching signal input from the external terminal, so that the address bus is effectively utilized. Then, the memory can be accessed, or the address bus can be effectively used and the data bus width can be expanded to perform the memory access.

In the memory access method according to the invention of claim 11, the address bus and the data bus are switched to the address bus or the data bus having the number of bits according to the use condition, and the widths of the address bus and the data bus are adjusted according to the use condition. By changing and executing a data transfer instruction that handles data of a predetermined bit, it is possible to access the memory and flexibly allocate the address bus and the data bus according to the usage status to perform the memory access.

According to the twelfth aspect of the present invention, in the memory access method, the width of the address bus and the data bus is changed by executing the switching instruction to switch to the address bus or the data bus having the number of bits according to the use condition. It is possible to flexibly change the memory access according to the usage status.

According to the memory access method of the thirteenth aspect of the present invention, the number of bits according to the use condition is determined based on the information of the bus switching information register which stores the information indicating the bus switching state which is set in the memory to be accessed. By switching to the address bus or the data bus, it is possible to flexibly change the widths of the address bus and the data bus according to the usage status and perform the memory access.

According to the memory access method of the fourteenth aspect of the present invention, the width of the address bus and the data bus is changed by switching to the address bus or the data bus having the number of bits according to the use condition according to the mode set in the microprocessor. Can be flexibly changed according to the usage status and memory access can be performed.

According to a fifteenth aspect of the present invention, in the memory access method, based on a bus switching signal input from an external terminal, switching to an address bus or a data bus having a number of bits according to a use condition is performed by the data bus. Data can be transferred, and the width of the address bus and data bus can be flexibly changed according to the usage conditions to enable memory access.

In the semiconductor circuit device according to the sixteenth aspect of the invention, the address bus corresponding to the non-significant bit of the address data designating the memory area to be accessed is switched to the data bus, and the address bus is effectively used. Allows access to memory.

According to another aspect of the semiconductor circuit device of the present invention, the address bus corresponding to the non-significant bit of the address data designating the memory area to be accessed is switched to the data bus, and the data bus switched from the address bus is used. The original data bus is used together, the data bus width is expanded and memory access is performed, the effective use of the address bus is enabled, and the memory access by the expanded data bus width becomes possible.

In the semiconductor circuit device according to the eighteenth aspect of the invention, the address bus corresponding to the non-significant bit of the address data is switched to the data bus by executing the bus switching instruction, and the data corresponding to the number of the non-significant bits is stored. Transfer is performed by the switched data bus to perform memory access, and memory access that effectively utilizes the address bus is realized.

In the semiconductor circuit device according to the nineteenth aspect of the invention, the address bus corresponding to the predetermined number of non-significant bits of the address data is switched to the data bus by the execution of the bus switching instruction, and the predetermined number of bits and the original number. Data transfer of a width corresponding to the number of bits of the data bus is performed by the data bus switched from the address bus and the original data bus to perform memory access, and effective use of the address bus is realized. It enables extended memory access.

According to a twentieth aspect of the invention, a semiconductor circuit device corresponds to information indicating a bus switching state of a bus switching information register provided in a memory to be accessed and a predetermined number of bits of a data bus switched from an address bus. Based on the data transfer instruction for transferring the data, the data is transferred by the data bus and the memory is accessed, and the memory access that effectively uses the address bus is realized.

According to another aspect of the semiconductor circuit device of the present invention, information indicating the bus switching state of the bus switching information register set in the memory to be accessed, and the number of bus bits switched from the address bus to the data bus. Based on the execution of a data transfer instruction that transfers data corresponding to the number of bits of the original data bus, the data bus switched from the address bus and the original data bus are used to transfer data and access the memory, Effectively utilize the address bus and realize memory access with an expanded data bus width.

According to a twenty-second aspect of the invention, in the semiconductor circuit device, the address bus corresponding to the predetermined number of bits of the address data is set to the data bus by setting the mode for switching the address bus corresponding to the predetermined number of bits of the address data to the data bus. It is possible to switch to the data bus and effectively utilize the address bus to access the memory, or to effectively utilize the address bus and expand the data bus width to perform the memory access.

According to a twenty-third aspect of the invention, in the semiconductor circuit device, by setting a mode in which the address bus corresponding to the predetermined number of bits of the address data is switched to the data bus, the address bus corresponding to the predetermined number of bits of the address data is set to data. It is possible to switch to a bus and effectively utilize the address bus for memory access, or to effectively utilize the address bus and expand the data bus width to perform memory access.

In the semiconductor circuit device according to the invention of claim 24, the address bus corresponding to the predetermined number of bits of the address data is switched to the data bus based on the bus switching signal input from the external terminal, and the address bus is effectively utilized. Then, the memory can be accessed, or the address bus can be effectively used and the data bus width can be expanded to perform the memory access.

In the semiconductor circuit device according to the twenty-fifth aspect of the present invention, the address bus corresponding to the predetermined number of bits of the address data is switched to the data bus based on the bus switching signal input from the external terminal, and the data transfer instruction The data bus switched from the address bus by execution or the data bus switched from the address bus and the width of data corresponding to the original number of bits of the data bus are transferred and memory access is performed to effectively utilize the address bus. Then, it is possible to access the memory or to effectively utilize the address bus and to expand the data bus width to access the memory.

According to the semiconductor circuit device of the twenty-sixth aspect of the present invention, the address bus and the data bus are switched to the address bus and the data bus having the number of bits according to the use condition and the address bus and the data bus are distributed according to the use condition. The data is transferred by the data bus by executing a data transfer instruction that handles data of a predetermined bit to access the memory, and the address bus and the data bus are flexibly distributed according to the usage status to access the memory. To be able to do.

In the semiconductor circuit device according to the twenty-seventh aspect of the present invention, the address bus and the data bus are switched to the address bus or the data bus having the number of bits according to the use condition by executing the switching instruction, and the width of the address bus and the data bus is used. It is possible to allocate memory flexibly according to the situation.

According to a twenty-eighth aspect of the present invention, in a semiconductor circuit device, based on information indicating a bus switching state of a bus switching information register provided in a memory to be accessed, an address bus and data having a bit number according to a use condition are provided. By switching to the bus, it is possible to access the memory by the address bus and data bus that are flexibly changed according to the usage status.

In the semiconductor circuit device according to the twenty-ninth aspect of the invention, when the mode for changing the widths of the address bus and the data bus according to the use conditions is set, the number of bits of the address bus and the data bus is changed according to the use conditions. It is possible to switch to an address bus or a data bus for distribution, perform memory access by the allocated address bus and data bus, and flexibly change the bus width according to the use status to enable memory access by the data bus.

According to the semiconductor circuit device of the thirtieth aspect, when the bus switching signal is input from the external terminal, the switching between the address bus and the data bus having the number of bits according to the usage conditions is performed based on the bus switching signal. After that, the data is transferred by the address bus or the data bus to perform the memory access, and the memory access can be performed by the address bus and the data bus whose bus width is flexibly changed according to the use situation.

[0098]

【Example】

Example 1. An embodiment of the memory access method according to claims 1 to 4 and the semiconductor circuit device according to claims 16 to 19 will be described below. FIG. 1 is a block diagram showing the configuration of a semiconductor circuit device that realizes the memory access method of the present embodiment. In the figure, the same or corresponding parts as in FIG. 15 are assigned the same reference numerals and explanations thereof are omitted. In this embodiment, the semiconductor circuit device is shown as a 16-bit single chip microcomputer 200. In FIG. 1, reference numeral 31 is an address bus, which has a bus width of 24 bits for addressing according to the memory capacity (16 megabytes) of the memory 3. 32 is a data bus having a bus width of 16 bits. 33 is a switching circuit (bus switching means, bus changing means) for switching an address bus corresponding to a bit of non-effective address data to a data bus, 34 is an address bus having a bus width of 8 bits,
Reference numeral 35 is a data bus having a bus width of 32 bits.

FIG. 2 is a block diagram showing the configuration of a 16-bit single chip microcomputer 100 capable of 32-bit data bus access. Figure 2
In FIG. 2, the same parts as those in FIG. In the figure, 45 and 46 are data buses connecting between the MPU 2 (memory access means, bus switching means) and the memory 3, and the data buses 45 and 4 are shown in the drawing.
Each 6 has a bus width of 8 bits. Again 47,4
Reference numerals 8 and 49 are address buses connecting between the MPU 2 and the memory 3, each having a bus width of 8 bits in the drawing. Switching circuits (bus switching means) 33a, 33b, 33c for switching the address bus and the data bus, 36 and 3
7 is a 16-bit register built in the MPU 2, 38 and 3
9 is a data bus 45, 46 and an MPU internal data bus 51,
A data bus buffer provided between 52, 40 and 41 are data bus buffers provided between the switching circuits 33a and 33b, 42 and 43 are address bus buffers provided between the switching circuits 33a and 33b,
44 is an address bus buffer provided between the address bus 55 in the MPU and the address bus 49, and 53 and 54 are 16
It is an MPU internal data bus connecting between the bit register 37 and the switching circuit 33a.

Data bus in MPU 51, 52, 53, 5
4 has an 8-bit bus width, and the intra-MPU address bus 55 has a 24-bit bus width in the drawing.

Reference numerals 57 and 58 denote the switching circuit 33c and the memory 3.
Similarly, 59 and 60 are data buses connecting between the switching circuit 33c and the memory 3. Each of these buses has a bus width of 8 bits in the drawing.

FIG. 3 is a circuit diagram showing the structure of the switching circuit 33a. In the figure, reference numeral 61 is an input / output control signal line to which an input / output control signal of the address bus / data bus is supplied by execution of a switching instruction. When an “L” level signal is given, input control is performed, and an “H” level When a signal is given, output control is performed. Reference numeral 62 is a switching signal line to which a switching signal for instructing switching of the address bus / data bus is supplied by executing the switching instruction, and is'L '.
When a level signal is applied, switching to the address bus is performed, and when an'H 'level signal is applied, switching control to the data bus is performed. Therefore, the combination of the input / output control signal and the switching signal enables input / output control such as switching between the address bus and the data bus, inputting data on the switched bus, and outputting data on the bus. It is possible. 71-74 are 2-input NAND circuits, 75-82 are 3-input NAND circuits, 83
And 84 are inverter circuits.

The switching circuit shown in FIG. 3 shows one bit of all 16 bits of the switching circuit 33a in FIG. Here, according to the input / output control signal and the switching signal, it is switched whether it is used as a data bus or an address bus, and whether it is a data input or a data output.

Further, the internal MPU address bus 55 is the MPU.
2 is connected to the internal address bus, and is used as part of the address bus when accessing with a normal data 16-bit width. Data bus 53 in MPU (5
4) is mainly connected to the 16-bit register 37,
It is used as part of the data bus when accessing 32-bit data. The output of the NAND circuit 73 is connected to the data bus buffer 40 or the data bus buffer 41, and the output of the NAND circuit 74 is connected to the address bus buffer 42 or the address bus buffer 43.

The bus on the output side of the NAND circuit 73 is used as a part of the data bus in the case of accessing the normal data with a 16-bit width via the switching circuit 33a. The bus on the output side of the NAND circuit 74 is used as a part of the address bus when accessing the normal data with a 16-bit width via the switching circuit 33a. I / O control signal line 6
The input / output control signal supplied to 1 is a signal mainly obtained by changing a read / write signal in the MPU2 or a part of the read / write signal, and is switched in accordance with the instruction execution in the MPU2. Is performed and is output. The switching signal supplied to the switching signal line 62 is a signal obtained by a switching instruction for switching the switching circuit 33a or a signal for switching, and is switched by executing a switching instruction for switching the switching circuit 33a or a value written in the switching register. And output.

In the switching circuit 33a, when the input / output control signal is at the "H" level, the output of the inverter circuit 83 becomes the "L" level and the NAND circuits 75 to 7 on the input control side.
While the gate of 8 is closed, the NAND circuit 79 on the output control side
The gate of ~ 82 can be opened to write data from the MPU2 to the memory (SFR) or the internal memory or the external memory, and when the input / output control signal is at the "L" level, the NAND circuits 75 to 78 on the input control side. While the gates are opened, the gates of the NAND circuits 79 to 82 on the output control side are closed so that data can be read from the memory (SFR), the internal memory, and the external memory to the MPU 2.

When the switching signal is at the'H 'level, the gates of the NAND circuits 76, 78, 79, 81 open according to the input / output control signal, and the input / output control signal is at the'H' level indicating the data output. In the state, the MPU address bus 55 is connected to the NAND circuits 79 and 73 and the NAND circuit 8
It is connected to the address bus buffer 42 or the address bus buffer 43 via 1, 74 and operates as a normal address bus.

When the switching signal is at the'L 'level, the gates of the NAND circuits 75, 77, 80, 82 are opened according to the input / output control signal, and the input / output control signal shows the data output at the'H' level. In this state, the MPU internal data bus 53 (54) is connected to the data bus buffer 40 (41) via the NAND circuits 80 and 73.

FIG. 4 is a circuit diagram of the switching circuit 33b,
FIG. 33 is a circuit diagram showing a configuration of 33c, showing one bit of all 16 bits. In the figure 91
93 to 95 are inverter circuits, and 96 to 100 are NAND circuits. The switching circuits 33b and 33c use the address buses 47 and 48 as address buses according to the input / output control signal supplied by the input / output control signal line 61 and the switching signal required by the switching signal line 62. Or it is used as a data bus.

That is, the switching circuit 33b operates the NAND circuits 96 and 97 when the input control signal is at the "H" level (in the case of controlling the signal output from the MPU 2 to the memory 3).
Of the data bus buffer 40 or the data bus buffer 41 and the signal output from the address bus buffer 42 or the address bus buffer 43 are supplied to the address bus 47 (48).
Further, when the input control signal is at the'L 'level (also in the case of signal input control from the memory 3 to the MPU 2), the gates of the NAND circuits 98 and 99 are opened, and the address bus 47 (4
8) the signal sent by the data bus buffer 40
Alternatively, the data is output to the data bus buffer 41, the address bus buffer 42, or the address bus buffer 43.

Further, in the case of memory access by a 16-bit normal data bus, in the case of signal output control,
The gate of the NAND circuit 97 is opened by the switching signal of the "H" level, and the address data sent from the address bus buffer 42 or the address bus buffer 43 is output to the address bus 47 (48). That is, the address bus 47 (48) functions as a bus for address data transmission for transmitting address data.

Further, in the case of memory access by the 32-bit data bus, the address buses 47 and 48 are used as data buses, and in the case of signal output control, 'L'.
The gate of the NAND circuit 96 is opened by the level switching signal, and as a result, the data sent from the MPU internal data bus 53 (54) connected to the data bus buffer 40 (41) passes through the NAND circuits 96, 100. It is output to the address bus 47 (48) via the. In this case, the address bus 47 (48) functions as a data bus for transmitting data.

The switching circuit 33c is also the switching circuit 3
Although the circuit configuration is the same as that of 3b, the inverter circuit 95 shown in FIG. 4 is provided on the input side of the NAND circuit 98.
An'L 'level input / output control signal indicating an input is supplied to the switching circuit 33c, and an'H' level switching signal is sent to the switching signal line 62 in the case of memory access by a normal 16-bit data bus. In the case of memory access by the 32-bit data bus,
The'L 'level switching signal is supplied to the switching signal line 62.

As described above, when the memory 3 is accessed with the normal data bus 16-bit width, the switching circuit 33 is used.
By executing a switching instruction for controlling a, 33b, 33c, a switching signal is sent from the switching signal line 62 and an input / output control signal is sent from the input / output control signal line 61.
b, 33c, the internal connection is switched, and the switching circuit 33a, 33b, 33c causes the address bus 47
The address data is output on (48). That is, the switching circuits 33a, 33b, 33c connect the internal MPU address bus 55 to the memory 3 via the address bus 47 (48), and the address data is transmitted. In this case, the data is transferred to and from the memory via the data buses 45 and 46 for memory access.

Data reading is performed by the address bus 5 in the MPU.
5, the address data output on the address bus 47,
48 and 49 are transmitted to the memory 3, data is read out from the memory area designated by the address data onto the data buses 45 and 46, and a 16-bit width data bus composed of the data buses 45 and 46 is used. Data is M
It is transmitted to the 16-bit register 36 in the PU.

On the other hand, data is written by the address bus 4
The value of the 16-bit register 36 in the MPU 2 is set using the address bus having a bus width of 24 bits consisting of 7, 48, 49 and the data bus having a bus width of 16 bits consisting of the data buses 45, 46. The data is written in the memory area specified by the address data output onto the address buses 47, 48 and 49 having a bus width of 24 bits.

When accessing the data bus with a 32-bit width, by executing a switching command for switching the internal connection of the switching circuits 33a, 33b, 33c, a switching signal is input to the switching circuits 33a, 33b, 33c. Output control signals are provided. Then, the bus buffers connected to the switching circuit 33a are replaced by the data bus buffers 40, 4
Switch to 1. Further, the bus buffer connected to the switching circuit 33b is switched to the data bus buffers 40 and 41. At this time, the address buses 47 and 48 are connected to the switching circuit 33.
The address buses 47 and 48, which are connected to b, function as data buses for outputting 16-bit data. Further, to the switching circuit 33c on the memory 3 side, the address buses 47 and 48 are connected, and the expanded data buses 59 and 60 on the memory 3 side are connected. As a result, access can be realized with 8 bits by the address bus 49 and 32 bits by the data buses 45, 46 and the address buses 47, 48 functioning as data buses.

In this case, in the data read, the address data output on the MPU internal address bus 55 is transmitted to the memory 3 using 8 bits of the address bus 49, and 32 bits are read from the memory area indicated by the address data. Minute data is read out and data buses 45, 46, 47, 4
Output to a data bus having a 32-bit width of 8
This data is a 16-bit register 3 that the MPU2 contains.
16 bits are transmitted to 6, 37. That is, 16-bit data sent via the data buses 45 and 46 is sent to the 16-bit register 36 and 16-bit data sent via the address buses 47 and 48 functioning as data buses. The data is stored in the 16-bit register 37 from the switching circuit 33b via the switching circuit 33a.

Data writing is performed by the data buses 45 and 46.
And address buses 47 and 4 functioning as data buses
A data bus having a 32-bit bus width of 8 is used, and a total of 32-bit data stored in the 16-bit registers 36 and 37 in the MPU 2 is output onto an address bus 49 having a 8-bit bus width. Write to the memory area specified by the address data.

That is, the access at the time of writing by the 32 bits of the data bus is performed by the switching circuits 33a, 33b, 3
By switching 3c by a switching instruction or an input / output control signal and using 16 bits of the address buses 47 and 48 as a data bus, 32-bit access of the data bus is performed. In this case, the memory area to be accessed needs to be in the range specified by the address data whose significant bits are 8 bits, for example, the memory area from address "00" to address "FF". is there.

In FIGS. 3 and 4, the flow of data sent from the MPU 2 to the memory 3 when accessing by the data bus of 32 bits is shown by a solid line, and the flow of data sent from the memory to the microprocessor 2 is shown. It is indicated by a broken line.

As described above, according to this embodiment, the switching circuit switches between the address bus and the data bus so that the address bus corresponding to the non-significant bit of the address data can be used as the data bus. Because it can be done, you can effectively use the address bus,
Memory access can be performed by expanding the data bus width to the required width.

Example 2. Next, another embodiment of the memory access method according to claims 1 to 4 and the semiconductor circuit device according to claims 16 to 19 will be described. FIG. 5 is a block diagram showing the configuration of a semiconductor circuit device that implements the memory access method of this embodiment. 5, parts that are the same as those shown in FIG. 2 are given the same reference numerals, and descriptions thereof will be omitted. In this embodiment, the address bus buffer also serves as the data bus buffer. In the figure, 33d is a switching circuit, which is the switching circuit 33 described in the first embodiment.
b (33c) has the same structure as that of the inverter circuit 9
The output of 2 is connected to the MPU internal data bus 53 or the MPU internal data bus 54, and the output of the inverter circuit 93 is connected to the MPU internal address bus 55.

That is, in the case of accessing with a normal data bus 16-bit width, first, the switching circuit in the MPU 2 is executed by executing the switching instruction for switching the internal connection of the switching circuits 33d and 33c or switching the signal line. The output of the 33d inverter circuit 93 is set to MPU2.
Connected to the internal address bus 55, and also the address bus 47
By (48), the switching circuit 33d and the switching circuit 33c on the memory 3 side are connected. Regarding the switching circuit 33c and the memory 3 on the memory 3 side, the output of the inverter circuit 93 of the switching circuit 33c is connected to the address bus of the memory 3. Then, the normal address bus of 24 bits and the data bus of 16 bits are made accessible.

In this case, in the data read, the address data output to the MPU internal address bus 55 is transmitted to the memory 3 using the address buses 47, 48 and 49, and the 16-bit width consisting of the data buses 45 and 46. Data is stored in the 16-bit register 36 included in the MPU 2 using the data bus. For writing data, a 24-bit address bus composed of address buses 47 to 49 and a 16-bit data bus composed of data buses 45 and 46 are used to write the value of the 16-bit register 36 in the MPU 2 to the 24-bit data. Write to the address specified by the address.

Further, in the case of accessing with the data bus 32 bit width, the output side of the inverter circuit 92 of the switching circuit 33d in the MPU 2 is first switched by switching instruction or signal line switching for switching the switching circuits 33d and 33c. Internal data bus 53 or M
Switching to connect to the PU internal data bus 54, and switching so that the output side of the inverter circuit 92 of the switching circuit 33c on the memory 3 side is connected to the expanded data bus of the memory 3 by the address bus 49. 8
Access is performed by 32 bits consisting of bit and data buses 45 and 46 and address buses 47 and 48 functioning as data buses.

In this case, in reading data from the memory 3, the address data output to the internal MPU address bus 55 is transmitted to the memory 3 by using 8 bits of the address bus 49, and the data buses 45, 46 and the data buses 45 and 46 are read. A 32-bit data bus having address buses 47 and 48 functioning as a bus is used, and data is stored in 16-bit registers 36 and 37 included in the MPU 2 by 16 bits.

Similarly, for writing data, the address data output on the 8-bit address bus 49 and the 32-bit data bus consisting of the data buses 45 and 46 and the address buses 47 and 48 functioning as the data buses are used. , The values stored in the 16-bit registers 36 and 37 in the MPU 2 are written to the address designated by the address data.

That is, in the case of 32-bit access to the data bus, the switching circuits 33d and 33c are switched by a switching instruction or the like to change the address bus 47, 48 to 16 bits.
Memory access is realized by 32 bits of the data bus by using the bit portion as the data bus. In this case, it is assumed that the address bus buffers 42 and 43 connected to the address bus used as the data bus have an input / output function and are substantially the same as the data bus buffer.

Next, in a memory access method capable of 32-bit data bus access by a switching instruction and a data transfer instruction of a predetermined bit (32 bits in this embodiment) and a semiconductor circuit device realizing the memory access method, A case will be described in which a switching instruction and a data transfer instruction for performing 32-bit data transfer are created as a single instruction to perform switching control of a switching circuit and memory access by a 32-bit data bus to reduce the number of instructions. .

FIG. 6 is an internal block diagram of the MPU 2 to which an instruction has been added. 6, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the figure, 111 is an interface unit and 112 is a code R.
OM, 113 internal bus, 114 is a control signal, 115 is a signal line connected to the switching circuit, 116 is a signal line for controlling the internal bus width, 117 is an arithmetic control unit including a control circuit, a register group and an ALU, 118 is a code ROM
Shows additional instructions (bus switching instruction, data transfer instruction). Here, the extended instruction or data is transmitted from the address bus 31 or the data bus 32 to the MPU 2 via the bus interface unit 111, and the data value and the address value related to the instruction are transmitted from the bus interface unit 111 to the internal bus 113. The output, the instruction is transmitted to the code ROM 112, is decoded by the code ROM 112 to which the instruction is added, and is output on the control signal 114 and the signal line 115 connected to the switching circuit and the signal line 116 for controlling the internal bus width. Signal line 116 for generating various control signals to be supplied, and controlling the signal supplied to the switching circuit by the signal line 115 connected to the control of the arithmetic control unit 117 and the switching circuit by these control signals and the internal bus width. The internal interface of the bus interface unit 111 depends on the signal output above. Switching control of width is performed.

When switching control of the switching circuit and 32-bit data bus access or normal 16-bit access of the memory 3 are executed by one instruction, the internal bus width is controlled by the signal line 116 for controlling the internal bus width. Until the switching of the internal bus width is completed, the bus interface unit 111 does not output the data value and the address value related to the instruction to the internal bus 113. 32-bit data transfer is performed using the bus 113.

Example 3. Next, claim 5 and claim 6
An embodiment of the described memory access method and the semiconductor circuit device according to claims 20 and 21 will be described. FIG. 7 is a block diagram showing the configuration of a semiconductor circuit device that implements the memory access method of this embodiment. In FIG. 7, parts that are the same as or correspond to those in FIG. 2 are assigned the same reference numerals and explanations thereof are omitted. In this embodiment, the SF of the memory 3 is
The SFR register 121 (bus switching information register) is set in the address of R. Further, 122 is a signal line connecting the SFR register 121 and the switching circuits 33a, 33b, 33c, and the input / output control signal and the switching signal according to the value written in the SFR register 121 are switching circuits 33a, 33b. , 33c are supplied to the input / output control signal line and the switching signal line.

Further, the MPU 2 is added with an instruction for 32-bit data transfer. By writing to the SFR register 121 and executing the 32-bit data transfer instruction,
Data bus 32-bit access is possible. further,
The cancellation can be done by rewriting the SFR register. In this case, the SFR register 121 in the SFR address has a status flag indicating the current operating state, and not only the writing of the value to the SFR register but also the SFR register is performed. The register data read operation can be performed. Further, it is assumed that a register capable of setting write conditions such as masking of write data to the SFR register or write prohibition to the SFR register is provided, and these are used according to the conditions when actually used.

Here, the operation when accessing with a normal data bus 16-bit width will be described. By writing a value to the SFR register 121, first, the buffer side of the switching circuit 33a is moved to the address bus buffers 42 and 43.
Switch to be connected to. The switching circuit 33b
Is switched so as to be connected to the address bus buffers 42 and 43, and further, the switching circuit 33 on the memory 3 side.
Also for c, the memory access is switched to a normal 16-bit width so that the normal address buses 47 to 49 can access 24 bits and the data buses 45 and 46 can access 16 bits.

In this case, for data read, the address data output to the MPU internal address bus 55 is transmitted to the memory 3 using the address buses 47 to 49, and the data bus 4 is read.
Data is transmitted to the built-in 16-bit register 36 of the MPU 2 using a 16-bit wide data bus composed of 5,46. Similarly, when writing data, the value of the 16-bit register 36 in the MPU 2 is output to the address buses 47 to 49 using the 24-bit width address bus and the 16-bit width data bus. Write to the specified address.

When accessing the data bus with a 32-bit width, the buffer side of the switching circuit 33a is connected to the data bus buffers 40 and 41 by writing a value in the SFR register 121. Further, a buffer connected to the switching circuit 33b is used as the data bus buffer 4
0, 41, and the connection between the memory 3 and the switching circuit 33c is switched so as to connect the address buses 47, 48 and the extended data buses 57, 58 on the memory 3 side. Bus 4
It is set to a 32-bit accessible state by 5 to 48. In this case, the data is read by transmitting the address indicated by the address data output to the address bus 55 in the MPU to the memory 3 by using 8 bits of the address bus 49, and the 32-bit width consisting of the data buses 45 to 48. The data is transmitted to the 16-bit registers 36 and 37 incorporated in the MPU 2 using the data bus. Similarly, for writing data, an 8-bit wide address bus 49 and data buses 45 to 4 are used.
Using a 32-bit data bus consisting of 8
The values stored in the 16-bit registers 36 and 37 in U2 are written to the address designated by the 8-bit wide address bus 49.

That is, when the data bus 32-bit access is performed, the switching circuits 33a, 33b, 33c are switched by writing a value to the SFR register 121, and 16 bits of the address buses 47, 48 are used as the data bus. This realizes 32-bit data bus access.

Example 4. Next, claim 7 and claim 8
An embodiment of the semiconductor circuit device according to claim 22 and claim 23 will be described. FIG. 8 is an explanatory diagram of a semiconductor circuit device that realizes the memory access method of this embodiment.
In the figure, reference numeral 300 denotes a microcomputer whose data bus is 16-bit width memory access mode, and 1
Reference numeral 32 represents a microcomputer switched to the data bus 32-bit width memory access mode. 1
Two types of operating environments, a data bus 16-bit width memory access mode and a data bus 32-bit width memory access mode, are realized by mode switching in one microcomputer, and each mode operates as a completely independent microcomputer.

In this case, the operation mode can be set by operating a predetermined changeover switch, or a command for setting the operation mode can be written at the beginning of the program to automatically perform the initialization process when the program is started. It can be configured so that the modes are switched automatically. Furthermore, by inserting an instruction to switch the operation mode in the original program,
It is also possible for one microcomputer to execute the original program while automatically switching between the data bus 16-bit width memory access mode and the data bus 32-bit width memory access mode according to the situation.

Example 5. Next, claim 9 and claim 1
An embodiment of the memory access method according to claim 0 and the semiconductor circuit device according to claims 24 and 25 will be described. FIG. 9 is a block diagram showing the configuration of a semiconductor circuit device that implements the memory access method of this embodiment. 9, the same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 9, 131 is the semiconductor circuit device 2.
00 is an external terminal, and the external terminal 131
Is connected to the switching circuits 33a, 33b, 33c.

In this embodiment, the switching circuits 33a, 33a
Input / output control signal line and switching signal line of b and 33c are newly set as the external terminal 131, and a command for 32-bit data transfer is further added to the MPU2 to input the input / output control signal and switching signal from the external terminal 131. By doing so, after switching the address bus to the data bus by the switching circuits 33a, 33b, 33c, by executing the 32-bit data transfer instruction, the data bus 32-bit access to the memory 3 is enabled. The external terminal in this case is not always one terminal, and the external terminal of the fourth embodiment
The signal line for each bit of the SFR register 121 in 1) or all the signal lines necessary for bus switching in the switching circuit may be set by signals input from external terminals.

First, the operation in the case of accessing the normal data bus with a 16-bit width will be described. External terminal 132
Switching circuit 33a by switching the input voltage of
Is connected to the address bus buffers 42 and 43. Further, the buffer connected to the switching circuit 33b is switched to the address bus buffers 42 and 43. The switching circuit 33c is also switched to a normal 16-bit width memory access so that the normal address bus 24 bits by the address buses 47 to 49 and the data bus 16 bits by the data buses 45 and 46 can be accessed. In this case, for reading data, the address indicated by the address data output to the MPU internal address bus 55 is transmitted to the memory 3 using the address buses 47 to 49, and the 16-bit width data bus composed of the data buses 45 and 46 is transferred. A 16-bit register 36 that uses the data in the MPU2
Tell. Similarly, data is written by using the 24-bit wide address bus and the 16-bit wide data bus.
The value stored in the 16-bit register 36 in PU2 is written in the address designated by the address data.

In the case of accessing the data bus with a 32-bit width, the switching circuits 33a, 33b, 33c are switched by a signal input from the external terminal 131 so that the switching circuit 33a is first connected to the data bus buffers 40, 41. And the buffers connected to the switching circuit 33b are switched to the data bus buffers 40 and 41. For the switching circuit 33c, the address buses 47 and 4 are connected.
8 and the extended data buses 57 and 58 on the side of the memory 3 are connected to each other, and the address data of the address bus 49 is 8 bits, and the data buses 45 and 46 and the address buses 47 and 48 functioning as data buses are 32 bits of data. Realize access.

In this case, for reading data, the address indicated by the address data output to the MPU internal address bus 55 is transmitted to the memory 3 using 8 bits of the address bus 49, and the 32-bit wide data bus is used. And data is M
It is transmitted to the built-in 16-bit registers 36 and 37 of PU2. Similarly, for writing data, the value stored in the 16-bit registers 36 and 37 is written to the address designated by the address data using the 8-bit width address bus and the 32-bit width data bus. .

That is, in the case of 32-bit access to the data bus, by switching the input signal of the external terminal 131, all the switching circuits 33a, 33b and 33c are switched, and 16 bits of the address buses 48 and 49 are transferred to the data bus. The data bus 32-bit access is performed by using this as.

Example 6. Next, claims 11 to 15
A memory access method according to claim 26, and claim 26 to claim 3.
An example of the semiconductor circuit device described in 0 will be described.

FIG. 10 is a block diagram showing a part of the configuration of a switching circuit of a semiconductor circuit device which realizes a memory access method according to an embodiment of the invention of claims 11 to 15 and claim 26 to claim 30. Is. The other parts have the same configuration as that of FIG. 2 described in the first embodiment. In the figure, reference numeral 141 is a bit unit switching circuit for switching an address bus and a data bus in bit units,
It corresponds to the switching circuits 33a, 33b, 33c in FIG. Reference numeral 142 denotes an input / output control signal connected to the bit unit switching circuit 141, 143 similarly a switching signal line, 14
4 and 146 are data buses connected to the bit unit switching circuit 141, and 145 and 147 are also address buses and 1
Reference numeral 48 is a data write address decoder (bus changing means) for writing data to the register / decoder 149 (bus changing means). Reference numeral 150 denotes a switching circuit (bus changing means) for 1 bit, which is shown in FIG.
Alternatively, the circuit configuration shown in FIG. 4 is used.

In this embodiment, the MPU is used as the register / decoder 149 for controlling the switching of the address bus / data bus by using the data write address degoder 148.
By writing the distribution data output from 2, the distribution of the address bus and data bus of 1 to 16 bits is set, the operating environment of the circuit in each bit unit is specified, and further, the input / output control signal and switching By inputting a signal, it is determined whether the bus connected to the switching circuit 150 functions as an address bus or a data bus.
The memory is accessed by flexibly changing the bit width to 32 bits.

It should be noted that in the above-described embodiment, 1 to 1 is based on the input / output control signal, the switching signal and the distribution data.
When distributing the address bus and data bus of up to 6 bits, set the distribution instruction that outputs the I / O control signal, the switching signal, and the distribution data to the bit unit switching circuit, and execute this distribution instruction to set the bit unit. Can be distributed.

Further, instead of the register / decoder 149, the SFR register 121 set in the memory 3 shown in FIG.
May be configured to be used.

Further, the allocation in bit units may be set as respective modes as shown in FIG.

Further, each external terminal corresponding to each bit unit allocation is provided, and as shown in FIG. 9, each bit unit allocation is set based on the signal input from each external terminal. You may.

Example 7. In the first to sixth embodiments described above, the case where the non-essential address bus of the total 40 signal lines of the address bus and the data bus is switched to the data bus for access has been described. In the example, the case where the address bus and the data bus are multiplexed will be described. FIG. 11 shows the configuration when an external memory access is performed by using a switching circuit in the memory access of the data bus 32 bits. 11, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the figure, 152a and 15
Reference numeral 2b indicates an address decoder. Switching circuit 3
3, 155 functions to switch the address bus to the data bus as in the first embodiment. Further, the address decoders 152a and 152b connect the microcomputer 200 having a small number of external terminals and the external memory 156 by switching the data bus and the address bus with respect to time. 151 is a microcomputer 200
And an external memory 156, which are an address bus and a data bus composed of 32 signal lines in total. 153 is an address bus composed of eight signal lines, and 15
Reference numeral 4 is a data bus composed of 32 signal lines.

For data reading, the data at the memory address designated by the 24-bit address bus 31 is read from the external memory by the MPU 2, and the switching circuit 155 → data bus 154 → address decoders 152a, 152b →
It is transmitted to the MPU 2 via the switching circuit 33. Data is written to the MPU at the address specified by the address bus 31.
The data output from 2 to the data bus 35 is written in the external memory (3) via the address decoder 152a → address decoder 152b → switching circuit 155.
Regarding the widths of the address bus and the data bus, the switching circuit 33 in the microcomputer 200 switches 16 bits of the address bus 31 to the data bus. Access is possible with a book and 32 data buses. The address decoder 152a inside the microcomputer 200 is connected to the address decoder 152b outside the microcomputer 200 by a bus 151 composed of 32 signal lines.

The external memory 3 side is also the microcomputer 2
Similarly to the inside of 00, the switching circuit 155 switches 16 bits of the address bus to the data bus, and 32 signal lines connect the address decoder 152b to the address decoder 152a inside the microcomputer. Here, although the connection between the external memory 156 and the switching circuit 155 is omitted in the figure, they are connected by 24 address buses and 16 data buses. Further, the switching circuit 1 of the external memory 156 is connected.
55 can be provided as an independent circuit outside the external memory 156.

Example 8. Next, FIG. 12 shows a concrete example of the configuration in the case where the external memory access is performed by using the switching circuit in the 32-bit memory access of the data bus described in FIG. 11 in the seventh embodiment. FIG. 13 is a timing chart when an external memory is accessed by a 16-bit data bus using a 24-bit bus, and FIG. 14 is an external memory accessed by a 32-bit internal data bus using a 24-bit bus. 6 is a timing chart when performing the above, and shows a case where the address decoders 152a and 152b are multiplexed. 2 and 11 in FIG.
The same or corresponding parts are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 12, 160 is a switching circuit 33.
Switching signal lines connecting a, 33b, and 33c, 161 is a 24-bit address bus and data bus, 162 to
165 is an external terminal of the microcomputer 200, 16
6 to 171 are external terminals of the external memory 156, 172-1
75 is a data bus connecting the external memory 156 and the address decoder 152b, and 176 to 178 are also address buses.

When accessing with a 16-bit width of a normal data bus, a switching command for switching the switching circuits 33a, 33b, and 33c or switching of the signal line 160 is performed. Connect to 43. Further, the buffers connected to the switching circuit 33b are switched to the address bus buffers 42 and 43, and the switching circuit 33c on the external memory 156 side is also switched to a normal 16-bit width memory access.
A 16-bit data bus access is realized. In this case, for data reading, the address indicated by the address data output to the 24-bit wide address bus 55 in the MPU 2 is transmitted to the external memory 156 via the switching circuit 33a → address decoder 152a → address decoder 152b, and externally The 16-bit data read from the memory 156 is transmitted to the built-in 16-bit register 36 of the MPU 2 via the 16-bit wide data bus and the address decoder 152b and the like. Similarly, for writing data, using the 24-bit address bus 55 and the 16-bit data bus, the switching circuit 33a and the switching circuit 33b can be similarly written.
Switch circuit 33c, address decoders 152a, 15
The value of the 16-bit register 36 in the MPU 2 is written to the address designated by the address bus 55 via 2b.

Further, in the case of accessing the data bus 32 bits wide, first, the switching side of the switching circuit 33a is switched to the data bus buffer 40 by switching the switching command or the signal line 160 for switching the switching circuits 33a, 33b and 33c. 41, and a buffer connected to the switching circuit 33b is a data bus buffer 4
0, 41, and the switching circuit 33c on the external memory 156 side is also switched to connect the address bus connected to the address decoder 152b and the extended data buses 174, 175 on the external memory 156 side.
Access is realized with an 8-bit address bus and a 32-bit data bus.

In this case, for data reading, 8 bits of the address data output to the MPU internal address bus 55 are transmitted to the external memory 156 via the address decoder 152a, and 32 bits are transmitted from the external memory 156. The width of the data bus is used for reading, and the MPU is passed through the switching circuit 33c and the address decoders 152b and 152a.
2 is transmitted to the built-in 16-bit registers 36 and 37.

For data writing, an address bus having an 8-bit width and a 32-bit data bus are used inside the microcomputer 200 and on the side of the external memory 156, and the switching circuit 33a, the switching circuit 33b, and the switching circuit 33 are used.
c, via address decoders 152a and 152b,
The values of the 16-bit registers 36 and 37 in the MPU 2 are written to the address designated by the address data output to the address bus.

That is, in the case of 32-bit data bus access, 32-bit access of the data bus is performed by using 16 bits of the address bus as the data bus by the switching circuits 33a, 33b and 33c.

[0164]

As described above, according to the first aspect of the present invention, the memory is accessed by using the address bus corresponding to the non-significant bit of the address data designating the memory area to be accessed as the data bus. Since it is configured as described above, there is an effect that memory access that effectively utilizes the address bus is realized.

According to the second aspect of the present invention, the address bus corresponding to the non-significant bit of the address data designating the memory area to be accessed is used as the data bus and is used together with the original data bus. As a result, the effective use of the address bus can be realized, and further, the data bus width can be expanded to obtain a memory access method capable of memory access.

According to the third aspect of the present invention, there is provided a bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, and a data transfer instruction for transferring data corresponding to the predetermined number of bits. In addition, since the address bus corresponding to the non-significant bit of the address data that specifies the memory area to be accessed is switched to the data bus, and the switched data bus transfers data, the memory is accessed. There is an effect that a memory access method capable of performing memory access by effectively utilizing the address bus is obtained.

According to the invention of claim 4, a bus switching instruction for switching the address bus corresponding to the predetermined number of bits of the address data to the data bus, and a width corresponding to the predetermined number of bits and the original number of bits of the data bus. Based on a data transfer instruction that transfers data, the address bus corresponding to the non-significant bit of the address data that specifies the memory area to be accessed is switched to the data bus, and the switched data bus and the original data bus are used. Since the configuration is such that data transfer is performed and memory access is performed, effective use of the address bus is realized, and there is an effect that a memory access method capable of memory access is obtained by expanding the data bus width.

According to the fifth aspect of the invention, the bus switching information register for storing the information indicating the bus switching state set in the memory to be accessed and the data transfer corresponding to the predetermined number of bits of the switched data bus are transferred. Memory access for effectively accessing the memory by setting the bus switching based on the data transfer instruction to perform the data transfer and transferring the data through the data bus to access the memory. There is an effect that the method can be obtained.

According to the sixth aspect of the invention, the bus switching information register for storing information indicating the bus switching state set in the memory to be accessed and the predetermined number of bits switched to the data bus and the original data bus Based on the data transfer instruction that transfers the data corresponding to the number of bits, the data bus is transferred by the switched data bus and the original data bus to access the memory. There is an effect that a memory access method that can be utilized and further has a data bus width expanded and capable of memory access can be obtained.

According to the seventh aspect of the invention, since the address bus corresponding to the predetermined number of bits of the address data is switched to the data bus for the memory access according to the mode set in the microprocessor, the address bus is enabled. There is an effect that a memory access method can be obtained in which the memory is accessed by utilizing it, or the address bus is effectively used and the data bus width is expanded to perform the memory access.

According to the invention of claim 8, the address bus is switched to the data bus for memory access based on the mode set in the microprocessor and the data of the bus switching information register. Therefore, the address bus is enabled. There is an effect that a memory access method can be obtained in which the memory is accessed by utilizing it, or the address bus is effectively used and the data bus width is expanded to perform the memory access.

According to the invention of claim 9, the address bus is switched to the data bus based on the bus switching signal inputted from the external terminal to perform the memory access. Therefore, the memory can be effectively utilized by utilizing the address bus. There is an effect that a memory access method can be obtained in which the data access is performed or the address bus is effectively used and the data bus width is expanded to perform the memory access.

According to the tenth aspect of the invention, the address bus is switched to the data bus based on the bus switching signal input from the external terminal to perform the memory access. There is an effect that a memory access method for performing memory access by performing access or effectively utilizing the address bus and expanding the data bus width can be obtained.

According to the eleventh aspect of the present invention, the address bus and the data bus are switched and distributed according to the use condition, the widths of the address bus and the data bus are changed according to the use condition, and the memory is accessed by the data transfer instruction. Since it is configured to perform the memory access, there is an effect that a memory access method for flexibly allocating the address bus and the data bus according to the use status to perform the memory access can be obtained.

According to the twelfth aspect of the present invention, a switching instruction for switching between the address bus and the data bus having the number of bits according to the use condition is switched by the number of bits according to the use condition. Since the memory access method is configured to perform the memory access, the memory access method can be obtained in which the width of the address bus and the data bus is flexibly changed according to the usage status to perform the memory access.

According to the thirteenth aspect of the present invention, the address bus and the data bus are switched according to the usage conditions based on the bus switching information register which is set in the memory to be accessed and which stores the information indicating the bus switching state. Since the memory access method is configured to access the memory, there is an effect that a memory access method can be obtained in which the width of the address bus and the data bus is flexibly changed according to the usage status to perform the memory access.

According to the fourteenth aspect of the present invention, since the address bus and the data bus are switched by switching between the address bus and the data bus according to the usage conditions according to the mode set in the microprocessor, the address bus and the data bus can be accessed. There is an effect that a memory access method is obtained in which the bus width is flexibly changed according to the usage status to perform memory access.

According to the fifteenth aspect of the invention, the memory access is performed by switching between the address bus and the data bus according to the use condition based on the bus switching signal input from the external terminal. There is an effect that a memory access method capable of performing memory access according to the widths of the address bus and the data bus, which are flexibly changed according to the usage situation, can be obtained.

According to the sixteenth aspect of the invention, the bus switching means for switching the address bus corresponding to the non-significant bit of the address data designating the memory area to be accessed to the data bus is provided. There is an effect that a semiconductor circuit device capable of performing memory access by effectively utilizing the bus can be obtained.

According to the invention of claim 17, a bus switching means for switching the address bus corresponding to the non-significant bit of the address data designating the memory area to be accessed to the data bus, and the data bus switched from the address bus. And the original data bus are used together to expand the original data bus width to provide memory access means for accessing the memory, so that the address bus can be effectively used, and the expanded data bus There is an effect that a semiconductor circuit device capable of memory access by width can be obtained.

According to the eighteenth aspect of the present invention, there is provided a bus switching instruction for switching the address bus to the data bus and a data transfer instruction for transferring the data, and the bus switching means sets the address bus to the data bus by the bus switching instruction. Since it is configured to switch to, it is possible to obtain a semiconductor circuit device that makes effective use of the address bus to perform memory access.

According to the nineteenth aspect of the present invention, there is provided a bus switching instruction for switching the address bus to the data bus and a data transfer instruction for transferring the data, and the bus switching means corresponds to the non-significant bit of the address data. Since the address bus is configured to be switched to the data bus by executing the bus switching instruction, the address bus can be effectively used, and the semiconductor circuit device capable of memory access with the expanded data bus width can be obtained. is there.

According to the twentieth aspect of the present invention, there is provided a bus switching information register for storing information indicating a bus switching state set in the memory to be accessed, and the bus switching information register and data transfer for transferring data. Since the memory access means for transferring data by the data bus based on the instruction and for accessing the memory is provided, the semiconductor circuit device for performing the memory access by effectively utilizing the address bus can be obtained.

According to the twenty-first aspect of the present invention, the bus switching information register for storing information indicating the bus switching state set in the memory to be accessed, the bus switching information register and the switched data bus are the original Since the memory access means for accessing the memory is provided based on the data transfer instruction for transferring the data by the data bus, the address bus can be effectively utilized and the memory access by the expanded data bus width is possible. There is an effect that a semiconductor circuit device can be obtained.

According to the twenty-second aspect of the invention, since the mode setting means for setting the mode for switching the address bus to the data bus is provided, the memory can be accessed by effectively utilizing the address bus, or the address bus can be used. There is an effect that a semiconductor circuit device capable of memory access with an expanded data bus width can be obtained by effectively utilizing the above.

According to the twenty-third aspect of the invention, the mode setting means for setting the mode for switching the address bus to the data bus is provided, and the bus switching means is configured to switch the address bus to the data bus according to the set mode. There is an effect that a memory access is performed by effectively utilizing the address bus, or a semiconductor circuit device capable of performing memory access by effectively utilizing the address bus and having an expanded data bus width is obtained.

According to the twenty-fourth aspect of the invention, an external terminal to which a bus switching signal is input is provided, and the bus switching means switches the address bus to the data bus based on the bus switching signal input from the external terminal. Since it is configured, there is an effect that a semiconductor circuit device that effectively utilizes the address bus to perform memory access, or effectively utilizes the address bus and performs memory access with an expanded data bus width can be obtained.

According to the twenty-fifth aspect of the present invention, when the address bus corresponding to the predetermined number of bits of the address data is switched to the data bus, the data transfer instruction for transferring the data corresponding to the predetermined number of bits or the address data A data transfer instruction for transferring data having a width corresponding to the predetermined number of bits and the original number of bits of the data bus when switching the address bus corresponding to the predetermined number of bits to the data bus, and a bus switching signal are input externally. Since the bus switching means is configured to switch the address bus corresponding to the predetermined number of bits of the address data to the data bus based on the bus switching signal input from the external terminal, the bus can be effectively used. Memory access, or effective use of the address bus The effect of the semiconductor circuit device which performs memory access by bus are placed width is obtained.

According to the twenty-sixth aspect of the present invention, the address bus and the data bus are switched and distributed according to the use conditions,
Bus changing means for changing the widths of the address bus and the data bus according to usage conditions, a data transfer instruction for handling data of a predetermined number of bits, and the memory for transferring the data by the assigned data bus by the data transfer instruction. Since it is configured to include a memory access unit that accesses the memory, there is an effect that a semiconductor circuit device capable of memory access by an address bus and a data bus that are flexibly distributed according to a use situation can be obtained.

According to the twenty-seventh aspect of the present invention, there is provided a switching instruction for switching the address bus and the data bus in accordance with the use condition, and the bus changing means executes the switching instruction so that the address bus and the data in accordance with the use condition are obtained. Since the configuration is such that switching is performed between the bus and the bus, there is an effect that a semiconductor circuit device capable of memory access by an address bus and a data bus, which are flexibly distributed according to a use situation, can be obtained.

According to the twenty-eighth aspect of the present invention, there is provided a bus switching information register for storing information indicating a bus switching state set in the memory to be accessed, and the bus changing means is based on the bus switching information register. Since it is configured to switch to the address bus and the data bus according to the usage conditions, there is an effect that a semiconductor circuit device capable of memory access by the address bus and the data bus flexibly allocated according to the usage status can be obtained. is there.

According to the twenty-ninth aspect of the invention, there is provided mode setting means for switching the address bus and the data bus in accordance with the use conditions and setting a mode for changing the widths of the address bus and the data bus in accordance with the use conditions. The bus changing unit changes the widths of the address bus and the data bus according to the use condition based on the set mode, and the memory access unit uses the data bus switched by the data transfer instruction after the mode is set. Since it is configured to transfer data and perform memory access, there is an effect that a semiconductor circuit device capable of memory access by an address bus and a data bus that are flexibly distributed according to the usage situation can be obtained.

According to the thirtieth aspect of the present invention, there is provided an external terminal to which the bus switching signal is inputted, and the bus changing means is based on the bus switching signal inputted from the external terminal, and the address bus according to the use condition. Since the memory access means is configured to access the memory by transferring data by the data bus by a data transfer command after the bus switching signal is input from the external terminal, There is an effect that a semiconductor circuit device capable of memory access by an address bus and a data bus, which are flexibly distributed according to a use situation, can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor circuit device that implements a memory access method according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a semiconductor circuit device that implements a memory access method according to a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a switching circuit of a semiconductor circuit device that realizes a memory access method according to a first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a switching circuit of a semiconductor circuit device that realizes a memory access method according to a first embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a semiconductor circuit device that implements a memory access method according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an MPU of a semiconductor circuit device which realizes a memory access method according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a semiconductor circuit device that implements a memory access method according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a semiconductor circuit device that implements a memory access method according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a semiconductor circuit device that implements a memory access method according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a bit unit switching circuit of a semiconductor circuit device that realizes a memory access method according to a sixth embodiment of the present invention.

FIG. 11 is a block diagram showing the configuration of a semiconductor circuit device that implements a memory access method according to a seventh embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a semiconductor circuit device that implements a memory access method according to an eighth embodiment of the present invention.

FIG. 13 is a timing chart showing an access to an external memory according to an eighth embodiment of the present invention through 16 bits of a multiplexed data bus.

FIG. 14 is a timing chart showing an access by an multiplexed data bus 32 bits to an external memory according to an eighth embodiment of the present invention.

FIG. 15 is an explanatory diagram showing memory access to a conventional internal memory.

FIG. 16 is an explanatory diagram showing memory access to a conventional external memory.

FIG. 17 is a block diagram showing the inside of a conventional MPU.

[Explanation of symbols]

2 MPU (memory access means, bus switching means, mode setting means, bus changing means) 3 memory 31, 34, 47, 48, 49 address bus 32, 35, 45, 46 data bus 33, 33a, 33b, 33c, 33d , 150, 15
5 switching circuit (bus switching means, bus changing means) 118 additional instruction (bus switching instruction, data transfer instruction) 121 SFR register (bus switching information register) 131 external terminal 148 data write address decoder 149 register decoder (bus changing means) ) 156 External memory

Claims (30)

[Claims] 1. A data read to output data stored in a memory to a data bus based on address data on the address bus, or a memory address by specifying a memory address based on the address data on the address bus In the memory access method for writing the above data, a memory access method is used in which an address bus corresponding to a non-significant bit of address data that specifies a memory area to be accessed is used as a data bus. 2. Data reading for outputting data stored in a memory to a data bus based on address data on the address bus, or data writing by designating an address of the memory based on the address data on the address bus. In the memory access method of performing the above, the address bus corresponding to the non-significant bit of the address data that specifies the memory area to be accessed is used as the data bus and is used together with the original data bus to obtain the original data bus width. A memory access method that extends the memory to access the memory. 3. A memory to be accessed based on a bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus and a data transfer instruction for transferring data corresponding to the predetermined number of bits. 2. The memory access method according to claim 1, wherein the address bus corresponding to the non-significant bit of the address data designating the area is switched to the data bus, and the data is transferred by the switched data bus to access the memory. 4. A bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, and a data transfer for transferring data having a width corresponding to the predetermined number of bits and the original number of bits of the data bus. Based on the instruction, the address bus corresponding to the non-significant bit of the address data that specifies the memory area to be accessed is switched to the data bus, and data is transferred by the switched data bus and the original data bus. The memory access method according to claim 2, wherein access is performed. 5. A bus switching information register for storing information indicating a bus switching state set in a memory to be accessed is provided, which corresponds to the information of the bus switching information register and a predetermined number of bits of a switched data bus. 2. The memory access method according to claim 1, wherein data is transferred by the data bus to access a memory based on a data transfer instruction for transferring data. 6. A bus switching information register for storing information indicating a bus switching state set in a memory to be accessed, the information of the bus switching information register and a predetermined number of bits switched to a data bus and an original 3. The memory is accessed by transferring data through the data bus based on a data transfer instruction that transfers data corresponding to the number of bits of the data bus.
The memory access method described. 7. Instead of a bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, an address bus corresponding to a predetermined number of bits of address data is set to a data bus according to a mode set in a microprocessor. 5. The memory access method according to claim 3, wherein the memory access method is switched to. 8. The address bus corresponding to a predetermined number of bits of address data is switched to the data bus based on the mode set in the microprocessor and the information in the bus switching information register. The memory access method described. 9. Instead of a bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, a predetermined number of bits of address data is supported based on a bus switching signal input from an external terminal. 5. The memory access method according to claim 3, wherein the address bus is switched to the data bus. 10. The memory access according to claim 5, wherein an address bus corresponding to a predetermined number of bits of address data is switched to a data bus based on a bus switching signal input from an external terminal. Method. 11. A data read operation for outputting data stored in a memory to a data bus based on address data on the address bus, or a data write operation for designating an address of the memory based on the address data on the address bus. In the memory access method to be performed, the address bus and the data bus are distributed by switching to the address bus and the data bus having the number of bits according to the use condition, and the widths of the address bus and the data bus are changed according to the use condition to set a predetermined bit. A memory access method for accessing the memory according to a data transfer instruction for handling minute data. 12. A switching instruction for switching between the address bus and the data bus having the number of bits according to the use conditions and switching the address bus and the data bus to the address bus and the data bus having the number of bits according to the use conditions. 12. The memory access method according to claim 11, which is performed by. 13. A bus switching information register for storing information indicating a bus switching state set in a memory to be accessed, and an address having a bit number according to a usage condition based on the information of the bus switching information register. 12. The memory access method according to claim 11, wherein the bus and the data bus are switched to transfer data by the data bus to access the memory. 14. A memory access is performed by switching between an address bus and a data bus having a number of bits according to a use condition according to a mode set in a microprocessor to transfer data by the data bus. The memory access method described. 15. An access to a memory is performed by switching between an address bus and a data bus having a bit number according to a use condition based on a bus switching signal input from an external terminal to transfer data by the data bus. 12. The memory access method according to claim 11, wherein: 16. A data read operation for outputting the data stored in the memory onto the data bus based on the address data output onto the address bus, or an address designation based on the address data output onto the address bus. In a semiconductor circuit device capable of accessing a memory for writing data on a data bus to a memory, a bus switching means for switching an address bus corresponding to a non-significant bit of address data designating a memory area to be accessed to a data bus A semiconductor circuit device comprising: 17. A data read operation for outputting the data stored in the memory onto the data bus based on the address data output onto the address bus or an address designation based on the address data output onto the address bus. In a semiconductor circuit device capable of accessing a memory for writing data on a data bus to a memory, a bus switching means for switching an address bus corresponding to a non-significant bit of address data designating a memory area to be accessed to a data bus And a memory access means for expanding the original data bus width and accessing the memory by using both the data bus switched from the address bus by the bus switching means and the original data bus. Semiconductor device. 18. A bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, and a data transfer instruction for transferring data corresponding to the predetermined number of bits. 17. The semiconductor circuit device according to claim 16, wherein an address bus corresponding to a predetermined number of bits of address data is switched to a data bus by a bus switching instruction. 19. A bus switching instruction for switching an address bus corresponding to a predetermined number of bits of address data to a data bus, and data transfer for transferring data of a width corresponding to the predetermined number of bits and the original number of bits of the data bus. The bus switching means has an instruction and switches the address bus corresponding to the non-significant bit of the address data designating the memory area to be accessed to the data bus by executing the bus switching instruction. Claim 1
7. The semiconductor circuit device according to 7. 20. A bus switching information register for storing information indicating a bus switching state set in a memory to be accessed is provided, which corresponds to the information of the bus switching information register and a predetermined number of bits of a switched data bus. 19. The semiconductor circuit device according to claim 18, further comprising a memory access unit that transfers data by the data bus and accesses the memory based on a data transfer instruction for transferring data. 21. A bus switching information register that stores information indicating a bus switching state set in a memory to be accessed, information in the bus switching information register, the number of bus bits switched to a data bus, and original data. 20. The semiconductor circuit device according to claim 19, further comprising: memory access means for accessing the memory by transferring data by the data bus based on a data transfer instruction for transferring data corresponding to the number of bits of the bus. 22. Mode setting means for setting a mode for switching an address bus corresponding to a predetermined number of bits of address data to a data bus instead of a bus switching instruction,
20. The semiconductor circuit device according to claim 18 or 19, wherein the bus switching means switches the address bus to the data bus based on the mode set by the mode setting means. 23. Mode setting means for setting a mode for switching an address bus corresponding to a predetermined number of bits of address data to a data bus instead of a bus switching instruction,
22. The semiconductor circuit device according to claim 20, wherein the address bus corresponding to the predetermined number of bits of the address data is switched to the data bus according to the mode set by the mode setting means. 24. An external terminal for inputting a bus switching signal is provided, and the bus switching means corresponds to a predetermined number of bits of address data based on the bus switching signal input from the external terminal instead of the bus switching instruction. 17. The semiconductor circuit device according to claim 16, wherein the address bus is switched to a data bus. 25. A data transfer instruction for transferring data corresponding to the predetermined number of bits when switching the address bus corresponding to the predetermined number of bits of the address data to the data bus, or an address corresponding to the predetermined number of bits of the address data. The bus switching means includes a data transfer instruction for transferring data having a width corresponding to the predetermined number of bits when switching the bus to the data bus and the original number of bits of the data bus, and an external terminal to which a bus switching signal is input. Is based on the bus switching signal input from the external terminal,
17. An address bus corresponding to a predetermined number of bits of address data is switched to a data bus.
Alternatively, the semiconductor circuit device according to claim 17. 26. Data reading for outputting the data stored in the memory to the data bus based on the address data output to the address bus or designating an address based on the address data output to the address bus. In a semiconductor circuit device that writes data on a data bus to a memory, the address bus and the data bus are switched by switching between the address bus and the data bus having the number of bits according to the usage conditions, and the widths of the address bus and the data bus are divided. Bus change means for changing according to use conditions, a data transfer instruction for handling data of a predetermined bit, and memory access means for accessing the memory by transferring data by the data bus by the data transfer instruction Semiconductor circuit device. 27. A switching instruction for switching the address bus and the data bus to the address bus and the data bus having the number of bits according to the usage conditions, and the bus changing means executes the switching instruction to thereby set the bits according to the usage conditions. 27. The semiconductor circuit device according to claim 26, wherein the number of address buses and the number of data buses are switched. 28. A bus switching information register, which stores information indicating a bus switching state set in a memory to be accessed, is provided, and the bus changing means is based on the information of the bus switching information register and is adapted to a use condition. 27. The semiconductor circuit device according to claim 26, wherein the address bus and the data bus having the number of bits are switched. 29. A mode for setting a mode in which the address bus and the data bus are distributed by switching to the address bus and the data bus having the number of bits according to the use condition, and the width of the address bus and the data bus is changed according to the use condition. The bus changing means changes the width of the address bus and the data bus according to the use condition based on the mode set by the mode setting means, and the memory access means changes the data after the mode is set. 27. The semiconductor circuit device according to claim 26, wherein data is transferred by the data bus in accordance with a transfer instruction to access the memory. 30. An external terminal for inputting a bus switching signal is provided, and the bus changing means has an address bus and a data bus having a bit number according to usage conditions based on the bus switching signal input from the external terminal. 27. The memory access means accesses the memory by transferring data by the data bus according to a data transfer command after a bus switching signal is input from the external terminal. Semiconductor circuit device.