JPH07254274A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a storage device not operated erroneously even when noises are generated from a memory cell array by arranging a word-line noise killer array between the memory cell array and a word-line driver circuit array. CONSTITUTION:A word-line noise killer circuit array 102 formed by NMOSFETs is disposed between a memory cell array 100 and a word-line driver circuit 101 formed by NMOS and PMOSFETs. The array 100 and the array 101 are separated mutually by the arrangement, and the noise interference of the array 100 and the array 101 is inhibited. Accordingly, a semiconductor storage device capable of preventing a malfunction even when noises are generated from the memory cell array is manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a word line selection circuit for selectively driving word lines.

[0002]

2. Description of the Related Art With the high integration of semiconductor memory devices, there is an increasing demand for lowering the power supply voltage VCC and increasing the read speed. FIG. 21 is a block diagram of a conventional word line selection circuit. In FIG. 21, the P channel MO
The boosted potential VPP is supplied to the source of the S transistor (PMOSFET). The boosted potential VPP is higher than a power supply voltage (VCC) given from the outside. Boosted potential VPP is usually generated by using a boosted potential generation circuit (not shown) provided inside the chip. N-channel MOS transistor (NMOSFET)
The ground potential VSS is supplied to the source of the. Drain of P channel MOS transistor and N channel M
The word line WL connected to the memory cell is connected to the drain of the OS transistor. P channel MOS
The gates of the transistors and the gates of the N-channel MOS transistors are commonly connected, and a row decoder supplied with the power supply voltage VCC as a power supply is connected via a level conversion circuit. The row decoder is controlled by a control signal such as an address signal or a precharge signal, and the VC is selectively selected according to the signal level of the control signal.
C system output signal (H level is VCC level output signal)
Outputs S _VCC . The level of the output signal of the VCC system is converted into a signal of the VPP system (a signal whose H level is the VPP level) S _VPP by the level conversion circuit, and the converted signal is the gate of the P channel MOS transistor and the gate of the N channel MOS transistor. Is being supplied to.

In the conventional technique disclosed in FIG. 21, a PMOSFET for driving the word line is provided between the word line and the boosted potential VPP. This PMOS FE
T is used instead of the boot strap circuit used in the normal word line selection circuit. The boot strap circuit is an NMO for driving the word line in order to reduce the power supply voltage and speed up the time for selecting the word line.
It consists of SFET and isolation transistor.

As described above, when the PMOSFET is used instead of the boot strap circuit, the control signal input to the gate is a VPP control signal (H level is V level).
Control signal which is PP). Because V
CC control signal (control signal whose H level is VCC)
This is because, when the PMOSFET is controlled by, when the H level (VCC) is input to the gate, the source voltage is VPP, so that the PMOSFET is not completely turned off. Therefore, the signal for controlling the gate of the PMOSFET needs to be a VPP system control signal, but the output of the row decoder is a VCC system control signal, so it is necessary to convert the signal level from the VCC level to the VPP system level. is there. Therefore, the row decoder and P
It is necessary to provide a level conversion circuit with the MOSFET.

A storage device of this type is, for example, USPate.
nt Number 4,344,005. In addition, U.
S.Patent Number 4,344,005 discloses a word line killer circuit in addition to the level conversion circuit. The word line killer circuit sets another word line to the ground potential when the boosted potential is supplied to the certain word line. The word line killer circuit is driven by the killer drive circuit. This killer drive circuit, like the level conversion circuit, has a boosted potential VP.
Let P be the power source.

FIG. 22 is a circuit diagram of another conventional word line selection circuit. In FIG. 22, what corresponds to the level conversion circuit is a PMOSFET provided in a row decoder portion in each word line selection circuit and having respective gates cross-coupled (see broken line frame LS).

A storage device of this type is, for example, an IEEE JOU.
RNAL OF SOLID-STATE CIRCUITS, VOL.26.NO.8, AUGUST
1991, pp. 1171 to 1175. Also,
JP-A-4-106794 discloses an EPROM. In the EPROM disclosed herein, the address signal groups are level-converted and then input to the row decoder.

[0008]

However, these conventional techniques have the following problems. First, the memory device shown in FIGS. 21 and 22 requires a large number of level conversion circuits. This is because a level conversion circuit must be provided for each word line selection circuit. For example, in FIG.
The technique shown in FIG. 22 requires level conversion circuits for the number of word lines.

Similarly, in a memory device in which the level of each address signal group is converted and then input to the row decoder,
Many level conversion circuits are required. This is because a level conversion circuit must be provided for each address signal line.

As the number of level conversion circuits increases, the chip area increases. At the same time, since the level conversion circuit uses the boosted potential VPP as a power supply, the consumption amount of the boosted potential VPP increases.

Secondly, the consumption of the boosted potential VPP is increased even when a large number of circuits using the boosted potential VPP as a power source exist in the chip in addition to the level conversion circuit. Boosted potential V
As the consumption of PP increases, the potential of the boosted potential VPP easily changes. In particular, the level of boosted potential VPP tends to decrease. In order to suppress the fluctuation of the boosted potential VPP, a sufficient boosted potential VPP must be supplied to the boosted potential wiring. In order to supply a sufficient boosted potential VPP to the boosted potential wiring, the area of the boosting capacitor of the boosted potential generation circuit must be increased. As the area of the boosting capacitor increases, the chip area increases.

Thirdly, the level conversion circuit must be arranged near the memory cell array in the chip layout. The memory cell array generates noise. The level conversion circuit may malfunction due to the noise. As the memory integration density increases, the memory cell array generates more noise. Therefore,
In a dynamic RAM of 64 Mbits or 256 Mbits or more, the level conversion circuit is more likely to malfunction.

The present invention has been made especially in view of the above third point, and an object thereof is to provide a semiconductor memory device which does not malfunction even if noise is generated from the memory cell array.

[0014]

In order to achieve the above object, in a semiconductor memory device according to the present invention, a word line noise killer circuit array is arranged between a memory cell array and a word line drive circuit array. It has a feature.

[0015]

According to the semiconductor memory device having the above structure, since the memory cell array and the word line drive circuit array are separated from each other by the word line noise killer circuit array, noise interference between the memory cell array and the word line drive circuit array occurs. Suppressed. Therefore, the semiconductor memory device does not malfunction.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. In this explanation, the same reference numerals are given to the same portions throughout the drawings, and duplicate explanations will be avoided.

The present invention is also applicable to various semiconductor memory devices such as dynamic RAM and static RA.
M, rewritable ROM (EPROM), mask RO
Although it can be used for M and the like, the present invention has a configuration particularly suitable for a dynamic RAM, and therefore, the dynamic RAM will be described below as an example.

FIG. 1 is a block diagram of a VPP generation circuit, a level conversion circuit, a word line selection circuit, and a memory cell array included in the dynamic RAM according to the first embodiment of the present invention.

As shown in FIG. 1, a plurality of word lines WL0
The memory cells 10 and the word line selection circuits 16-0 to 16-n are connected to WLn, respectively. Each of the word line selection circuits 16-0 to 16-n has a ground potential VSS.
And a row decoder (hereinafter referred to as a VPP row decoder) 13 to which VPP, which is a boosted potential, is supplied as a power source.
(13-0 to 13-n), boosted potential supply circuit (hereinafter, VPP
It includes a supply circuit 12 (12-0 to 12-n) and a word line drive circuit 11 (11-0 to 11-n).

Further, each of the word line drive circuits 11-0 to 11-n has a P-channel MOSFET (hereinafter referred to as a PMOSF).
23) (referred to as ET) (23-0 to 23-n). P
The drains of the MOSs 23-0 to 23-n are word lines WL0 to WL0.
Each of them is connected to WLn. PMOS 23-0 ~ 2
The boosted potential VPP is supplied to the source of 3-n via the VPP supply circuits 12-0 to 12-n. Boosted potential VPP
Is a boosted potential higher than the power supply voltage VCC given from the external terminal. Boosted potential VPP is generated by VPP generating circuit 14 provided inside the chip.

Further, the VPP supply circuits 12-0 to 12-n respectively supply the boosted potential V to the sources of the PMOSs 23-0 to 23-n.
It is for supplying PP, and may be, for example, simple wiring. When the VPP supply circuits 12-0 to 12-n are wirings, the boosted potential VPP is always supplied to the sources of the PMOSs 23-0 to 23-n.

Further, the VPP supply circuits 12-0 to 12-n are
It may include a switching transistor. VP
When the P supply circuits 12-0 to 12-n include switching transistors, if the output of the partial decoder is connected to the gate of the switching transistor, the switching transistor turns on only when selected by the partial decoder. PMOS 23-0 connected to it
VPP will be supplied to the ~ 23-n sources.

The gates of the PMOSs 23-0 to 23-n are controlled by signals corresponding to the output signals of the VPP system row decoders 13-0 to 13-n, respectively. Here, the signals corresponding to the output signals are the row decoders 13-0 to 13-n and the PMO.
This is because a circuit element such as an inverter may exist between the gates of S23-0 to 23-n. The VPP system row decoders 13-0 to 13-n are controlled by control signals such as precharge signals and address signals.

In the present invention, some of the control signals are VPP system control signals (H level is VPP level).
Is important. Then, this VPP system control signal is supplied to the VCC system control signal (H
This is a signal whose level is converted to the VCC level.

In the dynamic RAM shown in FIG. 1, a certain VCC system control signal is supplied to the VP by the level conversion circuit 15.
The level is converted into a P system control signal. The converted signal is commonly input to the plurality of VPP row decoders 13-0 to 13-n. Therefore, unlike the circuits shown in FIGS. 21 and 22, it is not necessary to provide the level conversion circuit 15 for each word line selection circuit 16, and one level conversion circuit 15 is provided for a plurality of word line selection circuits 16. Can be provided. Therefore, the number of level conversion circuits 15 is reduced, the chip area can be reduced, and the power consumption can be further reduced.

Further, in the dynamic RAM shown in FIG. 1, unlike the dynamic RAMs shown in FIGS. 21 and 22, the level conversion circuit 15 includes the word line selection circuits 16 respectively.
Not provided for each. Therefore, the circuit 15 can be arranged away from the memory cell array that generates noise, and the level conversion circuit 15 can be prevented from being affected by the noise generated from the memory cell array. As the memory integration density increases, the memory cell array generates more noise. Especially 64 megabits or 25
With a large-capacity dynamic RAM of 6 megabits or more,
The noise generated in the memory cell array becomes relatively larger than that in the small-capacity dynamic RAM. However, since the level conversion circuit 15 is away from the memory cell array, malfunction of the circuit 15 is suppressed. Since the malfunction of the circuit 15 is suppressed, the dynamic RAM can operate stably.

On the other hand, in the dynamic RAM shown in FIGS. 21 and 22, since the level conversion circuit 15 is provided for each word line selection circuit 16, the circuit 15 is provided near the memory cell array which generates noise. Must be placed in. Therefore, 64 megabits, or 2
In a large-capacity dynamic RAM of 56 megabits or more, the circuit 15 is highly likely to malfunction and cannot operate stably.

However, in the dynamic RAM shown in FIG. 1, if the level conversion circuit 15 and the word line selection circuit 16 are too far apart from each other, the influence of noise is less likely, but the length of the wiring connecting them becomes long. Therefore, the parasitic capacitance of the connection wiring becomes large, and there is a drawback that the circuit operation is delayed. Therefore, regarding the arrangement of the circuit portion on the chip layout, a region (memory cell array) in which memory cells are formed is arranged adjacent to one side of the region in which the word line selection circuit 16 is formed on the semiconductor substrate. Is to make the wiring length of the word line as short as possible in order to prevent the parasitic capacitance of the word line from increasing, and the other side (preferably opposite to the region where the memory cell is formed) It is desirable that the region in which the level conversion circuit 15 is formed is arranged adjacent to the word line selection circuit 16 in the direction (1). For example, an area where the word line selection circuit 16 is formed is arranged between the area where the level conversion circuit 15 is formed and the area where the memory cell is formed. With such a configuration, the level conversion circuit 15 is separated from the memory cell array by the area in which the word line selection circuit 16 is formed, and the influence of noise generated in the memory cell array can be sufficiently prevented. In addition, since it is possible to prevent the wiring length of the wiring that connects the level conversion circuit 15 and the word line selection circuit 16 from increasing, the wiring delay hardly becomes a problem. Furthermore, it is also effective in that the chip size can be reduced.

In the first embodiment, the boosted control signal is used for controlling the row decoder 13. However, the word line selection circuit in an actual product has various functions other than the row decoder. Since there are circuit parts that have (for example, circuits related to redundancy), boosted control signals may be used for those parts as well. Therefore, the present invention is not limited to the control signal for controlling the row decoder as in the above embodiment, and is applied to many signals for controlling the word line selection circuit within the scope of achieving the purpose and effect. It is possible.

Next, the VPP generating circuit, the level converting circuit, which the dynamic RAM according to the first embodiment comprises,
A specific circuit configuration of the word line selection circuit and the memory cell will be described.

FIG. 2 is a specific circuit diagram of the word line selection circuit shown in FIG. 1, FIG. 3 is a specific circuit diagram of the level conversion circuit shown in FIG. 1, and FIG. 4 is a VPP generation shown in FIG. It is a circuit diagram of a circuit.

First, as shown in FIG. 2, a memory cell 10 is connected to each of the plurality of word lines WL0 to WLn. The memory cell 10 has one transistor 2
Dynamic type RA including one and one cabastor 22
It is an M cell. The word line WL is the PMOSFET 23.
(23-0 to 23-n) and NMOSFET 24 (24-0 to 2
4-n) and a word line drive circuit 11 (11-0 to 11-
connected to n). The drain of the PMOSFET 23 is connected to the drain of the NMOSFET 24, and the boosted potential VPP is supplied to the source thereof. NMOS FE
The ground potential VSS is supplied to the source of T24. In this embodiment, the VPP supply circuit 12 (12-0 shown in FIG. 1 is used.
.About.12-n) corresponds to the wiring connecting the source of the PMOSFET 23 and the boosted potential VPP. PMOSFET2
3 and the gate of the NMOSFET 24 are commonly connected to each other, and this common connection point is connected to the output node a of the VPP row decoder 13 (13-0 to 13-n). This VPP system row decoder 13 has a boosted potential VP.
PMO for precharge between P and ground potential VSS
It includes a configuration in which the SFETs 26 (26-0 to 26-n) and the decoding circuit unit 29 (29-0 to 29-n) composed of NAND gates are connected in series. VPP system row decoder 1
Reference numeral 3 is controlled by address signals A0 to Ak and / A0 to / Ak (the leading / is a "bar" indicating an inverted signal) and a precharge signal PRCH '. The precharge signal PRCH 'is a VPP system control signal, and the VCC system control signal PRCH is converted into the level conversion circuit 15 shown in FIG.
Is a signal whose level has been converted by. The output node a of the VPP system row decoder 13 has a noise killer circuit 17 (17-0) for preventing fluctuation of the potential level of the output node a.
~ 17-n) are connected. Noise killer circuit 17
Is a load PMOSFET 28 whose source is supplied with the boosted potential VPP and whose drain is connected to the output node a.
(28-0 to 28-n) and boosted potential VPP are used as power sources, and P
An inverter 30 (30-0 to 3) that supplies the gate of the MOSFET 28 with an inverted level of the potential level of the output node a
0-n) and.

FIG. 4 is a specific circuit diagram of a boosted potential generating circuit for generating boosted potential VPP. As shown in FIG. 4, the boosted potential generation circuit 14 includes the clock signal generation circuit 3
0, a means for generating complementary first and second clock signals CP1, CP2 by the inverter 31, a first boosting capacitor 32 to which the first clock signal CP1 is supplied to one end, and a power supply voltage VCC Is connected to the first boosting capacitor 32 and a gate to which the second clock signal CP2 is supplied.
It is connected between the ET 33, a terminal to which the power supply voltage VCC is supplied, and the second boosting capacitor 35, and has a first gate connected to the ET 33.
Second MOSFET to which the clock signal CP1 of
34, a drain and a gate of which are commonly connected to a node of the first MOSFET 33 and the boosting capacitor 32, and a source of which is connected to the boosted potential output terminal 38.
24, a drain and a gate are commonly connected to a connection node between the second MOSFET 34 and the second boosting capacitor 35, and a source is connected to the boosted potential output terminal 38.
And the OSFET 27.

Such a boosted potential generating circuit 15 has a DR
It is generally used for driving a word line such as AM, and a boosted potential VPP generated by this circuit is supplied to a word line selection circuit 16 via a power supply line.

Next, the operation of the circuit having the configuration shown in FIG. 2 will be described. Row address signals A0-Ak, / A0-
Before inputting / Ak to the NAND gate 29, the precharge signal PRCH ', which is a VPP system control signal, is set to a high level, a low level, or a low level within a predetermined period as a precharge operation.
High to low (ie VPP level, VSS level,
VPP level). PMOSFET 26
Turns on when the signal PRCH 'is at the VSS level, and turns off after charging the output node a to the VPP level.

The load PMOSFET 28 is a PMOS
It is provided to prevent the potential level of the output node a from fluctuating due to noise or the like when the FET 26 is turned off and the output node a temporarily becomes a floating state. Here, the inverter 30 having the output terminal connected to the gate of the PMOSFET 28 has the boosted potential VPP.
And the PMO connected in series with the ground potential VSS.
Includes SFET and NMOSFET. Inverter 30
However, the reason why the boosted potential VPP is used for the power supply is as follows. When the potential VCC is used as the power supply instead of the boosted potential VPP, the PMOSFET forming the inverter is not completely turned off when the output node a is at the H level. For this reason, the operation of the inverter becomes unstable, which prevents the speeding up of the word line.

After the lapse of the predetermined period as the precharge operation, the address signals A0 to Ak, / A0 to / Ak
Is input to the NAND gate 29.
Considering the word line selection circuit 16 connected to the selected word line WL, only the output node a corresponding to the selected word line becomes the VSS level, and the PMOS FE
T23 turns on and NMOSFET 24 turns off. As a result, the selected word line WL becomes VPP level,
The transistor 21 of the memory cell 10 connected to the word line WL is turned on, and the data stored in the capacitor 22 is transferred to the bit line BL. In this case, for the word line WL which is not selected, the output node a in the word line selection circuit 16 corresponding to the word line WL remains at the VPP level. Therefore, since the PMOSFET 23 is turned off and the NMOSFET 24 is turned on, the potential of the VPP level is not supplied to the unselected word line WL, so that the data is not read from the memory cell 10.

Here, the NMOSFET 24 is turned on when the word line WL is not selected, and the potential of the word line WL is set to 0.
It is provided to fix the level to the level, thereby preventing the word line WL from entering the floating state. This is effective in preventing the potential of the word line WL from changing due to the influence of noise and the unselected word line WL from being selected.

In this embodiment, of the signals controlling the VPP row decoder 13, the PMOSFET 26 is included.
Control signal PR for precharge supplied to the gate of
Only the CH is level-converted and the VPP control signal PR
CH '. NM configuring the NAND gate 29
The address control signals A0 to Ak and / A0 to / Ak supplied to the gates of the OSFETs remain the VCC system control signals. This means that the control signal for controlling the PMOSFET must be a VPP system control signal.
This is because the control signal for controlling the MOSFET does not necessarily need to supply the VPP system control signal. That is, when the PMOSFET is controlled by the control signal of the VCC system, the transistor is not completely turned off when the control signal is at the H level (VCC level).
In the OSFET, the VCC system control signal is at the L level (VS
This is because the transistor is completely turned off at the (S level), so that no inconvenience occurs in the circuit operation. In addition, NMOSF
Even if the ET control signal is a VPP system control signal, there is no problem in circuit operation.

For the above reasons, the word line selection circuit 16
There is no problem in circuit operation even if all the control signals for controlling the VPP system are control signals, but at least the PMOSF
The control signal supplied to ET needs to be a VPP system control signal. In this embodiment, the PMOSFET 26 is used as the precharge transistor. The use of PMOSFET for the transistor for precharging is effective because it has the effect of preventing threshold drop compared to the case of using NMOSFET.

In the first embodiment, one or more of the signals controlling the word line selection circuit 16 (at least the PMOS) are used.
It is important to use a VPP-based control signal as a signal for controlling the FET). The method of generating the VPP control signal does not matter.

Further, in the first embodiment, the control signal PRCH, which is a precharge signal, is changed to the VPP system control signal PR.
One level conversion circuit 27 is used for level conversion into CH '.

As described above, in the first embodiment, it is not necessary to provide a level conversion circuit for each of the plurality of row decoders, so the number of level conversion circuits is reduced. Further, the number of level conversion circuits is reduced as compared with the memory device which inputs the address signal groups to the row decoder after level conversion.

Therefore, in the dynamic RAM, the increase of the chip area is suppressed and the consumption of the boosted potential VPP is reduced. Further, in a memory device that level-converts the address signal groups, it takes time until the address signal groups are input to the row decoder, and especially speeding up of the word line selection operation is hindered, but the precharge signal is level-converted. In the first embodiment having the structure, the speeding up of the word line selecting operation is not hindered. The precharge signal is
This is because the row decoder is only precharged and the precharge is released.

Further, if the memory cell array and the level conversion circuit are arranged apart from each other, the dynamic RAM is less likely to malfunction. Further, in the first embodiment, the power supplies supplied to the word line selection circuit are the boosted potential VPP and the ground potential VSS, and the potential VCC is not required. That is, the power supply lines routed to the circuit area where the word line selection circuit is formed on the chip are VSS line and VPP line.
No need for two power supply lines, no VCC line. Therefore, one power supply line (VSS line and VPP line)
The width can be designed to be thick enough. If the width of the power supply line is increased, it is possible to prevent the potential level of the power supply line from changing due to noise or the like. There is also an advantage that the circuit design becomes easy.

Further, in the first embodiment, the output node a of the VPP row decoder 13 is directly connected to the gates of the PMOSFET 23 and the NMOSFET 24 in the word line drive circuit, but a plurality of VPP inverters are provided. As a matter of course, they may be indirectly connected with each other, and this point is the same in the following embodiments.

FIG. 5 is a circuit diagram showing a modification of the word line selection circuit described with reference to FIG. The word line selection circuit according to the modification shown in FIG. 5 is different from the word line selection circuit shown in FIG. 2 in the row decoder 13 (13).
-0) is not directly connected to the gate of the PMOSFET 23 of the word line drive circuit 11 (only 11-0 is shown), and the row decoder 13 and the word line drive circuit 1 are not connected.
1 and the VPP inverter 18 (only 18-0 is shown) and the VPP inverter 19 (only 19-0 is shown). Inverter 1
Reference numerals 8 and 19 are provided to control the timing of controlling the PMOSFET 23.

The output node a of the row decoder 13
And the gate of the PMOSFET 23 of the word line drive circuit 11 are connected via the inverters 18 and 19, the waveforms of the output signals of the row decoder 13 can be adjusted by the inverters 18 and 19. Therefore, a signal whose "H" level and "L" level are clearly distinguished is
It is input to the gate of the PMOSFET 23 of the word line drive circuit 11, which is useful for speeding up the operation and preventing malfunction due to erroneous detection of the signal level.

As shown in FIG. 2, the row decoder 13 and the word line drive circuit 11 are not only directly connected to each other, but also indirectly connected via an inverter or the like as shown in FIG. It may be. In short, the PMOSFET 23 and the NMOSFET 24 for driving the word line may be controlled according to the potential level of the output node a of the row decoder 13.

Next explained is a dynamic RAM according to the second embodiment of the invention. FIG. 6 is a block diagram of a VPP generation circuit, a level conversion circuit, a word line selection circuit, and a memory cell array included in the dynamic RAM according to the second embodiment of the present invention.

In particular, as shown in FIG. 1, in the dynamic RAM according to the first embodiment, the word line drive circuit 11
The VPP supply circuits 12-0 to 12-n are provided for each of -0 to 11-n. As shown in FIG.
The supply circuit 12 is connected to a plurality of word line drive circuits 11-0 to 11
You may share it with -n.

In the dynamic RAMs according to the first and second embodiments, one level conversion circuit is used to convert the level of the precharge signal, but a plurality of levels that operate exactly the same. The conversion circuits may be provided in parallel. The reason why a plurality of circuits that operate in exactly the same manner are provided for one control signal is because, for example, the parasitic capacitance of the wiring length and the driving capability of the level conversion circuit are taken into consideration. For example, when the memory cell is divided into some blocks, a plurality of level conversion circuits may be provided in parallel for each block or for some blocks. This also applies to the plurality of embodiments described below.

Next explained is a dynamic RAM according to the third embodiment of the invention. FIG. 7 is a block diagram of a level conversion circuit, a word line selection circuit and a VPP supply circuit included in the dynamic RAM according to the third embodiment of the present invention.

The dynamic RAM according to the third embodiment shown in FIG. 7 relates to a partial decoding dynamic RAM. The partial decoding method has advantages such as low voltage operation because the number of transistors connected in series between power supply potentials can be reduced.
Due to these advantages, the partial decoding method is suitable for large-capacity dynamic RAM.

Dynamic RAM according to the third embodiment
However, the difference from the dynamic RAM according to the first embodiment shown in FIG. 1 or the dynamic RAM according to the second embodiment shown in FIG. 6 is that the VPP supply circuit 12 has a decoding function. (Generally referred to as partial decoding. Sometimes also referred to as predecode).

Dynamic RAM according to the third embodiment
The VPP supply circuit included in the
It is shown in FIG. 7 as (40a-40d). A plurality of partial decoders 40 are provided. In the embodiment shown in FIG. 7, four partial decoders 40a-40d are provided.
Is provided. Four partial decoders 40a-
A signal obtained by converting the second control signal of the VCC level to the VPP level by the second level conversion circuit 15-2 is supplied to 40d. Four partial decoders 40a
To 40d output word line drive signals WDRV1 to WDRV4 at VPP level, respectively. The word line drive signals WDRV1 to WDRV4 are supplied to the word line selection circuit 16A.
(16A-0 to 16A-n). The word line selection circuit 16A is slightly modified as compared with the first and second embodiments because a plurality of partial decoders 40 are provided. Specifically, the word line drive circuit 11 is provided for each of the word line drive signals WDRV1 to WDRV4.

In the embodiment shown in FIG. 7, word line drive signals WDRV1 to WDR are provided in one word line selection circuit 16A.
Four word line drive circuits 11a to 11d are provided for each RV4. The word line drive circuit 11a has its gate connected to the output node a of the main row decoder 13,
A PMOS whose source is connected to the output node b of the partial decoder 40a and whose drain is connected to the word line WL1.
It includes the FET 23a. Similarly, the word line drive circuit 11b
Is the output node a of the main row decoder 13
A PMOSFET 23b whose source is connected to the output node b of the partial decoder 40b and whose drain is connected to the word line WL2. Similarly, the word line drive circuit 11c has its gate connected to the output node a of the main row decoder 13 and its source connected to the partial decoder 4
0c output node b connected to the drain of word line WL
3 includes a PMOSFET 23c connected to 3. Similarly, the word line drive circuit 11d includes a PMOSFET 23d having a gate connected to the output node a of the main row decoder 13, a source connected to the output node b of the partial decoder 40d, and a drain connected to the word line WL4. .

In the dynamic RAM of the partial decoding system, a plurality of word line selection circuits 16A having the above structure are provided. In the embodiment shown in FIG. 7, word line selection circuits 16A-0 to 16A-n are provided. Each of the word line selection circuits 16A-0 to 16A-n includes one main row decoder 13. Main row decoder 13-0 to 13-n
In the same manner as in the first and second embodiments, the first level conversion circuit 15-1 supplies the first control signal of the VCC level to
The signal converted to the VPP level is supplied.

When a dynamic RAM of the partial decoding system is realized by using a conventionally known technique, for example, the word line selection circuit 16A (16A-0 to 16A).
A-n) and the partial decoder 40 (40a-
It was necessary to provide a level conversion circuit inside each of 40d). Therefore, the number of circuits has increased and the number of transistors has also increased.

However, in the dynamic RAM according to the third embodiment, the level of the first control signal is converted,
The level conversion circuit 15-1 for the main row decoder, and the second
Only the level conversion circuit 15-2 for the partial decoder, which level-converts the control signal of 1), is provided, and the number of circuits is reduced. Thereby, the number of transistors is significantly reduced. Therefore, both the dynamic RAM according to the third embodiment and the dynamic RAMs according to the first and second embodiments are effective in reducing the circuit area, and the object of improving the integration density can be achieved. . Further, since the number of level conversion circuits is reduced, the consumption amount of boosted potential VPP can be reduced.

In addition to the above effects, the third embodiment has the following effects. Conventional dynamic type R
The AM includes a word line driving circuit and a word line driving NMO.
SFET and separation MOSF for suppressing backflow of carriers charged to the gate of the driving NMOSFET
Some use a bootstrap circuit consisting of ET. In this case, in order to prevent the threshold value of the driving NMOSFET from falling, first, the output of the main row decoder is determined and the gate of the driving NMOSFET is sufficiently charged, and then the output of the partial decoder (word line driving). Signal WDRV) is applied to the source of the driving NMOSFET, and the potential is coupled to couple the gate and the source of the driving NMOSFET. Due to this timing limitation, the word line drive signal WDRV
Output must be delayed, which slows down the word line selection time.

However, as in the third embodiment, the PMOS
If the FET is used as a transistor for driving the word line, it is not necessary to consider the threshold drop. Therefore, the timing limitation is eliminated. That is, it is not always necessary to give the precharge signal PRCH1 'which is the precharge signal of the main row decoder and then the PRCH2' which is the precharge signal of the partial decoder after a predetermined time has passed. It may be given to the main decoder and the partial decoder at the timing of. When the P-channel MOS transistor is used as the driving transistor in this way, in the partial decoding method, there is no limitation on the control timing of the main decoder and the partial decoder, so that there is an effect that the word line can be selected at a higher speed than before. .

Next explained is a dynamic RAM according to the fourth embodiment of the invention. The dynamic RAM according to the fourth embodiment is a more specific version of the dynamic RAM according to the third embodiment shown in FIG.

FIG. 8 is a block diagram schematically showing the structure of a dynamic RAM according to the fourth embodiment of the present invention. As shown in FIG. 8, the precharge signal generation circuit 1 generates a VCC level precharge signal PRCH used for precharge of the main row decoder and partial decoder and its cancellation. The VCC level precharge signal PRCH is supplied to the level conversion circuit 15
Then, the first precharge signal PRCH1 of VPP level
'And VPP level second precharge signal PRC
The level is converted to H2 '. The level-converted precharge signals PRCH1 ′ and PRCH2 ′ may be directly input to the main row decoder and the partial decoder, but are input to the main row decoder and the partial decoder after passing through a buffer circuit including an inverter circuit. May be. This is the precharge signal PRC
When the timings of H1 'and PRCH2' are shifted, or the precharge signals PRCH1 'and PRCH1'
This is performed as necessary, such as when changing the current drive capacities of CH2 '.

Eight main row decoders 13 are provided. Each of the eight main row decoders 13-0 to 13-7 has a level-converted first precharge signal P.
RCH1 'is commonly input. Main row decoder 1
The number of row address signals input to 3-0 to 13-7 is "A
There are 6 rows address signals, 3 "," A4 "," A5 "," / A3 "," / A4 "and" / A5 ". Eight combinations of signals can be obtained from the 6 row address signals. Each of the eight combinations of signals is a main row decoder 13
It is input to -0 to 13-7.

Eight word line selection circuits 16A are provided. Each of the eight word line selection circuits 16A-0 to 16A-7 has one main row decoder 13, an output wiring a connected to the output of the main row decoder 13, and four output wirings a connected to the output wiring a. Divided output wirings aa to ad,
It includes word line drive circuits 11a to 11d provided one for each of the divided output wirings aa to ad, and word line noise killer circuits 41a to 41d provided for each of the four word lines WL.

A word line drive signal line selection circuit 39 including a partial decoder 40 is also provided. In this embodiment, four word line drive signal line selection circuits 39a ...
39d is provided. Partial decoder 40a-
A level-converted second precharge signal PRCH2 ′ is commonly input to each of 40d. The row address signals input to the partial decoders 40a to 40d are "A0", "A1", "/ A0" and "/ A1".
Is 4 in total. Four combinations of signals can be obtained from the four row address signals. Each of the four combinations of signals is input to the partial decoders 40a to 40d.

In this embodiment, the number of row address signals input to the partial decoder is four, but if the number of row address signals is six, eight combinations of signals can be obtained.
At this time, eight partial decoders 40 are provided,
The number of divided output wirings provided in the word line selection circuit 16A is also changed from 4 to 8.

A pair of word line drive signal lines are connected to the word line drive signal line selection circuit 39a. A pair of wires
One of the word line drive signal lines, the word line drive signal WDR
The word line drive circuits 11a-0 to 11a are provided at the intersections of V and the divided output wirings aa of the main row decoders 13-0 to 13-7.
-7 is provided. Another word line drive circuit 11b (1
1b-0 to 11b-7) to 11d (11d-0 to 11d-7) are word line drive circuits 11 as shown in FIG.
It has the same configuration as a. Further, of the pair of word line drive signal lines, the other inversion word line drive signal line / WDRV
And word line noise killer circuits 41a-0 to 41 at the intersections of the output lines of the main row decoders 13-0 to 13-7.
a-7 is provided. Other word line noise killer circuits 41b (41b-0 to 41b-7) to 41d (41d-0 to 4)
1d-7) has the same configuration as that of the word line noise killer circuit 41a, as shown in FIG.

FIG. 9 is a circuit diagram of the word line selection circuit shown in FIG. As shown in FIG. 9, the word line selection circuit 16
The circuit of A-0 is almost the same as the circuit shown in FIG. The most different point is that one output wiring a is connected to four divided output wirings aa to ad. The word line drive circuits 11a-0 to 11d-0 are also almost the same as the circuit shown in FIG. However, PMOSFETs 23a-0 to 23
The source of d-0 is the word line drive signal W of VPP level.
DRV1 to WDRV4 are supplied.
Power is supplied to the word line drive circuits 11a-0 to 11d-0 by supplying the word line drive signals WDRV1 to WDRV4. The outputs of the word line drive circuits 11a-0 to 11d-0 are connected to the word lines WL1 to WL4. Word line W
The word line noise killer circuit 41a-0 is connected to L1 to WL4.
~ 41d-0 are connected. Each of the word line noise killer circuits 41a-0 to 41d-0 has a source connected to the low potential power supply line VSS and a drain connected to the word lines WL1 to WL4.
And NMOSFETs 42a-0 to 42d-0 connected to.
The inverted word line drive signals / WDRV1 to / WDRV4 are input to the gates of the NMOSFETs 42a-0 to 42d-0. The NMOSFETs 42a-0 to 42d-0 are turned on when the inverted word line drive signals / WDRV1 to / WDRV4 are at the "H" level, and the potentials of the word lines WL1 to WL4 are set to V.
Set to SS level. Word line noise killer circuit 41a-0
Output of main row decoder and word line drive signal WDR even when ~ 41d-0 is not connected to word line
When both V are at "L" level, the potential of the word line WL becomes "L" level. However, the potential of the word line actually fluctuates between 0 V and the threshold Vth due to the influence of noise and the like. Therefore, malfunction may occur. Therefore, inverted word line drive signals / WDRV1 to / W
DRV4 is at "H" level, that is, word line drive signal WDR
NM that turns on when V1 to WDRV4 are at "L" level
By providing the word line noise killer circuits 41a-0 to 41d-0 including the OSFETs 42a-0 to 42d-0, the potential of the word line WL can be fixed at the VSS level and fluctuation of the potential of the word line can be suppressed. To be done. In addition, the inverted word line drive signals / WDRV1 to / WDRV4 are the same as the drive word line drive signals WDRV1 to WDRV4.
Although it may be level, in the fourth embodiment, VCC
It is a level.

Although not particularly shown, the other word line selection circuits 16A-1 to 16A-7 are circuits similar to the word line selection circuit 16A-0 shown in FIG. FIG. 10 is a circuit diagram of the word line drive signal line selection circuit shown in FIG.

As shown in FIG. 10, the word line drive line signal line selection circuit 39a includes a partial decoder 40a. The partial decoder 40a has the same configuration as the main row decoder 13-0 shown in FIG. The output wiring c of the partial decoder 40a is connected to the word line driving signal line driving circuit 43a. In addition, the output wiring c
A noise killer circuit 44a having the same configuration as the noise killer circuit 17-0 shown in FIG. 2 is connected.

The drive signal line drive circuit 43a has a source connected to the boosted potential power supply line VPP, a drain connected to the output wiring b, and a gate connected to the output wiring c.
45a and an NMOSFET 46a in which the source is connected to the low potential power supply line VSS, the drain is connected to the output wiring b, and the gate is connected to the output wiring c. The drive signal WDRV1 is extracted from the output wiring b.

A killer drive circuit 47a for driving the word line noise killer circuit is connected to the output wiring b.
The killer drive circuit 47a includes an inverter to generate an inverted signal / WDRV1 of the drive signal WDRV1. The killer drive circuit 47a includes a PMOSFET 48a having a source connected to the high potential power supply line VCC, a drain connected to the output wiring d, and a gate connected to the output wiring b, and a source connected to the low potential power supply line VSS. , The drain of which is connected to the output wiring d, and the gate of which is connected to the output wiring b.
a is included. Inverted drive signal / WDR from output wiring d
V1 is extracted. Killer drive circuit 47a may include an inverter supplied with boosted potential VPP as a power supply, or may include an inverter supplied with high potential VCC as a power supply, as shown in FIG.

When the killer drive circuit 47a includes an inverter supplied with the boosted potential VPP as a power source,
Since the potential of the word line can be brought to the VSS level faster, the speed can be increased, and the VCC line is not required.

On the other hand, the high potential VC is applied to the killer drive circuit 47a.
When an inverter supplied with C as a power source is included, it is possible to reduce consumption of boosted potential VPP.

In the large-capacity storage device, the boosted potential VP
The advantage is that the consumption of P can be reduced.
If the consumption of the boosted potential VPP can be reduced, the boosted potential V
This is because there is an effect such that the potential variation of PP and the area of the boosting capacitor can be reduced.

Although not particularly shown, the other word line drive line signal line selection circuits 39b to 39d are circuits similar to the word line selection circuit 16A-0 shown in FIG. In addition, the word line drive line signal line selection circuits 39a to 39d are similar to those shown in FIG.
In addition to the circuit shown in FIG. 5, the circuit shown in FIG.

Dynamic RAM according to the fourth embodiment
Then, the precharge signal PRCH is level-converted, and the level-converted precharge signals PRCH1 ', PRCH
Since 2'is input to the main row decoder and the partial row decoder, the number of level conversion circuits can be reduced. The number of transistors is reduced in order to reduce the number of level conversion circuits. Further, since the number of level conversion circuits can be reduced, the consumption amount of boosted potential VPP is reduced.

Further, a precharge signal PRCH1 'for precharging the main row decoder and a precharge signal PRCH for precharging the partial decoder.
The number of level conversion circuits can be further reduced because each 2'is created using one level conversion circuit.

Further, since the inverted drive signal / WDRV is generated by using the inverter which uses the high potential VCC as a power source, the consumption amount of the boosted potential VPP can be further reduced. Next, the chip layout of the dynamic RAM according to the fourth embodiment will be described. The chip layout described below is a new and useful chip layout that can achieve high integration density, excellent workability, suppression of noise interference between circuits, and the like.

FIG. 11 is a diagram showing a chip layout of a dynamic RAM according to the fourth embodiment. Figure 11
As shown in, there is a memory cell array 100 in which memory cells are arranged. The word line drive circuit array 101 includes PMOSFETs 23a-0 to 23a-0 included in the word line drive circuit.
23a-7, 23b-0 to 23b-7, 23c-0 to 23c-7,
23d-0 to 23d-7, NMOSFET 24a-0 to 24a
-7, 24b-0 to 24b-7, 24c-0 to 24c-7, 24d
-0 to 24d-7 are placed. A word line noise killer circuit array 102 is arranged between the memory cell array 100 and the word line drive circuit array 101. The word line noise killer circuit array 102 includes NMOSFETs 42a-0 to 42a-7 included in the word line noise killer circuit,
42a-0 ~ 42a-7, 42a-0 ~ 42a-7, 42a-0 ~
42a-7 is arranged.

Word line drive signal line drive circuit array 103
Are arranged adjacent to the word line drive circuit array 101. In this layout, the word line drive signal drive circuit array 103 has two drive signal line drive circuit arrays 1
03-1 and the drive signal line drive circuit array 103-2. The word line drive circuit array 101 includes the array 10
It is arranged between 3-1 and the array 103-2. The drive signal line drive circuit array 103-1 includes PMOSFETs 45a, 45c and NMOSFET 45 included in the drive signal line drive circuit.
a and 45c are arranged. On the other hand, the drive signal line drive circuit array 103-2 includes a PMOS included in the drive signal line drive circuit.
FET 45b, 45d, NMOSFET 45b, 45d
Are placed.

The killer drive circuit array 104 is arranged adjacent to the word line noise killer circuit array 102. In this layout, the killer drive circuit array 104
Is divided into two killer drive circuit array 104-1 and drive signal line drive circuit array 104-2. The word line noise killer circuit array 102 is arranged between the array 104-1 and the array 104-2. The killer drive circuit array 104-1 includes a PMOSFET 4 included in the killer drive circuit.
8a, 48c and NMOSFETs 49a, 49c are arranged. On the other hand, the killer drive circuit array 104-2 includes PMOSFETs 48b, 48d, NMs included in the killer drive circuit.
OSFETs 49b and 49d are arranged.

FIG. 12 is a diagram showing in detail the word line drive circuit array 101 and the word line noise killer circuit array 102 in the chip layout shown in FIG. 11, and FIG. Of the chip layout shown in FIG. 1, the word line drive signal drive circuit array 103-1,
FIG. 13B (b) is a diagram showing the killer drive circuit array 104-1 in detail, showing the drive signal drive circuit array 103-2 and the killer drive circuit array 104-2 in the chip layout shown in FIG. It is the figure which showed the part in detail.

As shown in FIG. 12, NMOSFETs 42a-0 to 42a-7, 42 included in the word line noise killer circuit.
b-0 ~ 42b-7, 42c-0 ~ 42c-7, 42d-0 ~ 42
d-7 is a PMOSFET 23a included in the word line drive circuit
-0 ~ 23a-7, 23b-0 ~ 23b-7, 23c-0 ~ 23c
-7, 23d-0 to 23d-7, NMOSFET 24a-0 to 2
4a-7, 24b-0 to 24b-7, 24c-0 to 24c-7, 2
They are arranged 90 ° apart from 4d-0 to 24d-7.
In FIG. 12, the direction of the current flowing through each MOSFET is indicated by an arrow. The direction of this arrow points to the gate length direction at the same time as the direction of the electric current.

As shown in FIGS. 13A and 13B, the PMO included in the word line drive signal line drive circuit is included.
SFET 45a-45d, NMOSFET 46a-46
d is an NMOSFET included in the word line noise killer circuit
42a-0 ~ 42a-7, 42b-0 ~ 42b-7, 42c-0 ~
42c-7 and 42d-0 to 42d-7 are arranged in the same direction. Similarly, the PMOS FE included in the killer drive circuit
T48a-48d, NMOSFET 49a-49d,
NMOSFET 42a included in the word line noise killer circuit
-0 ~ 42a-7, 42b-0 ~ 42b-7, 42c-0 ~ 42c
-7, 42d-0 to 42d-7 are arranged in the same direction. In FIG. 13A and FIG. 13B, the direction of the current flowing through each MOSFET is shown by an arrow, as in FIG. The direction of this arrow points to the gate length direction at the same time as the direction of the electric current.

In the chip layout shown in FIG. 11, by disposing the word line noise killer circuit array between the memory cell array and the word line drive circuit array, the memory cell array and the word line drive circuit array are separated from each other. You can Therefore, noise interference is suppressed between the memory cell array and the word line drive circuit array. By suppressing the noise interference, it is possible to further reduce the possibility that the storage device malfunctions.

Further, FIG. 12, FIG. 13 (a) and FIG.
As shown in FIG. 3B, the NMOSFET included in the word line noise killer circuit and the PMO included in the word line drive circuit.
By arranging the SFET and the NMOSFET so as to be shifted by 90 degrees, the area of the word line noise killer circuit array does not increase unnecessarily. That is, it has a high integration density. Further, the word line pattern can be a pattern that only crosses over the word line noise killer circuit array from the word line drive circuit to the memory cell array. That is, the word lines can be made into a linear pattern.
A linear pattern can withstand fine processing, as compared to a pattern that bends repeatedly. That is, it has excellent workability. The pattern after forming the word line is shown in FIG.

FIG. 15 is a pattern plan view of the memory cell array. As shown in FIG. 15, the memory cell array 1
In 00, a memory cell 200 including one transfer transistor and one capacitor is integrated.
The transfer transistor is arranged 90 degrees apart from the NMOSFET included in the word line noise killer circuit. The memory cell 200 is a buried plate trench cell (hereinafter referred to as a BPT cell) having a high integration density. A cross-sectional view of the BPT cell 200 is shown in FIG.

As shown in FIG. 15, the capacitor 201 of the BPT cell 200 has a plate potential V from the N-type silicon layer 202 formed inside the P-type silicon substrate.
PL is given. The N-type silicon layer 202 is formed by N-type impurities diffused from the bottom of the trench 203. Since the N-type silicon layer 202 is embedded in the substrate, it is also called a buried wiring layer.

Further, the chip layout shown in FIG. 11 can further obtain the following effects when the BPT cells 200 are integrated in the memory cell array. FIG. 17 is a schematic sectional view of a word line drive circuit array, a word line noise killer circuit array, and a memory cell array.

As shown in FIG. 17, the BPT cell 200
Has an N-type embedded wiring layer 202. The N-type buried wiring layer 202 has a plate potential VPL (normally, a power supply potential VC).
About 1/2 of C) is supplied. Further, the word line drive circuit array has an N-type well as a region for forming a PMOSFET. The N-type well has a boosted potential VPP.
Is supplied. If the N-type well to which the boosted potential VPP is supplied is arranged near the N-type buried wiring layer 202, the N-type buried wiring layer 2 is formed by the potential of the N-type well.
The potential of 02 changes.

However, as shown in FIG. 17, a word line noise killer circuit 102 is arranged between the memory cell array 100 and the word line drive circuit 101. The word line noise killer circuit 102 separates the N-type well to which the boosted potential VPP is supplied from the N-type buried wiring layer 202 from each other. Therefore, the fluctuation of the potential of the N-type embedded wiring layer 202 can be suppressed.

FIG. 18 is a diagram showing a chip layout of a block of the dynamic RAM according to the fourth embodiment shown in FIG. As shown in FIG. 18, the main row decoder array 105 in which the main row decoders are arranged is
It is provided adjacent to the word line drive circuit array 101.
Further, the partial decoder array 106 in which the partial decoder is arranged is divided into two arrays 106-1 and 106-2. The array 106-1 is provided adjacent to the word line drive signal line drive circuit array 103-1. On the other hand, the array 106-2 is provided adjacent to the word line drive signal line drive circuit array 103-2. The level conversion circuit area 107 in which the level conversion circuit is arranged is provided adjacent to the main row decoder array 105.

Further, the capacitor region 108 in which the boosting capacitor is arranged is formed in the main row decoder array 10.
It is provided adjacent to 5. The booster circuit region 109 in which the booster circuit is arranged is provided adjacent to the capacitor region 108.

In the chip layout shown in FIG. 18, the main row decoder array 105, the partial decoder array 106-2, the word line drive circuit array 101,
A word line noise killer circuit array 102 is provided.
Therefore, noise interference between the level conversion circuit and the memory cell array can be suppressed.

Further, since level conversion circuit region 107 is provided adjacent to main row decoder array 105, the distance from the level conversion circuit to the main row decoder can be shortened. For this reason, the length of the wiring connecting the level conversion circuit and the main row decoder can be shortened, and the signal delay due to the wiring becomes almost no problem. Further, since the partial decoder arrays 106-1 and 106-2 are provided adjacent to the main row decoder array 105,
The distance from the level conversion circuit to the partial decoder is also shortened.

In an actual storage device, a plurality of memory blocks shown in FIG. 18 are integrated in one chip to realize a large storage capacity. At this time, the capacitor region 108 and the booster circuit region 109 are provided for each memory block.
And will be provided. As described above, by providing the capacitor region 108 and the booster circuit region 109 for each memory block, the boosted potential VPP with less potential fluctuation can be generated. The fluctuation of the boosted potential VPP causes a malfunction of the circuit.

FIG. 19 is a circuit diagram of a dynamic RAM according to the fifth embodiment of the present invention. The fifth embodiment is similar to the third and fourth embodiments in that the partial decoding method is used. However, if the decoder is CMO
The difference is that it is composed of an S circuit, that a precharge signal is not input, and that a noise killer circuit is not connected to the output wiring of the row decoder.

As shown in FIG. 19, the PMOSFET 23 and NMO for driving the word line connected to the word line WL.
The gates of the SFETs 24 are commonly connected, and are directly connected to the output wiring a of the VPP row decoder 50.
Of course, a VPP inverter for delay may be provided as described above. The row decoder 50 is a CMOS-NAND controlled by address signals A2 to A4.
It consists of a gate. Further, in the VPP supply circuit 51, CMOS-controlled by address signals A0 to A1.
It includes a partial decoder circuit portion composed of NAND gates. Both decoder circuits are supplied with VPP as a power source. These address signals A0 to A4 control the PMOSFET, but in order to completely turn off the PMOSFET when the address signal is at the H level, the address signal must be a VPP system control signal. Converted to VCC
The level of the system control signal is converted to the VPP system control signal. In this embodiment, since one level conversion circuit is used for one control signal, at least five level conversion circuits are required, but one control signal is taken into consideration in consideration of the driving capability of the level conversion circuit. It is also possible to provide a plurality of level conversion circuits. In any case, compared with the prior art, the number of level conversion circuits is much smaller, so that the chip area and power consumption can be reduced, and a dynamic RAM that is less likely to malfunction can be provided. Has the same effect. Further, in this embodiment, there is also an effect that a high speed operation is possible besides this. That is, since the decoder circuit is not an NMOSFET but a CMOS circuit, it is not necessary to input the precharge signal in advance and charge the output end of the decoder before inputting the address signal, and therefore the word line selection can be speeded up. Can be planned. Also, the output end of the decoder is VP
Since it is fixed to the P level or the VSS level and does not float, the potential level does not easily fluctuate even if the noise killer circuit is not connected to the output wiring a.

The storage device according to the fifth embodiment cannot apply the technique of converting the level of only the precharge signal. However, the memory device according to the fifth embodiment operates the killer drive circuit at VCC to reduce the consumption of VPP, and the word line noise killer circuit array 102 between the word line drive circuit array and the memory cell array. , And a technology for achieving high integration density while suppressing noise interference can be applied.

Although the NAND gate is used as the row decoder in the first to fifth embodiments, the N
An OR gate may be used. FIG. 20 is a circuit diagram of a word line selection circuit using a NOR gate 60 made of NMOSFET as a row decoder.

As shown in FIG. 20, the PMOSFET 61 included in the noise killer circuit is not directly connected to the output wiring a of the row decoder 61, but the VPP inverter 62.
It is indirectly connected via. The connection in this specification is used to mean that the connection relationship includes both direct and indirect.

[0105]

As described above, according to the present invention, it is possible to provide a semiconductor memory device which does not malfunction even if noise is generated from the memory cell array and consumes less boosted potential.

[Brief description of drawings]

FIG. 1 is a block diagram of a dynamic RAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of the word line selection circuit shown in FIG.

FIG. 3 is a circuit diagram of the level conversion circuit shown in FIG.

FIG. 4 is a circuit diagram of the VPP generating circuit shown in FIG.

FIG. 5 is a circuit diagram of a word line selection circuit according to a modification.

FIG. 6 is a block diagram of a dynamic RAM according to a second embodiment of the present invention.

FIG. 7 is a block diagram of a dynamic RAM according to a third embodiment of the present invention.

FIG. 8 is a block diagram of a dynamic RAM according to a fourth embodiment of the present invention.

9 is a circuit diagram of the word line selection circuit shown in FIG.

10 is a circuit diagram of a word line drive signal line selection circuit shown in FIG.

11 is a diagram showing a chip layout of the dynamic RAM shown in FIG.

12 is a plan view of the word line drive circuit array and the word line noise killer circuit shown in FIG.

13 is a plan view of the word line drive signal drive circuit array and the killer drive circuit array shown in FIG.
(A) is a plan view of the word line drive signal drive circuit array 103-1 and killer drive circuit array 104-1, and (b) is a word line drive signal drive circuit array 103-2 and killer drive circuit array 104-2. Plan view of.

FIG. 14 is a plan view of a pattern after forming word lines.

15 is a plan view of the memory cell array shown in FIG.

16 is a cross-sectional view of the memory cell shown in FIG.

17 is a cross-sectional view of the word line drive circuit array, word line noise killer circuit array and memory cell array shown in FIG.

18 is a diagram showing a chip layout of a block of the dynamic RAM shown in FIG.

FIG. 19 is a circuit diagram of a dynamic RAM according to a fifth embodiment of the present invention.

FIG. 20 is a circuit diagram of a word line selection circuit having a row decoder using a NOR gate.

FIG. 21 is a block diagram of a conventional word line selection circuit.

FIG. 22 is a block diagram of another conventional word line selection circuit.

[Explanation of symbols]

10 ... Memory cell, 11 ... Word line drive circuit, 12 ... V
PP supply circuit, 13 ... VPP system row decoder, 14 ... V
PP generation circuit, 15 ... Level conversion circuit, 16 ... Word line selection circuit, 17 ... Noise killer circuit, 18 ... Inverter, 19 ... Inverter, 21 ... Transfer transistor, 22 ... Capacitor, 23 ... P channel type MOSF
ET, 24 ... N-channel MOSFET, 26 ... P-channel MOSFET, 29 ... Decode circuit section, 30 ... Inverter, 39 ... Word line drive signal line selection circuit, 40 ...
Partial decoder, 41 ... Word line noise killer circuit, 43 ... Word line drive signal line drive circuit, 44 ... Noise killer circuit, 45 ... P-channel MOSFET, 46 ...
N-channel MOSFET, 47 ... Killer drive circuit, 4
8 ... P-channel MOSFET, 49 ... N-channel M
OSFET, 100 ... Memory cell array, 101 ... Word line drive circuit array, 102 ... Word line noise killer circuit array, 103 ... Word line drive signal line drive circuit array, 104 ... Killer drive circuit, 105 ... Main row decoder array, 106 ... -Shall decoder array, 10
7 ... Level conversion circuit area, 108 ... Capacitor area, 1
09 ... VPP generating circuit region, 200 ... Buried plate trench cell, 201 ... Capacitor, 202 ... N type silicon layer (buried wiring layer), 203 ... Trench.

Claims (19)

[Claims] 1. A memory cell array in which memory cells are arranged, and a P-channel insulated gate FE included in a word line drive circuit.
A word line drive circuit array in which T and N channel type insulated gate FETs are arranged, and a word line noise killer circuit array in which N channel type insulated gate FETs included in the word line noise killer circuit are arranged are provided. A semiconductor memory device, wherein the word line noise killer circuit array is provided between the memory cell array and the word line drive circuit array. 2. A boosted potential wiring drive circuit which supplies a boosted potential to a boosted potential wiring adjacent to the word line drive circuit array and drives the word line drive circuit array includes P.
2. The semiconductor memory device according to claim 1, further comprising a boosted potential wiring drive circuit array in which a channel type insulated gate type FET and an N channel type insulated gate type FET are arranged. 3. A P-channel insulated gate FET included in a killer drive circuit that drives the word line noise killer circuit by inverting the output of the boosted potential wiring drive circuit adjacent to the word line noise killer circuit array. And N
3. The semiconductor memory device according to claim 2, further comprising a killer drive circuit array in which channel type insulated gate FETs are arranged. 4. A row decoder array in which a row decoder is arranged is provided adjacent to the word line drive circuit array, and a level commonly used in the row decoder array is adjacent to the row decoder array. 4. The semiconductor memory device according to claim 3, further comprising a conversion circuit. 5. The semiconductor memory device according to claim 4, wherein a boosting capacitor is provided adjacent to the row decoder array. 6. The boosted potential wiring drive circuit array is two in number, and the word line drive circuit array is arranged between two boosted potential wiring drive circuit arrays. Semiconductor memory device. 7. The killer drive circuit array is two,
4. The semiconductor memory device according to claim 3, wherein the word line noise killer circuit array is arranged between two killer drive circuit arrays. 8. The word line noise killer circuit includes N
The gate length direction of the channel type insulated gate FET is the P channel type insulated gate type FE included in the word line drive circuit.
8. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is orthogonal to the gate length direction of the T and N channel insulated gate FETs. 9. The gate length direction of the P-channel type insulated gate FET and the N-channel type insulated gate FET included in the boosted potential wiring drive circuit is the same as the N-channel type insulated gate FET included in the word line noise killer circuit. 9. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is parallel to the gate length direction. 10. The gate length direction of the P-channel type insulated gate FET and the N-channel type insulated gate FET included in the killer drive circuit array is the gate of the N-channel type insulated gate FET included in the word line noise killer circuit. 9. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is parallel to the longitudinal direction. 11. The semiconductor memory device according to claim 1, wherein the memory cell includes one transfer transistor and one capacitor. 12. The gate length direction of an N-channel type insulated gate FET included in the word line noise killer circuit is orthogonal to the gate length direction of a transfer transistor included in the memory cell. Semiconductor memory device. 13. The plate potential is applied to the capacitor of the memory cell from a second conductivity type semiconductor layer formed inside a first conductivity type semiconductor substrate. Semiconductor memory device. 14. The semiconductor memory device according to claim 13, wherein the semiconductor layer is an N-type buried wiring layer. 15. The P-channel type insulated gate FET included in the word line drive circuit is provided in an N-type well region formed in a P-type semiconductor substrate. Semiconductor memory device. 16. The word line noise killer circuit array is provided between the N-type well region and the N-type buried wiring layer. Semiconductor memory device. 17. The P-channel insulated gate FET included in the killer drive circuit is provided in an N-type second well region formed in a P-type semiconductor substrate. The semiconductor memory device according to 1. 18. The N-type well region is connected to a wiring to which a boosted potential higher than a high potential is supplied,
-Type second well region is connected to the wiring to which the high potential is supplied, and the N-type buried wiring layer is connected to the wiring to which the potential between the high potential VCC and the low potential VCC is supplied. 18. The semiconductor memory device according to claim 17, wherein the semiconductor memory device is a memory device. 19. The semiconductor memory device according to claim 18, wherein the P-channel type insulated gate FET included in the boosted potential wiring drive circuit is provided in the N-type well region.