JPH07253997A - Layout design support device - Google Patents

Abstract

PURPOSE:To improve the wiring rate while maintaining the functions requested to a circuit with respect to the layout design support device which edits circuit wiring information before layout design. CONSTITUTION:A retrieval means 11 and an editing means 13 are provided. The means 11 subjects circuit connection information of the circuit, which should be arranged on an integrated circuit, to retrieval processing and obtains a pair of flip flops where the non-inverted data output of the preceding stage is connected to the data input of the succeeding stage directly or through a non-inverting buffer and the scan data output of the preceding stage is connected to the scan data input of the succeeding stage through the non-inverting buffer. The means 13 takes in circuit connection information and subjects the section between the non-inverted data output and the data input or that between the scan data output and the scan data input of the pair of flip flops which is obtained by the retrieval means 11, to the editing processing that data of the succeeding stage and the preceding stage are individually merged in the output end of the preceding stage and the input end of the succeeding stage respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design support device for editing circuit wiring information obtained as a result of logic design or circuit design applied to a scan path system prior to layout design.

[0002]

2. Description of the Related Art In recent years, many electronic devices are equipped with large-scale integrated circuits, and the scale of such large-scale integrated circuits is increasing in response to the demand for higher functionality and diversification of electronic devices. . Further, conventionally, as a method for surely determining the correctness of the operation of each part in the manufacturing process of such an integrated circuit, a scan path method, a level sensitive scan design, a scan set and other serial scan methods have been proposed and put to practical use. Has been done.

Among these serial scan methods, particularly the scan path method is a flip-flop with scan (hereinafter, simply referred to as "flip-flop") as all flip-flops sandwiched between sequential circuits.
By configuring the shift register and reading and writing the test bit pattern via the shift register during testing, the internal circuit is controlled and observed from outside the chip compared to other serial scan methods. It is easy to do, and the scale of the additional circuit is small, and the sequential circuit can be tested as a combinational circuit. further,
Such a scan path method is widely used because it has a high degree of freedom in setting a circuit block to be tested and can realize a homogeneous test without depending on the experience of a logic designer.

FIG. 8 is designed by applying the scan path method.
It is a figure which shows an example of the performed circuit. In the figure, the input end
Child P₁Is flip-flop 81₁Connected to input D of
The non-inverted output Q is a flip-flop 81₂To input D
Connected. Flip-flop 81₂The non-inverted output Q of
It is connected to one input of AND gate 82 and its output is
It is connected to one input of the OR gate 83. Input terminal P
₂Is the input of the inverter 84 and the other of the OR gate 83
Of the OR gate 83 is connected to the input of
(Not shown) through output terminal P₃Connected to
It Input terminal P _FourIs the non-inverting buffer 85₁Pretend through
Scan data input to the flip-flop 81 (hereinafter, simply
It is called "scan input". ) Connected to SDI
Can data output (hereinafter, simply "scan output"
U ) SDO is flip-flop 81₂Scan input
Connected to SDI. Flip-flop 81₁~ 81_Nof
The clock input CK has a predetermined clock generated inside the chip.
Lock CLK is given and flip-flop 81_NNon of
The inverted output Q is connected to a combination circuit (not shown).
It Also, the flip-flop 81_NScan output SD
O is a non-inverting buffer 85₂Output terminal P via_FiveContact
Will be continued. Input terminal P₆Is the inverter 86₁Through
Lip flop 81₁~ 81_NTest clock mode
Clock input IH for input terminal P₇Is inva
Data 86₂Through the flip-flop 81₁~ 81_Nof
Connected to clock input A. Input terminal P₈Is the Inva
Data 86₃Through the flip-flop 81₁~ 81_Nof
Connected to clock input B.

In the circuit having such a configuration, the inverter 8
The operation test based on the scan path method of the combinational circuit including the AND gate 82, the OR gate 83, and the like is performed by repeating the following two modes including the scan mode and the subsequent test clock mode.

In the scan mode, the input terminals P ₇ and P ₈
The scan clocks XACK and BCK are given from the input terminal P, and the input terminal P is synchronized with these clocks.
₄ is provided with test data consisting of serial bit strings. In such a state, the flip-flops 81 ₁ to 8 ₁
1 _N is the scan output SDO and scan input SD between stages
It operates as a shift register connected in series with I and scans out the result of the test previously loaded into these flip-flops while sequentially fetching the above-mentioned test data and giving it to the combinational circuit.

In the test clock mode, the input terminal P ₆
From the general input terminal (for example, the input terminal P ₂ ) is supplied with the test clock XTCK from
Flip-flops 81 ₁ to 8 in the scan mode described above
Each part of the combinational circuit operates based on the data scanned in to 1 _N , and the result of the operation is loaded into a flip-flop arranged in the subsequent stage of each circuit.

Therefore, desired test data is surely given to the combinational circuit from the input terminal P ₄ , and basic circuit blocks (for example, each functional block including a logic gate and a circuit of a larger scale) are provided for these combinational circuits. The operation test is performed. In addition, here
Inverter 84, AND gate 82 and OR gate 8
The operation of the combinational circuit including 3 is not related to the present application, and thus its description is omitted.

For such a circuit, the circuit connection information shown in FIG. 9 and the basic element table shown in FIG. 10 are generated as a result of the logic design and circuit design of the circuit. In the circuit connection information, the circuit shown in FIG. 8 is divided into unit connection information between the starting point indicated by the identifiers and terminal names of the elements forming the circuit and its connection destination. Further, such element identifiers are collectively given as the basic element table shown in FIG. 10, and a character string indicating the function of the element (for example, a flip-flop is indicated by “FF”, an AND gate is indicated by “A”). Shown, the OR gate is indicated by "O", and the inverter is indicated by "I") and a suffix of an identification number that physically identifies the element. In addition, in FIG. 8, such an identification number is shown in the symbol of each element.

Further, the circuit connection information and the basic element table are used to determine the shape of each basic element and the layout of the chip area, and the wiring path between these elements on the chip to determine the mask. It is referred to when designing the layout that generates the pattern.

Further, in such a layout design process, a desired circuit fits on a chip as small as possible within the allowable range of the design standard, and stray capacitance, parasitic resistance, parasitic transistor, heat generation, and physical parameters caused by the process In order to obtain desired characteristics with a high probability in consideration of variations and the like, optimization is appropriately performed.

[0012]

By the way, in the process of layout design of an LSI in which a circuit designed by applying such a scan path method is arranged, there is a need to meet the demand for higher functionality and complexity of the LSI. Circuit scale increases,
As the scale of the additional circuit required for the operation test by the scan path method increased, the placeability and wiring performance decreased significantly.

Further, due to such a reduction in the layout and wiring property, fine adjustment of the layout is required manually at the final stage of the layout design process, and the required number of steps is significantly increased. However, if the wiring rate does not increase even if the cost is increased, it is necessary to change the chip size to a large size, which may significantly increase the cost.

It is an object of the present invention to provide a layout design support device which increases the wiring rate while maintaining the function required for a circuit.

[0015]

FIG. 1 is a block diagram showing the principle of the invention described in claims 1 and 2. According to the first aspect of the present invention, the scan path method is applied to the circuit connection information of the circuit to be arranged on the integrated circuit, a search process adapted to the format of the circuit connection information is performed, and the non-inverted data output of the preceding stage is performed. Search means 11 for obtaining a pair of flip-flops connected to the data input of the latter stage directly or via the non-inverting buffer and the scan data output of the previous stage directly or via the non-inverting buffer to the scan data input of the latter stage. And, regarding the pair of flip-flops obtained by the search means 11 by taking in the circuit connection information,
Edit that merges the other section with the output end of the previous stage and the input end of the latter stage in any one of the section of non-inverted data output and data input and the section of scan data output and scan data input And an editing unit 13 for performing processing.

According to a second aspect of the present invention, the scan path method is applied to the circuit connection information of the circuit to be arranged on the integrated circuit, and a search process adapted to the format of the circuit connection information is performed to invert the preceding stage. The data output is connected to the data input of the subsequent stage through the odd number of inverting buffers connected in cascade,
Further, a search means 21 for obtaining a pair of flip-flops whose scan data output of the preceding stage is connected to the scan data input of the succeeding stage directly or via a non-inverting buffer, and a flip-flop obtained by the searching means 21 by fetching circuit connection information. , The non-inverted data output and the data input in the preceding stage and the scan data output and the scan data input in either one of the periods, the output end of the preceding stage and the input end of the succeeding stage separately And an editing means 23 for performing an editing process for merging the sections.

[0017]

In the layout design support apparatus according to the first aspect of the present invention, the retrieval means 11 retrieves the circuit connection information so that the non-inverted data output of the preceding flip-flop becomes the data input of the succeeding flip-flop. Directly or via a non-inverting buffer, and the scan data output of the preceding flip-flop is directly connected to the scan data input of the same subsequent flip-flop, or the flip-flop of the flip-flop connected via a non-inverting buffer. Ask for a pair. The editing means 13 includes, between the non-inverted data output and the data input, the scan data output and the scan data input, in the portion corresponding to the pair of flip-flops thus obtained in the circuit connection information described above. Edit processing is performed on any one of the sections between and between and between and between the section and the section where the other section is individually merged with the output terminal of the front-stage flip-flop and the input terminal of the rear-stage flip-flop.

Further, regarding these sections, in general,
Only one of the normal operation state and the test operation (scan mode) state of the circuit is used as a signal line,
On the contrary, since the output end of the previous stage of the unused section is set to the ungrounded state or the unpowered ungrounded state or is configured with the circuit that enables the wired OR, the normal operation is achieved even if it is merged as described above. Guaranteed.

That is, among the flip-flops included in the circuit to be arranged on the chip of the integrated circuit prior to the layout design, the above-mentioned pair of flip-flops is guaranteed to operate normally while sharing the signal line between the stages. Since the circuit connection information is subjected to an edit process that can be realized, the area occupied by the wiring pattern on the chip is reduced, the wiring rate is efficiently increased, and the number of steps required for layout design is reduced.

In the layout design support apparatus according to the second aspect of the present invention, the search means 21 searches the circuit connection information so that the inverted data output of the preceding flip-flop is an odd number to the data input of the subsequent flip-flop. Of the flip-flops connected via the non-inverting buffer, and the scan data output of the flip-flop of the preceding stage is directly connected to the scan data input of the flip-flop of the same succeeding stage, or of the flip-flops connected via the non-inverting buffer. Ask for a pair.

The editing means 23 performs the same editing process as the editing means 13 in the layout design support apparatus according to the present invention on the circuit connection information corresponding to the pair of flip-flops thus obtained. Therefore, the area occupied by the wiring pattern on the chip is reduced, the wiring rate is efficiently increased, and the number of steps required for layout design is reduced.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a diagram showing an embodiment corresponding to the invention described in claims 1 and 2.

In the figure, the processing device 31 is connected to an external storage device 32 and a terminal 33 via a predetermined interface section (not shown). Regarding the correspondence relationship between the present embodiment and the block diagram shown in FIG. 1, the processing device 31, the external storage device 32, and the terminal 33 are the search means 1.
1 (21) and editing means 13 (23).

FIG. 3 is an operation flowchart of this embodiment.
It is (1). FIG. 4 is an operation flowchart of this embodiment.
(2) The operation of this embodiment will be described below with reference to FIGS.

In the external storage 32, the circuit connection information generated in the preceding logic designing or circuit designing process (here, for simplicity, the contents are the same as those shown in FIG. 9). Is stored in advance. In the main memory (not shown) of the processing device 31, as shown in FIG. 5, for all two combinations of the flip-flops (flip-flops with scan) included in the above-mentioned circuit connection information, the non-inverting output of the preceding stage is output. The presence / absence of a direct connection between Q and the input D in the subsequent stage and a direct connection between the scan data output SOD in the previous stage and the scan data input SID in the subsequent stage are individually shown.
Along with the bit control information, a net identification table including a set of information including a pointer value PM indicating the position of the unit connection information to be edited out of the individual unit connection information included in the circuit connection information is arranged. .

The processing device 31 sends a process start request to the terminal 33 in addition to the file identification information of the circuit connection information.
, The circuit connection information is read into the main memory and processed according to the following procedure. In the following, the circuit connection information thus read out on the main memory is also referred to as “circuit connection information” for simplicity.

The processor 31 sets "0" as an initial value in all storage areas of the net identification table (FIG. 3 (1)),
Moreover, the pointer value PTR for referring to the circuit connection information is set to "0" (FIG. 3 (2)). Furthermore, the processing device 31
Reads the unit connection information by referring to the circuit connection information based on such a pointer value PTR (FIG. 3 (3)).

Further, the processing device 31 determines whether either the starting point or the connection destination included in the unit connection information is the non-inverted output Q of the flip-flop indicated by the identifier FF (FIG. 3). (Four)). Note that, hereinafter, the flip-flop in the case where the result of such determination is true is referred to as a “previous-stage flip-flop”.

Further, when the result of the determination is true, the processor 31 determines whether or not the connection point or the start point facing the start point or the connection point is the input D of the flip-flop different from the above-mentioned flip-flop. It is determined (FIG. 3 (5)). Note that, in the following, the flip-flop in the case where the result of such determination is true is referred to as a “post-stage flip-flop”. When the result of the determination is true, the processing device 31 identifies the identification numbers i and j of the corresponding front-stage flip-flops and rear-stage flip-flops.
Based on the above, the net identification table is referred to and the control information of the storage area corresponding to these identification numbers is set to the bit string “10”
It is updated by taking the logical sum of and (Fig. 3 (6)).

On the other hand, when the processing device 31 recognizes that the determination result of either one of the above two determination processes ((4) and (5) in FIG. 3) is false, the corresponding unit connection information is obtained. It is determined whether or not the starting point or the connection destination included in is the scan data output SOD of the flip-flop indicated by the identifier FF (FIG. 3 (7)). Note that, hereinafter, the flip-flop in the case where the result of such determination is true is referred to as a “previous-stage flip-flop”.

Further, when the result of the determination is true, the processing device 31 is the scan data input SID of the flip-flop whose connecting point or starting point opposite the starting point or connecting point is different from the above-mentioned flip-flop. It is determined whether or not (Fig. 3 (8)). Note that, in the following, the flip-flop in the case where the result of such determination is true is referred to as a “post-stage flip-flop”. When the result of the determination is true, the processor 31 refers to the net identification table based on the identification numbers i and j of the corresponding front-stage flip-flops and rear-stage flip-flops, and responds to these identification numbers. The control information of the storage area is updated by taking the logical sum of the bit string "01" (FIG. 3 (9)). Further, the processor 31 writes and holds the pointer value PTR (= x) at this point in the pointer field of the net identification table (FIG. 3 (10)).

The processing device 31 recognizes that the determination result of either one of the above-described two determination processes (FIGS. 3 (7) and (8)) is false, When one of the processes shown in (10) to (10) is completed, it is determined whether the same process has been performed for all the unit connection information based on the pointer value PTR described above ((11) in FIG. 3). If the result is false, the pointer value PTR is updated based on a predetermined algorithm and the series of processes described above (FIGS. 3 (3) to (11)) are repeated.

Therefore, the non-inverted output Q of the front-stage flip-flop is directly connected to the input D of the rear-stage flip-flop, and the scan data output SOD of the same front-stage flip-flop is directly connected to the scan-data input SID of the same rear-stage flip-flop. Only in such a case, both 2 bits of the control information stored in the net identification table corresponding to the corresponding front-stage and rear-stage flip-flops are both set to the logical value "1".

Further, the processing device 31 sets "1" as the initial value of the pointer value i corresponding to the preceding flip-flop among the pointers used when referring to the net identification table (FIG. 4 (1)). ). Furthermore, the processing device 31
Similarly sets "2" as the initial value of the pointer value j corresponding to the flip-flop in the subsequent stage ((2) in FIG. 4).

The processor 31 determines whether the pointer value i and the pointer value j are the same (FIG. 4 (3)). If they are different, the flip-flops corresponding to these pointer values are the same. Recognize that it is not a thing, and that there may be a relationship between the first stage and the second stage. In such a case, the processing device 31 refers to the net identification table based on the pointer values i and j, and sets 2 of the control information corresponding to these pointer values.
It is determined whether or not all the bits are logical "1" (FIG. 4 (4)).

When the result of such a determination is true, the processor 31 recognizes that there is no combinational circuit between the corresponding front-stage flip-flop and corresponding rear-stage flip-flop. Furthermore, the processing device 31
Refers to the circuit connection information based on the pointer value stored in the net identification table together with the control information described above, and as shown in the comparison between FIG. 9 and FIG. 6, the corresponding unit connection information “FF _i -SOD to ff _j -SID instead "set the unit connection information of" FF _j -D~FF _j -SID ", and the new end of the circuit connection information" FF _i -Q~
FF _i −SOD ”is set (FIG. 4 (5)).

The processing device 31 completes such processing, judges that the pointer value i and the pointer value j are the same in the judgment processing shown in FIG. 4 (3), and shows in FIG. 4 (4). The content of the corresponding control information in the determination process is “11”
If not, the pointer values i and j indicating the effective area of the net identification table are sequentially increased with the maximum values i _max and j _max as upper limits, and the series of processes described above (see FIG. 4). (2) to (5)) are repeated (Fig. 4
(6)).

Therefore, the circuit connection information is edited by being shaded in FIG. 6, and in the layout design process performed based on the circuit connection information thus edited, FIG. As shown, flip-flop 81 ₁
Scan data output SDO to flip-flop 81
Wiring section leading to the _second scan data input SDI is treated as an integrated wiring path in the section leading to the input D of the flip-flop 81 ₂ from the non-inverting output Q of the flip-flop 81 _1.

On the other hand, with respect to the flip-flops 81 _{1 to} 81 _N , in general, the non-inverted output Q and the scan data output SDO are internally output with the same logical value in both the normal operation state and the scan mode state. Are individually output via the same output circuit. Further, even if the output terminals of the non-inverted output Q and the scan data output SDO are directly connected to these output circuits, the logic values of the signals output from these outputs do not change, and a fixed fault occurs. A circuit method (for example, a single transistor pulled up by a resistor) is applied.

Therefore, if no combinational circuit is interposed between these flip-flops, the function is not impaired even if the wiring paths are integrated as described above.

In addition, a circuit in which two flip-flops are directly connected without any combinational circuit in this way is generally a first stage settling circuit to which a signal is externally applied via an LSI pin, and its LSI. Between a plurality of circuit blocks and functional blocks arranged on a chip (for example, a section of a bus connecting an arithmetic circuit and a memory circuit)
Many are included as interface circuits and others. Further, since the number of such circuits generally reaches a large value of 100 to several hundreds depending on the circuit scale and the number of pins of the LSI, the number of such circuits on the chip is increased according to the unification of the above-mentioned wiring paths. The required area is greatly reduced.

As described above, according to the present embodiment, by editing the circuit connection information prior to the layout design, the length of the wiring to be performed based on the circuit connection information is greatly reduced, so that the chip The size can be kept small, the wiring rate can be increased, and the layout design can be made more efficient. In addition, the number of man-hours such as optimization of layout and other trial and error that were conventionally performed before changing the chip size to a large one is reduced, and the layout design can be completed without changing the chip size. Is increased.

In this embodiment, the non-inverted output Q of the preceding flip-flop is the input D of the following flip-flop.
The pair of flip-flops is retrieved from the circuit connection information on the condition that they are
Without being limited to such a condition, when the inverted output XQ of the flip-flop of the preceding stage is connected to the input D of the succeeding stage through an odd number of inverters, it is possible to obtain the signals shown in FIGS. 3 (3) to (4) and FIG. Five)~
In the determination processing shown in (6), the search condition is that the inverted output XQ of the front-stage flip-flop is connected to the input D of the rear-stage flip-flop via an odd number of inverters. Similarly to the layout design support apparatus according to the invention described in (1), the circuit connection information editing process can be similarly applied to a pair of flip-flops that perform an operation equivalent to that of this embodiment.

Further, in this embodiment, by searching the circuit connection information, the non-inverted output Q of the preceding flip-flop is directly connected to the input D of the succeeding flip-flop, and the skinner data output SDO of the preceding flip-flop is obtained. Although the pair of flip-flops directly connected to the scan data input SDI of the subsequent flip-flop has been obtained, the present invention is not limited to the pair of flip-flops having such a configuration, and, for example, the above-mentioned non-inverting output Q and input An arbitrary number of non-inverting buffers and an even number of inverters connected in series with D are arranged, and such non-inverting buffers and inverters further include the scan data output SDO described above.
And the scan data input SDI, the non-inverting buffer or the inverter described above is used in the determination process shown in FIGS. 3 (3) to (4) and 3 (5) to (6). This can be applied by performing a determination process that allows the intervention.

Further, in the present embodiment, the control information and the pointer corresponding to the same combination of the flip-flops are arranged in the net identification table, but the present invention is not limited to the net identification table having such a configuration, and the certainty is sure. If the addressing is possible, it is possible to apply a net identification table of any configuration including a storage area corresponding to only a combination of different flip-flops.

Further, in this embodiment, first, all the unit connection information included in the circuit connection information is searched to extract all the pairs of flip-flops, and then the unit connection corresponding to each pair of flip-flops is extracted. Although information editing processing is performed, the present invention is not limited to such serial processing, and a processing mode in which the editing work is performed in parallel each time a pair of flip-flops is extracted may be adopted.

Further, in the present embodiment, the corresponding unit connection information is edited for all the flip-flop pairs given by the circuit connection information, but the present invention is not limited to such a processing form. If the area occupied by the wiring on the chip can be surely reduced, the editing process may be interrupted based on an arbitrary algorithm.

Further, in the present embodiment, for each pair of flip-flops, one unit connection information to be edited is rewritten, and one unit connection information is newly added to the end of the circuit connection information. However, the present invention is not limited to such a process. For example, the unit connection information to be rewritten may be deleted and two unit connection information may be added to the end of the circuit connection information. Regardless of which method of editing the circuit connection information is adopted, the unit connection information may be sorted based on a desired key.

Further, in the present embodiment, the circuit connection information is given as a set of unit connection information indicating individual connection sections constituting the circuit, but the present invention is not limited to such a configuration, and the flip-flop is not limited thereto. Circuit connection information in a format that permits the display of a plurality of connection destinations corresponding to one starting point, if the edit processing is surely performed on the search processing of the pair of flip-flops and the pair of flip-flops obtained by the search processing. May be

Further, in this embodiment, the wiring between the scan data output SDO of the front stage flip-flop and the scan data input SDI of the rear stage flip-flop has a non-inverted output Q of the front stage flip-flop and the rear stage flip-flop. However, the present invention is not limited to such a method, and conversely, between the scan data output SDO of the preceding flip-flop and the scan data input of the following flip-flop. The wiring between the non-inverted output Q of the front-stage flip-flop and the input D of the rear-stage flip-flop may be merged with the wiring.

Further, in the present embodiment, the non-inverted output Q and the scan data output S of the flip-flops 81 _{1 to} 81 _N are output.
The DO and the output always have the same logical value, and the output stages of these outputs are composed of a circuit that does not cause a failure even if it is externally diameterd, but the present invention is limited to the circuit having such a structure. However, for example, only one of the normal operation state and the test operation (scan mode) state is active, and the other output terminal that is not used is set to the ungrounded state or the unpowered ungrounded state. It may be one.

In this embodiment, the signal lines between the paired stages of the flip-flops are merged by editing the circuit connection information. However, in addition to this method, for example, the corresponding unit connection By updating the identification information of the basic element included in the information, the first flip-flop in which the non-inverted output Q and the scan data output SDO are directly connected in advance is arranged as the front-stage flip-flop, and as the rear-stage flip-flop. A method of arranging a second flip-flop in which the input D and the scan data input SDI are directly connected in advance may be applied.

Further, in the present embodiment, all the processing is performed based on the software executed by the processing device 31, but the present invention is not limited to such a configuration, and any processing is dedicated. The configuration may be performed by hardware, a plurality of processing devices to which the load distribution method or the function distribution method is applied, or dedicated hardware.

In the present invention, as for the layout design method to be applied, if the circuit connection information adapted to the method is surely generated by performing the above-mentioned editing process, the manual design method and the symbolic layout design are used. Any method such as a method and an automatic layout design method may be applied.

[0055]

As described above, according to the present invention, prior to the layout design, the signal line between the stages of the pair of flip-flops indicated by the circuit connection information is directly connected,
Since the circuit connection information is subjected to the editing process for sharing the signal line of the data or scan data connected via the gate that guarantees the consistency of the logical value, the area occupied by the wiring pattern on the chip is reduced. It

Further, in the layout design process, the wiring rate is efficiently increased, and in order to increase the wiring rate, the chip size is changed to a large size and the layout is optimized prior to the change. It reduces the need for man-hours.

Therefore, the integrated circuit designed by applying the present invention can be manufactured at low cost, the response characteristics and reliability can be improved, and the efficiency of the integrated circuit design and the working environment can be improved. .

[Brief description of drawings]

FIG. 1 is a principle block diagram of the invention described in claims 1 and 2. FIG.

FIG. 2 is a diagram showing an embodiment corresponding to the invention described in claims 1 and 2.

FIG. 3 is an operation flowchart (1) of this embodiment.

FIG. 4 is an operation flowchart (2) of this embodiment.

FIG. 5 is a diagram showing a configuration of a net identification table.

FIG. 6 is a diagram showing circuit connection information edited according to the present embodiment.

FIG. 7 is a diagram illustrating a layout result based on edited circuit connection information.

FIG. 8 is a diagram showing an example of a circuit designed by applying a scan path method.

FIG. 9 is a diagram showing a structure of circuit connection information.

FIG. 10 is a diagram showing a configuration of a basic element table.

[Explanation of symbols]

 11, 21 Searching means 13, 23 Editing means 31 Processing device 32 External storage device 33 Terminal 81 Scanning flip-flop 82 AND gate 83 OR gate 84, 86 Inverter 85 Non-inverting buffer

Claims (2)

[Claims] 1. A search process adapted to the format of the circuit connection information is applied to the circuit connection information of the circuit to be arranged on the integrated circuit by applying the scan path method, and the non-inverted data output of the preceding stage is directly or non-existent. Retrieval means (11) for obtaining a pair of flip-flops connected to the data input of the subsequent stage via the inverting buffer and the scan data output of the previous stage directly or via the non-inverting buffer to the scan data input of the subsequent stage, For the pair of flip-flops obtained by the search means (11) by taking in the circuit connection information, the section between the non-inverted data output and the data input, the section between the scan data output and the scan data input, Editing means for performing an edit process for separately merging one of the sections with the output section of the preceding stage and the input section of the latter stage separately. 13) and a layout design support device. 2. The scan connection method is applied to the circuit connection information of the circuit to be arranged on the integrated circuit, and a search process suitable for the format of the circuit connection information is performed, and the inverted data output of the preceding stage is cascaded. Retrieval means (21) for obtaining a pair of flip-flops connected to the data input of the succeeding stage through an odd number of inverting buffers and the scan data output of the preceding stage directly or via the non-inverting buffer to the scan data input of the succeeding stage. ), The circuit connection information is taken in, and for the pair of flip-flops obtained by the search means (21), the section of the non-inverted data output of the preceding stage and the data input, the scan data output and the scan data input Edit processing for merging the other section separately in the output end of the preceding stage and the input end of the latter stage in one of the sections The layout design support apparatus characterized by comprising a edit unit (23).