JPH07253766A - Driving circuit for display device, display device and display method - Google Patents

Abstract

PURPOSE:To provide the driving circuit of a display device which realizes multiple gray levels of shades by the use of a small number of reference power sources, reducing loads of the reference power sources, and gives no output deviation and to provide such a display device. CONSTITUTION:The display device using capacitive devices as image information storing means has a decode and select circuit 15 which decodes input image data D1 to D4 and selects one or more reference power sources from a specified number of reference power sources V1 to V9 in accordance with the decoded outputs DE1 to DE9. The decode circuit 16 is controlled by the timing signal TM which determines the output period of a single reference power source and by the enable signal OE which determines the effective period of the output in order to control the decoded outputs DE1 to DE9 and the supply of the reference voltages V1 to V9 to picture element electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit, a display device and a display method for a display device, and more particularly to a drive circuit, a display device and a display method for a display device using a capacitive element as image information storage means.

An active matrix type capacitive display device in which a switching transistor is provided in each pixel can easily realize a thinner and lighter weight than a CRT and can obtain a display quality comparable to that of a CRT. It is used for purposes. Recently, there has been a demand for a multi-color compatible data driver because the number of colors has been increased in order to enhance the expression.

[0003]

2. Description of the Related Art A panel structure of an active matrix type capacitive display device having a high display quality among flat panel displays will be described. This is because the electrodes run in a matrix,
A capacitive element (hereinafter, a liquid crystal will be taken as an example of the capacitive element will be described) is enclosed between a substrate to which a switching element (TFT or the like) is connected at the intersection and a substrate on which electrodes are evenly wound. Have a different structure. Here, the former substrate is called a TFT substrate and the latter substrate is called a common substrate.

FIG. 15 shows a block diagram of a TFT substrate of a liquid crystal display device.

As shown in FIG. 15, data bus lines (signal electrodes) 32 and gate bus lines (scanning electrodes) 33 intersect in a matrix on the TFT substrate 31, and the TFTs 34 function as switching elements at all the intersections. It is connected. T of the row selected by the gate bus line 33
When the FT 34 turns on, the data bus line 32
The video signal voltage applied to the pixel electrode 35 is written in each pixel electrode 35, and the electric charge is retained until the row is selected next, whereby information is retained. Since the tilt of the liquid crystal is determined according to the information held, it is possible to control the amount of light transmission,
It is possible to display gradation. Furthermore, to display in color,
It is realized by mixing light using RGB color filters.

A peripheral circuit for driving the LCD is composed of a data driver connected to the data bus line 32 side and a gate driver connected to the gate bus line side. When ON voltage is output from the gate driver,
A voltage corresponding to the video signal is applied to the selected pixel through the data driver.

FIG. 16 shows a conventional example of a 16 gradation data driver. CLK is the clock for the shift register, S
P is the start pulse, RDATA, GDATA, and BDATA are 4-bit digital video signals, LP is a latch pulse for transferring data from the first digital memory 32 to the second digital memory 33, and V1 to V16 are 16 gradations. It is a reference power source corresponding to the voltage of. The video signal synchronized with CLK is input while being shifted by the shift register 31.
By P, loading into the first digital memory 32 is started. After the video signal for one line is captured, LP
Thus, the information in the first digital memory 32 is transferred to the second digital memory 33. The second digital memory 33 holds data for one line, and when the data for one line is held, the data for one line is collectively supplied to the decode & select circuit 34 according to the line pulse LP. . The decode & select circuit 34 decodes the data supplied from the second digital memory 33, obtains the decoded data DE1 to DE16, selects one of the voltages V1 to V16 according to the result, and outputs it to the outside. FIG. 17 shows a circuit for selecting one of the voltages V1 to V16 from the decode data DE1 to DE16. FIG. 17 shows an example in which V1 is selected.

FIG. 18 shows another conventional example of the 16 gradation data driver. 16, those parts which are the same as those corresponding parts in FIG. 16 are designated by the same reference numerals, and a description thereof will be omitted. The basic operation is the same as that of the driver of FIG. 16, but the decode & select circuit 35
And the gradation control method is different. FIG. 19
The operation explanatory diagram is shown in FIG. Decode & select circuit section 3
Reference numeral 5 is to output the intermediate voltage by using the ON resistance of each switch by selecting V1 and V2 at the same time. Here, an example in which V1 and V2 are simultaneously selected is shown. When this method is used, 16 types of reference power sources are required in the conventional example, whereas 9 types of reference power sources 1 to V9 are sufficient in other conventional examples. This reduces the area of the decode and select circuit, which occupies most of the chip area, and thus leads to the cost reduction.

[0009]

However, among the drive circuits of the conventional display device shown in FIG. 16 and FIG.
There are problems that the number of reference voltages is large, the number of wirings for supplying the reference voltage is large, the area occupied by the data & select circuit is increased, and the miniaturization of the display device is hindered.

Further, in a display device using a resistance voltage dividing type data driver which is another conventional example in which the number of reference power sources is reduced, as shown in FIG. There are problems that the power consumption increases and that the potential of the single selection output deviates due to the influence of the wiring resistance inside the chip.

The present invention has been made in view of the above points, and it is possible to realize a multi-gradation with a small number of reference power sources while reducing the load on the reference power source, and a drive circuit of a display device having no output deviation. An object is to provide a display device and a display method.

[0012]

FIG. 1 shows a block diagram of the principle of the present invention. In the figure, a selection unit 1 is supplied with a predetermined number of reference voltages and image data, selects one or a plurality of reference voltages from the predetermined number of reference voltages according to the image data, and supplies the selected reference voltage to one pixel electrode of the display device. .

The reference voltage supply control means 2 controls the timing of supplying a plurality of selected reference voltages to one pixel electrode.

According to a second aspect of the present invention, the reference voltage supply control means 2 divides one output period to one pixel electrode into a first half and a second half, one of which is a period for selectively selecting and outputting the other, and a plurality of reference voltages are selected. In case of output.

In the present invention, the reference voltage control means 2 switches the output timing of the reference voltage for each pixel electrode.

According to a fourth aspect, one or a plurality of reference voltages selected by the selecting means 1 are supplied to the pixel electrode, and an image corresponding to the image data is displayed according to the selected one or a plurality of reference voltages. To do.

According to a fifth aspect, the reference voltage supply control means 2
By setting the period for selecting the reference voltage independently and the period for selecting the multiple reference voltages to be different, it is possible to reduce the voltage fluctuation at the time of mixed output at the time of voltage division selection and single selection, and at the same time, to output multiple gradations. To realize.

[0018]

According to the first aspect of the present invention, the plurality of reference voltages are made different by controlling the timing of supply to each pixel electrode of the one or more reference voltages selected by the reference voltage control means. Since it can be supplied to one pixel electrode at different timings, a reference voltage selected independently and a plurality of reference voltages can be output in different periods. Therefore, a single reference voltage can be output independently from one pixel selected. Even when other pixels in which a plurality of reference voltages including the reference voltage are selected are driven in the same period, the number of pixel electrodes that must supply the same reference voltage in the same period can be reduced, Therefore, the fluctuation of the reference voltage can be reduced.

According to the second aspect, the period for supplying the reference voltage to one pixel electrode is divided into the first half and the latter half, and when one is the reference voltage alone, the other is the output period when the reference voltage is plural. Since the same reference voltage can be output less frequently in the same period, the fluctuation of the reference voltage can be reduced.

According to the third aspect, since the number of pixel electrodes driven at the same timing can be reduced by controlling the output timing of the reference voltage for each pixel electrode, the same reference voltage is supplied at the same timing. The number of pixel electrodes can be reduced, and thus the fluctuation of the reference voltage can be reduced.

According to a fourth aspect, the drive circuit of the display device according to any one of the first to third aspects supplies one or a plurality of reference voltages corresponding to the image data to the pixel electrodes, and the reference voltages are supplied according to the image data. By displaying the displayed image, the output deviation of the voltage supplied to each pixel electrode can be reduced, so that the displayed image is less likely to be uneven and the display image quality can be improved.

According to the fifth aspect, since a single reference voltage or a plurality of reference voltages can be supplied at different timings, it is possible to reduce the fluctuation of the reference voltage, reduce the unevenness of the display image, and improve the image quality.

[0023]

FIG. 2 shows a block diagram of an embodiment of the present invention. The drive circuit 11 of the display device of this embodiment includes a shift register circuit 12, first and second digital memories 1.
3, 14 and a decode & select circuit section 15.

The driving circuit 11 is composed of, for example, n color pixels in one line, and one pixel is R (red) or G.
It is composed of dots of three colors (green) and B (blue).
It is assumed that a display device having m (3n) dots in a line is driven. At this time, the clock CLK and the start pulse SP are supplied to the shift register circuit 12,
The start pulse SP is taken in and output while sequentially moving the output terminals T _{s1 to} T _sn in accordance with the clock CLK.

The clock CLK generates at least n pulses for each line cycle, and the start pulse SP generates one pulse for each line cycle.

Output terminals T _s1 of the shift register circuit 12
T _sn is connected to the first digital memory 12.
The first digital memory 12 has m storage areas,
The outputs of the output terminals T _{s1 to} T _sn of the shift register 12 are supplied to the three storage areas as write signals.

Image data for one pixel is supplied in parallel to the first digital memory 12 for each of K, G and B, and R, R depending on the outputs of the output terminals T _{s1 to} T _sn of the shift register circuit 12. The image data composed of G and B is captured and held.

The first digital memory 12 supplies the held data to the second digital memory 13. At this time, data is output from the first digital memory 12 for each of R, G, and B, and m pieces of data are output as a whole.

Image data is supplied to the second digital memory 13 from the first digital memory 12 and a line pulse LP is supplied for each line, and is supplied from the first digital memory 12 in response to the line pulse LP. The created image data is retained. Second digital memory 1
The data held in 3 is the decode & select circuit section 15
Is supplied to.

The decode & select circuit section 15 is provided with decode & select circuit sections 15 _-1 to 15 _-m corresponding to the data bus lines DBL _{1 to} DBL _3n of the display device. Image data separated into R, G, and B for each dot by the digital memories 12 and 13 is supplied, and a voltage is supplied to each data bus line DBL _{1 to} DBL _n in accordance with the supplied image data.

FIG. 3 shows the decode & select circuit section 15 _-1 .
The block diagram of 15- _m is shown. One decode & select circuit 15 _-1 decodes R, G, B video data and generates a control signal according to each of the R, G, B video data from a plurality of reference voltages A predetermined number of reference voltages V according to the control signal generated by the circuit 16
₁ composed of a select circuit 17 for selecting one or more voltage than ~V _9.

FIG. 4 shows a block diagram of the decoding circuit 16.
The decoding circuit 16 includes AND gates 18 _-1 to 18 _-24 , 1
9 _{-1 to} 19 _-8 and inverters 20 _{-1 to} 20 _-3, and generates control data for controlling the select circuit 17 according to the input data D _{1 to} D ₄ .

The first control signal TM is Vn and Vn + 1.
It is a timing signal that determines the output time of Vn + 1 when the partial pressure is selected such that (1 ≦ n ≦ 8). The second control signal OE is
This is an output enable signal that determines the effective period of the output.

[0034] Figure 5 shows the output logic of the control data DE1~DE9 corresponding to the input data D ₁ to D _4.

FIG. 5A shows the output logic when the first control signal TM = 1 and the second control signal OE = 1. In the figure, the data of "1" among the control data DE1 to DE9 selects the reference voltage.

FIG. 5B shows the control data DE for the input data D ₁ , the first control signal TM and the second control signal OE.
Indicates the output status of _{1 to} DE ₉ . When D1 = 1 and TM = 1, a plurality of reference voltages are selected, a divided voltage is obtained, and D
When 1 = 0 and DE = 0, DE1 to DE9 are fixed to 0, and when D1 = 0, DE = 1 or DE = 1 and TM = 0, the reference voltage is independently selected.

The select circuit 17 is composed of SW ₁ to SW ₉ switches to select the reference power V1 to V9.

Switch SW₁~ SW₉Is the reference voltage V₁
~ V₉Is generated and is generated by the decoding circuit 16
Control signals DE1 to DE9 are supplied, and control signals
Switch SW by DE1 to DE9₁~ SW₉Switch
The reference voltage V₁~ V ₉Control the applied state of
Switch SW₁~ SW₉Group applied by the internal resistance of
The reference voltage V₁~ V₉Get the intermediate value of
It is configured.

FIG. 6 shows an operation explanatory diagram. In the decode & select circuit section 15, the power supply selection signals DE1 to DE9 are received according to the video data (D4 to D1) fetched from the outside.
To create. As an example, a case in which a single selection of V ₁ in FIG. 6 (A), the case where the partial pressure selection of V ₁ and V ₂ 6
It shows in (B). FIG. 6 (A) shows that DE ₁ during the period of OE = ₁
V ₁ selected by is output alone, the output is opened during the period of OE = 0, and the voltage is held in the capacitor on the liquid crystal panel. FIG. 6 (B) shows DE during the period TM = 0.
V ₁ selected by ₁ is output alone, TM = 1
V ₂ selected by DE ₂ during the period is simultaneously selected with V ₁ , and the output voltage finally becomes (V ₁ + V
₂ ) It falls to the potential of / 2. In this way, by dividing the periods of single selection and partial pressure selection, it is possible to obtain a multi-tone driver with no output deviation even when both are mixed in the same driver.

FIG. 7 shows an example of operation timing. HS is a horizontal synchronizing signal, D _{4 to} D ₁ are digital 4 bits of video data, SP is a start pulse signal for starting data capture, CLK is a shift register operation clock, and S ₁
And S ₂ is an internal shift register output, LP is a latch pulse for transferring data from the first digital memory 13 to the second digital memory 14 every horizontal period, and TM is a ratio of output periods of single selection and voltage division selection. And OE is an enable signal that determines the effective period of the output. As an example, (D ₄ , D ₃ , D ₂ , D ₁ ) = (0,
8 (A) and 8 (A), the waveforms of the reference power supply selection signals DE ₁ and DE ₂ , the driver output, the gate output, and the pixel potential change in the case of (0, 0, 0) and (0, 0, 0, ₁ ) B). As shown in the former FIG. 8A, V ₁ is independently selected during the period of DE ₁ being ₁ to charge the pixel to the voltage V ₁ . After that, DE ₁ is controlled to 0 by the enable signal OE,
Output is open. The voltage V ₁ held in the distributed capacitance of the liquid crystal panel is held in the pixel when the gate output is turned off, and continues to hold information until the same pixel is rewritten next. In the latter case, as shown in FIG.
= V ₁ by DE ₁ during the period 0 is independently selected, to charge the pixel to V _1. Then, during the period of TM = 1, DE ₁
Is valid, DE ₂ is valid, V ₁ and V ₂ are simultaneously selected, and the pixel is charged with (V ₁ + V ₂ ) / 2. Charged voltage (V ₁ + V ₂ ) / 2 is gate output OF
When it becomes F, it is held in the pixel, and the information is kept held until the same pixel is rewritten next.

FIG. 9 shows a block diagram of a modification of the decoding circuit 16. The decoding circuit 16 of the present modification is the AND gate 2
1 _{-1 to} 21 _-24 , gate 22 _{-1 to} 22 _-8 , inverter 2
3 is constituted from _-1 to 23 _-4, and generates a control signal for controlling switching of switch SW ₁ to SW ₉ of the select circuit 17 selects the voltage V ₁ ~V ₉ according to the input data D ₁ to D _4.

FIG. 10 shows an operation explanatory diagram of a modification of the decoding circuit 16.

When D1 = 0, that is, when the voltage division is not selected, the original single selection is performed regardless of the enable signal OE and the timing signal TM. When D = 1, that is, when the voltage division is selected, the timing signal TM is valid while the OE signal is 1, and when TM = 0, the timing signal TM is independently selected.
When = 1, partial pressure is selected. During the period of OE = 0, the output is open because it is fixed at 0. In the case of this modification, the output voltage period is divided into two, that is, the partial pressure selection period in the first half and the single selection period in the second half.

FIG. 11 shows an example of operation timing according to this modification. The main signals are the same as in FIG. 11, but the waveform of the timing signal TM is different. (D ₄ , D ₃ , D ₂ ,
D ₁ ) = (0,0,0,0) and (0,0,0,1) waveforms of reference power source selection signals DE ₁ and DE ₂ , driver output, gate output, and pixel potential change timing Is shown in FIG. (D ₄ , D ₃ , D ₂ , D ₁ ) =
In the case of (0,0,0,0), as shown in FIG. 12A, DE ₁ and DE ₂ are simultaneously selected in the period of TM = 1, and (V ₁ + V ₂ ) / 2 is reserved for the pixel. Be charged. After that, when the timing signal TM = 0, DE ₂ becomes invalid,
The original V ₁ is charged to the pixel. The finally charged voltage V ₁ is held in the pixel when the gate output is turned off, and continues to hold information until the same pixel is rewritten next. In the latter case, D is generated during the period of timing signal TM = 1.
E ₁ and DE ₂ are selected at the same time, and the pixel (V ₁ + V ₂ )
/ 2 is charged. After that, DE ₁ and DE ₂ are controlled to 0 by the enable signal OE, and the outputs are open. The voltage (V ₁ + V) held in the distributed capacitance of the liquid crystal panel
₂ ) / 2 is held in the pixel when the gate output is turned off, and continues to hold information until the same pixel is rewritten next.

In the above example, the period is divided into two periods including one single selection period and one divided voltage selection period, but the divided voltage selection period may be divided into two or more periods. For example, if two periods corresponding to odd-numbered channels and even-numbered channels are provided in the voltage division selection period, the number of simultaneously divided voltages is half of the total number of data lines, and the amount of current that instantaneously flows is It is possible to reduce the load on the reference power source.

Decoding using the decoding circuit of FIG. 9 &
A modification of the select circuit 15 is shown in FIG.

The decode & select circuit 15 of this modification is provided for each of the data bus lines, the decode circuit 16 for generating the data DE _{1 to} DE ₉ , the odd / even timing control circuit 24 for generating the odd / even timing control signal for controlling the odd / even timing. ₁ to DE ₉ from the decoding circuit 16 and select circuits 25 _{-1 to} 25 _-n which generate output voltages based on the signals from the odd / even timing control circuit 24.

Each of the decode circuits 16 _{-1 to} 16 _-n is composed of the circuit shown in FIG. 9, and supplies the decode data DE _{1 to} DE ₉ to the select circuits 25 _{-1 to} 25 _-n . The odd-even timing control circuit 24 is composed of AND gates 24a and 24b and inverters 24c and 24d, is supplied with the data D ₁ and the second enable signal OE _2, and generates an odd timing control signal and an even timing control signal.

The select circuits 25 _{-1 to} 25 _-n are the decode data DE _{1 to} DE ₉ from the decode circuits 16 _{-1 to} 16 _-n.
In addition to the switches SW ₁ to SW ₉ which switch in accordance with the above, switches which switch in accordance with the odd-even timing control signal are respectively provided.

The enable signal OE ₂ is an odd-numbered channel and an even-numbered channel c.
It is a signal for selecting h, and is valid when D1 = 1, that is, when voltage division is selected. In this case, when OE = 0, the odd-numbered channel is OE2 =
When 1 is set, even channels are enabled.

FIG. 14 shows an operation explanatory diagram of a modified example of the decode & select circuit. In the same figure, (A) shows the partial pressure selection output timing of V ₁ and V ₂ at odd channel output, and (B) shows the partial pressure selection output timing of V ₁ and V ₂ at even channel output.

As shown in the figure, according to this modification, the enable signal O is started from when the enable signal OE rises.
The odd-numbered channel becomes the charging period until E ₂ rises, and the even-numbered channel becomes the charging period from the rise of enable signal OE ₂ to the fall of enable signal OE, so the channels driven in one period are halved. Therefore, the number of reference voltages driven at the same time can be further reduced, so that the fluctuation of the reference voltage can be further reduced. In the above example, the 16-gradation driver is assumed, but the invention is not limited to this, and it is also possible to apply to each gradation driver having 16 gradations or more.

FIG. 15 shows a drive circuit using the above voltage division method.
By driving a liquid crystal display device such as that shown in Fig. 4, the load on the reference power source is lighter than in the past, and even when partial pressure selection and single selection are mixed, the effect of eliminating the potential fluctuation of the independently selected output is eliminated. It contributes to the improvement of the display quality of the display device.

[0054]

As described above, according to claims 1 and 2 of the present invention, one reference electrode having a single reference voltage selected and a plurality of reference voltages including a single reference voltage selected by one pixel electrode are provided. Even when the other pixel electrodes whose voltages are selected are selected in the same period, each pixel electrode can be driven at different timings, so that the number of pixel electrodes driven by the same reference voltage can be reduced, Since the fluctuation of the reference voltage can be reduced and therefore the deviation of the potential of the pixel electrode can be reduced, the display quality of the display device driven by the drive circuit of the present invention can be improved.

According to the second aspect, the same reference voltage is supplied by dividing the timing at which the reference voltage is supplied to the pixel electrode into the first half and the second half depending on the case of a single reference voltage and the case of a plurality of reference voltages. Since it is possible to reduce the number of pixel electrodes to be used, it is possible to reduce the fluctuation of the reference voltage, and thus the output deviation can be reduced.

According to the third aspect, since the number of pixel electrodes driven at the same timing can be reduced by controlling the timing for each pixel electrode, it is possible to reduce the pixel electrodes driven by the same reference voltage. Further, it has features that the fluctuation of the reference voltage can be reduced and the output deviation can be reduced.

According to the fourth aspect, by driving the display device by using the drive circuit of the display device according to any one of the first to third aspects, it is possible to reduce the output deviation of the reference voltage. It has features such as the ability to improve image quality.

According to the fifth aspect, the fluctuation of the reference voltage can be reduced by making the supply timing different for a single reference voltage or a plurality of reference voltages, so that the image quality of the display image can be improved.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of a decode & select circuit according to an embodiment of the present invention.

FIG. 4 is a configuration diagram of a decoding circuit according to an embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of the decoding circuit according to the embodiment of the present invention.

FIG. 6 is a diagram for explaining the operation of the embodiment of the present invention.

FIG. 7 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 9 is a configuration diagram of a modification of the decoding circuit according to the embodiment of the present invention.

FIG. 10 is an operation explanatory diagram of the decoding circuit of the modified example of the embodiment of the present invention.

FIG. 11 is an operation explanatory diagram of a drive circuit using a modified example of the embodiment of the present invention.

FIG. 12 is an operation explanatory diagram of a drive circuit using a modified example of the embodiment of the present invention.

FIG. 13 is a configuration diagram of a modification of the decode & select circuit according to the embodiment of the present invention.

FIG. 14 is an operation explanatory diagram of a modified example of the decode & select circuit according to the embodiment of the present invention.

FIG. 15 is a configuration diagram of a main part of a liquid crystal display device.

FIG. 16 is a configuration diagram of a conventional example.

FIG. 17 is a configuration diagram of a main part of a conventional example.

FIG. 18 is a configuration diagram of another example of the related art.

FIG. 19 is a configuration diagram of a main part of another example of the related art.

FIG. 20 is an operation explanatory diagram of another example of the related art.

[Explanation of symbols]

 1 Selection Means 2 Reference Voltage Supply Control Means 11 Drive Circuit 12 Shift Register Circuit 13 First Digital Memory 14 Second Digital Memory 15 Decode & Select Circuit Section

Claims (5)

[Claims] 1. A display device according to claim 1, wherein a predetermined number of reference voltages and image data are supplied, and one or a plurality of reference voltages are selected from the predetermined number of reference voltages by the selection means (1) according to the image data. A drive circuit of a display device for supplying to a pixel electrode is characterized by having a reference voltage supply control means (2) for controlling the timing of supply of one or a plurality of selected reference voltages to the one pixel electrode. Drive circuit of display device. 2. The reference voltage supply control means (2) divides one output period to the one pixel electrode into a first half and a second half, one of which is an output period when the reference voltage is independently selected, and the other is 2. The drive circuit of the display device according to claim 1, wherein is set as an output period when a plurality of reference voltages are selected. 3. The drive circuit for a display device according to claim 1, wherein the reference voltage supply control means (2) switches the output timing of the reference voltage for each pixel electrode. 4. One or a plurality of reference voltages selected by the selecting means (1) is supplied to a pixel electrode, and an image corresponding to the image data is displayed according to the selected one or a plurality of reference voltages. A display device using the drive circuit of the display device according to any one of claims 1 to 3. 5. A mixed output at the time of voltage division selection and at the time of single selection, wherein a period for independently selecting a reference voltage by the reference voltage supply control means (2) and a period for selecting a plurality of reference voltages are different from each other. 4. A display method using a drive circuit of a display device according to claim 1, which realizes multi-gradation output while reducing voltage fluctuations at the time.