JPH07250118A - Carrier recovery circuit - Google Patents

Abstract

PURPOSE:To obtain a carrier recovery circuit which can expand a carrier acquisition range with small-scale constitution as to a carrier recovery circuit used for the demodulator of a digital signal communication system using a phase modulation system such as BPSK and QPSK. CONSTITUTION:A feedback loop consists of a computing element 12, a phase detection circuit 14, a loop filter 15, a voltage-controlled oscillator 16, and a ROM table 13. The output phase error signal of the phase detection circuit 14 is inputted to a comparator 19 through a squaring computing element 17 and a low-pass filter 18 and at the time of 1st artificial synchronization, the outputs of the delay unit 154 in the loop filter 15, the delay unit 162 in a VCO 16, and the delay unit 183 in the low-pass filter 18 are controlled to 0 with the output signal of the comparator 19. Further, a limiter 155 is provided in the loop filter 15 and at the time of 2nd artificial synchronization, 0 is outputted if an input value exceeds the limiter value to reset the circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier recovery circuit,
In particular, the present invention relates to a carrier recovery circuit used for a demodulator of a phase modulation type digital signal communication system such as BPSK or QPSK.

[0002]

2. Description of the Related Art In the case of transmitting a digital signal, the transmitting side uses a baseband digital signal as a modulation signal and modulates a carrier with a predetermined modulation method among various modulation methods to generate a modulated wave and transmit the modulated wave. Output to the system. On the receiving side, a demodulator performs carrier wave recovery and clock recovery on the modulated wave received through this transmission system, and the transmitted baseband digital signal is reproduced as a demodulated signal.

As a modulation method used in such a digital signal communication system, BPSK (Bina) is used.
ry Phase Shift Keying method and QPSK (Quadrature Phase Shii)
Phase modulation methods such as the ft Keying method are known. As one of carrier recovery circuits used in a demodulator of a digital signal communication system using this phase modulation method, there is one that performs carrier synchronization by a Costas loop.

In this carrier recovery circuit, the received modulated wave and the output oscillation frequency of the voltage controlled oscillator are phase-compared by a phase comparator, and their phase error signals are supplied to the above voltage controlled oscillator via the loop filter. By inputting as, a phase locked loop (PLL) for controlling the output oscillation frequency of the voltage controlled oscillator according to the average value of the phase error signal is formed. But,
In this carrier recovery circuit, f _C ± {1 / (2n)} × R (where n is a natural number of 1 or more, f _C is carrier frequency [Hz], and R is transmission rate [Hz]) is pseudo-synchronized That is, it is generally known that a phenomenon may occur in which the voltage-controlled oscillator oscillates at a frequency different from the carrier frequency.

Specifically, for example, a transmission rate of 64 kHz
In the case of the QPSK method, f _C ± 8 kHz (R = 64, n
= 4) is a frequency that may cause pseudo synchronization, and the signal points of the reproduction data of the in-phase component and the quadrature component at this time are as shown in FIG.
Where there should be four signal points, four more signal points occur.

At this time, the carrier offset amount is -5.5.
In the case of kHz, when the voltage-controlled oscillator corrects −5.5 kHz, the carrier recovery circuit comes into a state of being correctly synchronized with the carrier frequency f _C of the received modulated wave ((−5.5) −
(-5.5) = 0). However, for example, when +2.5 kHz is corrected in the opposite direction to the offset in the above case, the carrier regeneration circuit causes the carrier frequency f _C of the received modulated wave to be −8 kHz (= (− 5.5) − (+ 2.5 )) Pseudo-synchronization with distant frequencies occurs, and the signal points of the reproduction data are those shown in FIG.

Therefore, in order to prevent such pseudo-synchronization, conventionally, there have been proposed various methods such as a method of limiting the carrier wave capturing range to some extent (Japanese Patent Laid-Open No. 4-2705).
07, JP-A-3-177112, JP-A-2-246.
No. 519, etc.). For example, JP-A-4-27050
In the conventional circuit described in Japanese Patent Publication No. 7, when the pseudo-synchronized state is reached, the loop is temporarily removed, the voltage-controlled oscillator is controlled to generate a frequency equal to the normal carrier frequency in the voltage-controlled oscillator, and then the loop pull-in operation is performed. It was designed to start.

Further, in the conventional circuit disclosed in Japanese Patent Laid-Open No. 3-177112, in a PLL circuit having a phase comparator for comparing the phases of received data and received clock, pseudo synchronization is performed based on the frequency comparison result of the received clock and the transmitted clock. When the state is detected and the pseudo-synchronous state is reached, the operation of the phase comparator is interrupted, and the low-pass filter in the PLL circuit,
A voltage-controlled oscillator or the like is driven to perform control so that the frequencies of the reception clock and the transmission clock are close to each other.

Further, in the conventional circuit disclosed in Japanese Patent Laid-Open No. 2-246519, a disturbance signal is added to the phase-locked loop when a pseudo-synchronized state is detected so that the false-synchronized state is released. is there.

[0010]

However, in the conventional circuit for limiting the carrier capturing range, the loop bandwidth of the phase locked loop must be narrowed, so that the received modulated wave is phased over a wide frequency range. I can't sync. Further, in the conventional circuit, for example, the coordinate plane of the signal point constellation diagram is divided into small areas, and when reproduction data exists in an inappropriate area, it is regarded as abnormal and pseudo synchronization is detected. However, it is difficult to detect pseudo-synchronization when there are many noise components, and the configuration such as area division is not easy. It is reliable in a small-scale configuration and with a low energy-to-noise power density ratio (Eb / No) per bit. However, there is a problem in that pseudo synchronization cannot be prevented. Further, in each of the conventional circuits described in the above publications, the phase error information is almost zero.
No consideration was given to the prevention of pseudo synchronization that would be indistinguishable from the normal pull-in state.

The present invention has been made in view of the above points,
With a small-scale configuration, the carrier capture range can be expanded compared to the past,
An object of the present invention is to provide a carrier recovery circuit capable of preventing various types of pseudo synchronization.

[0012]

In order to achieve the above object, the present invention provides phase rotation control means for performing phase rotation control on demodulated data of a modulated wave modulated by a phase modulation method to synchronize a carrier wave. A phase detection circuit for detecting phase error information of the first and second reproduction data extracted from the phase rotation control means, a loop filter for integrating output phase error information of the phase detection circuit, and an output signal of the loop filter. The output oscillation frequency is variably controlled, and has a voltage controlled oscillator that supplies the output oscillation frequency to the phase rotation control means as phase correction information, and in a feedback path of at least one of the loop filter and the voltage controlled oscillator, The configuration is such that a limiter is provided for setting the reset state when the input value reaches the limiter value.

Further, it is preferable that the limiter value of the limiter is set to a value in the synchronous pull-in state at the target value of the carrier wave capturing range in order not to narrow the carrier wave capturing range.

Further, according to the present invention, the calculating means for calculating the absolute value of the output phase error information of the phase detecting circuit, the filter circuit for integrating the output value of the calculating means, and the output value of the filter circuit are preset. A level comparison is performed with a threshold value, and when the output value exceeds the threshold value, the filter circuit, the loop filter, and the voltage control oscillator are each in a reset state.

When the output value of the filter circuit exceeds the threshold value, the comparator outputs the output of a one-sample delay device provided in each feedback path of the loop filter, the voltage controlled oscillator and the filter circuit. Controlling the value to 0 is preferable because the filter circuit, the loop filter, and the voltage-controlled oscillator can be surely reset.

[0016]

According to the present invention, since the limiter for resetting the input value when the input value reaches the limiter value is provided in the feedback path of at least one of the loop filter and the voltage controlled oscillator, the limiter in the synchronous pull-in state is provided. When the input value of 1 reaches the limiter value, the loop filter and / or the voltage controlled oscillator provided with the limiter are reset, and the carrier recovery circuit restarts the synchronous pull-in operation from the beginning.

Further, according to the present invention, when the output value of the filter circuit exceeds the threshold value by the comparator, the filter circuit, the loop filter and the voltage controlled oscillator are reset, respectively. When the pseudo sync state exceeds the threshold value, the carrier recovery circuit restarts the sync pull-in operation from the beginning.

[0018]

EXAMPLES Next, examples of the present invention will be described. FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure,
The input terminals 11a and 11b have a phase modulation method (here, QP
Demodulated data of a reception modulated wave of the SK system) is input. The arithmetic unit 12 includes input demodulated data at the input terminals 11a and 11b and a read only memory (ROM) table 13.
121a, 121 for performing multiplication with the data from
b, 122a, 122b, subtractor 123 and adder 12
4 and constitutes the phase rotation control means together with the ROM table 13.

The output terminal of the arithmetic unit 12 has output terminals 20a, 2
On the other hand, it is connected to the arithmetic unit 12 via the phase detection circuit 14, the loop filter 15, the voltage controlled oscillator (VCO) 16 and the ROM table 13 while being connected to 0b.

The loop filter 15 includes multipliers 151 and 152 for multiplying the output phase error signal of the phase detection circuit 14 and the multiplication coefficients α and β, and adders 153 and 153 to which the output signal of the multiplier 151 is input. It comprises a delay device 154 for delaying the output signal by one sample and a limiter 155 to which the output signal of the delay device 154 is input. Further, the VCO 16 is configured to feed back the output of the adder 161 to the adder 161 via the one-sample delay device 162.

The limiter 155 outputs the input signal as it is when the input signal is below the limiter value, and when the input signal becomes larger than the limiter value, the initial value (minimum level).
The limiter value of the delay unit 154 when the absolute value (unit: Hz) of the correction amount of the circuit from the input terminals 11a and 11b to the output terminals 20a and 20b of the circuit of this embodiment becomes a predetermined value. It is set to the output level.

In this embodiment, the output phase error signal of the phase detection circuit 14 is fed to this feedback loop by the squaring unit 1
7 and the low-pass filter 18 and inputs to the comparator 19, and the output signal of the comparator 19 controls the delay device 154 in the loop filter 15, the delay device 162 in the VCO 16, and the delay device 183 in the low-pass filter 18. It is said that.

The low-pass filter 18 multiplies the output signal of the square calculator 17 by the multiplication coefficient η, the adder 182 to which the output signal of the multiplier 181 is input, and the output signal of the adder 182 to 1 Sample delay device 18
3. A multiplier 184 that multiplies the output signal of the delay unit 183 by the multiplication coefficient and inputs the multiplication result to the adder 182. Further, the comparator 19 compares and detects whether the output signal of the low-pass filter 18 is larger than a predetermined threshold value, and when it is larger than the threshold value, the delay device 154,
Reset 162 and 183 respectively.

Next, the operation of this embodiment will be described with reference to FIGS. The demodulated data of the in-phase component of the reception modulated wave of the QPSK method input via the input terminal 11a is input to the multipliers 121a and 122a, where R
The demodulated data of the quadrature component multiplied by the rotation angle information of sin θ and cos θ from the OM table 13 and input through the input terminal 11b are multipliers 121b and 122b.
Input from the ROM table 13
It is multiplied by the rotation angle information of θ and cos θ.

The output signals of the multipliers 122a and 121b are added by the adder 124 and output as reproduction data P of the in-phase component. On the other hand, the output signals of the multipliers 121a and 122b are respectively input to the subtractor 123 and output as the reproduction data Q of the orthogonal component. That is, the input demodulated data at the input terminals 11a and 11b are controlled in phase rotation by the arithmetic unit 12 according to the rotation angle information from the ROM table 13 and are synchronized with the carrier wave.

The reproduced data P and Q are output from the output terminal 20.
While being output to a and 20b, it is input to the phase detection circuit 14. When the carrier waves are not synchronized with the reproduced data P and Q (during the pull-in process), a circle is drawn as shown in FIG. On the other hand, when the carrier wave synchronization is correctly performed, the reproduction data P and Q converge on any of the four signal points as shown in FIG.

The rotation angle control information of the arithmetic unit 12 is usually obtained based on the phase error signal obtained by the phase detection circuit 14 based on the reproduction data P and Q. The rotation angle control information θ of the arithmetic unit 12 may be calculated by calculating tan ⁻¹ (Q / P) based on the reproduction data P and Q, but it is generally a DSP (digital signal processor) or the like. When configured, there are many cases where division operation cannot be performed.
In addition, it is necessary to consider the process when P≈0. For this reason, in many cases, the phase error information θ is simply obtained from the reproduction values of the reproduction data P and Q as described below.

Θ = -sgn (P) .sgn (Q). (|
Q |-| P | (where sgn (A) is the sign of A and | A | is the absolute value of A.) When the normalization level of the reproduction data is "1" (reproduction data is X- When the Y display is performed, the reproduction data exists on the unit circle. For example, when the signal point of the reproduction data is shifted by 45 ° from the normal time of FIG. 2B, the signal point is the first in FIG. 2B. When in the quadrant, P = cos0 = 1, Q = sin0
= 0, and similarly, when the signal point is in another quadrant, θ = 1. When the signal point is in the quadrant 1 of FIG. 2B when the signal is deviated by −30 °, P = cos1
At 5 ° and Q = sin 15 °, θ≈0.37, and similarly when the signal point is in another quadrant, θ≈0.37.
Is.

The phase error θ of the reproduced data of the BPSK system is approximately given by the following equation θ = -sgn (P) · Q.

This phase error information (phase error signal) θ is integrated by the loop filter 15 and then input to the VCO 16 where it is used as the carrier phase correction information. Calculator 1
The rotation angle (correction amount) of the phase rotation operation performed in 2 is given by the ROM table 13 as described above. This ROM table 13 is stored with a value of sin θ (or cos θ) at a certain step size (for example, at intervals of 0.5 °), and based on the phase error information that has passed through the loop filter 15 and has been input to the VCO 16 as a control voltage. Yes, VCO16
Of the output phase rotation angle is received as address information, the rotation angle information of (sin θ, cos θ) is taken out and input to the calculator 12, and the carrier frequency is corrected (pulled in) by the phase rotation operation by the calculator 12. Let

Now, regarding pseudo-synchronization, this can be classified into two types. One is a type in which the phase error information θ becomes almost 0 (hereinafter, referred to as type A), and the other is a type in which the phase error information θ does not become almost 0 but is balanced (this is Hereinafter, it is referred to as type B).

First, type A will be described. For example, in the case of the BPSK system, f _C ± (1/2) × R (where n is a natural number of 1 or more, f _C is a carrier frequency [Hz], and R is a transmission). Rate [Hz]), and in the case of the QPSK method, f _C ± (1/2) × R or f _C ± (1/4) × R.

When the signal points of the reproduction data output to the output terminals 20a and 20b in the type A pseudo-synchronous state are displayed in XY, the BPSK method is shown in FIG.
In the QPSK method, as shown in FIG.
As in the signal point arrangement diagram in the normal synchronization state shown in (B), since the phase error information is 0, it cannot be distinguished from the normal pull-in state.

As a concrete example, for example, the transmission rate is 64k.
In the case of the QPSK system of Hz, the carrier offset amount is −
F at 8.5 kHz, when corrected at +7.5 kHz
_C- 16 kHz (= f _C − (1/4) × 64 [kHz
z]). At this time, the signal points of the reproduced data are arranged as shown in FIG. 3 (B), which is seemingly indistinguishable from the normal synchronization state, but the reproduced data alternately undergoes phase inversion (π), resulting in an error state. Becomes

As means for avoiding this pseudo synchronization state,
In the present embodiment, as shown in FIG. 1, a limiter 155 is provided in the feedback path from the delay device 154 of the loop filter 15 to the adder 153, and when the output signal of the delay device 154 exceeds the limiter value of the limiter 155. Both values are reset (substitution of the initial offset value 0), and the re-pull-in operation is repeated until the normal synchronization state is achieved. The limiter value of the limiter 155 seems to be (1/8) × R in the case of the QPSK method as described later (in the case of the BPSK method,
(1/4) × R).

When the limiter 155 is provided, the carrier capturing range (capture range) of the carrier regenerating circuit is limited to the limiter value or less. Normally, the value of the carrier capturing range in the PLL method is the QPSK method. In this case, since the target value is about (1/8) × R (12.5% of the transmission rate), provision of the limiter 155 does not restrict the carrier capture range. Conceivable. By the way, the target value of the carrier capturing range of the BPSK system is about (1/4) × R (2 of the transmission rate).
0%), and similarly, it is considered that the carrier acquisition range is not restricted.

Specifically, the transmission rate is 64 kHz.
In the case of the QPSK system of z, the carrier offset amount is +7.
When the frequency is 5 kHz and the +7.5 kHz correction works, the normal synchronization pull-in state occurs, but in the conventional case, the above-mentioned case is used.
When corrected to 8.5 kHz, f _C +16 kHz (= f
There was a possibility that a pseudo pull-in state would occur with _C + (1/4) × R).

Here, in this embodiment, the limiter value (absolute value) of the limiter 155 is set to 8 kHz (= (1/8) × 64).
[KHz]), so when the -8.5 kHz correction is about to work, the correction amount changes from 0 to the limiter value of -8 kHz.
When the frequency reaches Hz, the output of the limiter 155 becomes the initial value 0, that is, the reset state. Therefore, in this embodiment, the synchronization pull-in is started again. In this way, in the present embodiment, by setting the limiter 155, the correction amount is reset every time the limiter value is reached and the re-pull-in start is repeated, so that the normal synchronization state is finally reached, and therefore the QPSK method is used. Case f _C ± (1/2) × R, f _C ±
(1/4) × R (in case of BPSK method f _C ± (1/2)
It is possible to prevent type A pseudo synchronization with respect to (XR).

In the above example, when the carrier offset amount is, for example, +10 kHz, there is a possibility that pseudo synchronization will occur at f _C +16 kHz (= f _C + (1/4) × R) when the correction of -6 kHz works. However, the value of the carrier offset amount +10 kHz is a value outside the carrier acquisition range, and the offset amount continuously changes,
When the offset amount changes within +8 kHz (+10 kHz
Hz → + 8 kHz → ...), the correction amount is 16 kHz (=
Since + (1/4) × R) is maintained and changes following, the offset amount becomes +8 kHz of the limiter value (-6
It becomes impossible to follow up at (kHz → -8 kHz), and the reset operation is performed.

Therefore, in the present embodiment, the pull-in operation is performed again when the carrier offset amount within the carrier capture range is reached, and the pull-in operation is repeated until the normal synchronization state is achieved.

Next, the type B pseudo synchronization will be described. In the case of the BPSK system, this is when f _C ± (1/2 m) × R (where m is a natural number of 2 or more, f _C is the carrier frequency [Hz], and R is the transmission rate [Hz]) is pseudo-synchronized. Yes, and in the case of the QPSK method, it is a case of pseudo synchronization with f _C ± (1 / 2k) × R (where k is a natural number of 3 or more).

When the signal points of the reproduced data output to the output terminals 20a and 20b in the type B pseudo-synchronous state are displayed in XY, the BPSK method is shown in FIG.
In the QPSK method, as shown in FIG. 6B, more signal points are displayed than the signal points in the normal synchronization state. At this time, the output phase error information of the phase detection circuit 14 has the same absolute value and the control directions are alternately repeated,
As a result, the output oscillation frequency of the VCO 16 does not take a correct value, and there is a phenomenon in which it vibrates slightly in the vicinity of a different value and stabilizes in this pseudo-synchronized state.

Explaining a specific example, for example, in the case of the QPSK system with a transmission rate of 64 kHz, when the carrier offset amount is -3.5 kHz, when corrected by +4.5 kHz, f _C -8 kHz (= f _C- (1 / 8) x 64
[KHz]) is pseudo-synchronized.

In order to avoid this type B pseudo-synchronous state, in the present embodiment, the squaring unit 17, the low-pass filter 18 and the comparator 19 of FIG. 1 are provided. As a result, the output phase error signal of the phase detection circuit 14 is squared by the square calculator 17 (or the absolute value is obtained), and this squared value is multiplied by the multiplication coefficient η in the multiplier 181 in the low-pass filter 18. After that, the output of the multiplier 184 is added and output by the adder 182, and is also supplied to the multiplier 184 via the delay unit 183 and is multiplied by the multiplication coefficient (1−η).

The adder 18 in the low-pass filter 18
The output signal extracted from 2 has a value of almost 0 when the carrier is properly pulled in, but has a certain value when the pseudo synchronization occurs. Therefore, a threshold value is set in consideration of the influence of noise, and the comparator 19 compares and detects whether or not the output signal of the adder 182 exceeds this threshold value. When it exceeds the threshold value, the delay devices 154, 162 and 1
These are reset and controlled so that the respective output values of 83 become 0.

When the output frequency component value of the delay device 154, the output voltage controlled oscillator of the delay device 162, and the output sum of squares integrated value of the delay device 183 are reset to 0, the circuit of the embodiment starts the pull-in operation again. To do. In this way, the above-described pull-in restart control is repeated until the normal pull-in state is achieved.

When the carrier component does not exist, the reproduced data takes a random value but a small value, so that the output value of the low-pass filter 18 does not exceed the threshold value of the comparator 19 and the carrier is pulled in. (Signal points are shown in Figure 2
Even in the state (A), the output value of the low pass filter 18 does not exceed the threshold value of the comparator 19 by the low pass filter 18.

To explain this in more detail,
The carrier wave pull-in state as shown in FIG. 2A is a synchronous pull-in process, and a signal (carrier wave) is normally input.
The time required to settle into the normal synchronization state of the signal point arrangement shown in (B) is at most 100 × R to 200 × R.
(However, R is a transmission rate [Hz]), that is, it is considered to be 100 to 200 symbols. Therefore, the time constant of the low-pass filter 18 in FIG. 1 is increased (specifically, the multiplication coefficient η of the multiplier 23 is decreased). As a result, the output value of the low-pass filter 18 is set to the value shown in FIG.
It can be avoided that the threshold value of the comparator 19 is exceeded and the comparator 19 is reset.

Even if the time constant is increased, as shown in FIG.
Even if the signal point arrangement state shown in (B) exceeds the threshold value of the comparator 19 only after several thousand to 10,000 symbols continue, it is considered to be within one second, so there is no problem.

On the other hand, when the carrier wave pull-in state shown in FIG. 2A continues for about 100 × R to 200 × R or more,
It is considered that the threshold value of the comparator 19 is exceeded, but it takes an abnormally long time to pull in when a carrier having an offset outside the carrier capture range is input or V
It is considered that the CO 16 does not follow the normal frequency direction, and there is no problem with resetting, and it is desirable that resetting is performed.

In this way, when the steady state is not reached, the output value of the low-pass filter 18 exceeds the threshold value of the comparator 19 for the first time, and the output frequency component value of the delay device 154 and the delay device 162 are not reached. Of the output voltage controlled oscillator and the output square sum integrated value of the delay device 183 are reset to 0.

As described above, according to this embodiment, by providing the limiter 155, the type A pseudo-synchronous state can be prevented, and the squaring unit 17, the low-pass filter 18 and the comparator 19 are provided. As a result, the type B pseudo-synchronous state can be prevented. Further, in this embodiment,
It is not necessary to recognize in which area or in which quadrant the reproduced data exists on the XY coordinate plane (on the signal point arrangement diagram), and the pseudo-synchronous state can be easily determined by applying the condition of the reproduced data to the above formula. Moreover, the influence of noise can be reduced by the low-pass filter 18 having a large time constant.

The present invention is not limited to the above embodiment, and instead of the limiter 155 or together with the limiter 155, the delay device 162 in the VCO 16 is provided.
Therefore, a limiter 163 having the same characteristics as the limiter 155 may be provided in the feedback path of the adder 161.

Further, the present invention is not limited to the QPSK system or the BPSK system described above, and the formula for phase error detection may be slightly applied to demodulation data of other phase modulation systems such as offset QPSK or π / 4 shift QPSK. It goes without saying that the present invention can be applied in the same manner only by making changes. Furthermore, in the above embodiment, means for preventing the two types of pseudo-synchronization are provided, but in the case where the probability of occurrence of one type of pseudo-synchronization is considerably low,
Only means for preventing the other type of pseudo sync may be provided.

[0055]

As described above, according to the present invention,
When the input value of the limiter reaches the limiter value in the synchronous pull-in state, the loop filter and / or the voltage-controlled oscillator in which the limiter is provided are reset, so that the carrier wave recovery circuit restarts the synchronous pull-in operation from the beginning. Therefore, in the pseudo-synchronous state in which the input value of the limiter reaches the limiter value, the re-pull-in operation is repeated, and finally the normal synchronous state can be obtained.

Further, according to the present invention, when the output value of the filter circuit exceeds the threshold value of the comparator in the pseudo synchronization state, the carrier recovery circuit restarts the synchronization pull-in operation from the beginning by the output of the comparator. Therefore, even when the output value of the filter circuit exceeds the threshold value of the comparator in the pseudo-synchronous state, the re-pull-in operation is repeated, and finally the normal synchronous state can be obtained. .

Therefore, according to the present invention, the band of the loop filter can be expanded more than before without concern about pseudo-synchronization, so that the carrier capture range can be expanded more than before. Further, according to the present invention, since it is not necessary to recognize which region and in which quadrant the signal point of the reproduction data exists in the signal point arrangement diagram, it is possible to realize with a simple configuration and, on the other hand, a fine area. Since it is not necessary to consider separately, it is possible to reliably detect the pseudo synchronization without being significantly affected by noise, and thus it is possible to improve the reliability of preventing the pseudo synchronization.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

[Fig. 2] QP during synchronization pull-in and in synchronization pull-in state
It is an XY display figure of the reproduction data of a SK system.

FIG. 3 is an XY display diagram of an example of reproduction data at the time of pseudo synchronization.

FIG. 4 is an XY display diagram of another example of reproduction data during pseudo synchronization.

FIG. 5 is an XY display diagram of an example of reproduction data of the QPSK system during pseudo synchronization.

[Explanation of symbols]

 11a, 11b input terminal 12 arithmetic unit 13 ROM (read only memory) table 14 phase detection circuit 15 loop filter 16 voltage controlled oscillator (VCO) 17 square calculator 18 low-pass filter 19 comparator 154, 162, 183 1 sample Delay device 155,163 limiter

Claims (6)

[Claims] 1. A phase rotation control means for performing phase rotation control on the demodulated data of a modulated wave modulated by a phase modulation method to synchronize a carrier wave, and first and second phases extracted from the phase rotation control means. Phase detection circuit for detecting the phase error information of the reproduced data of, the loop filter for integrating the output phase error information of the phase detection circuit, and the output oscillation frequency is variably controlled by the output signal of the loop filter, and the output A voltage controlled oscillator that supplies an oscillation frequency to the phase rotation control means as phase correction information, and an input value has reached a limiter value in a feedback path of at least one of the loop filter and the voltage controlled oscillator. A carrier wave regenerating circuit characterized in that a limiter is provided for sometimes resetting. 2. The carrier regenerating circuit according to claim 1, wherein the limiter value of the limiter is set to a value in a synchronous pull-in state at a target value of a carrier wave capturing range. 3. A phase rotation control means for performing phase rotation control on the demodulated data of a modulated wave modulated by the phase modulation method to synchronize a carrier wave, and first and second phases extracted from the phase rotation control means. Phase detection circuit for detecting the phase error information of the reproduced data of, the loop filter for integrating the output phase error information of the phase detection circuit, and the output oscillation frequency is variably controlled by the output signal of the loop filter, and the output A voltage controlled oscillator that supplies an oscillation frequency to the phase rotation control means as phase correction information, a calculation means that calculates the absolute value of the output phase error information of the phase detection circuit, and a filter circuit that integrates the output value of the calculation means. And comparing the output value of the filter circuit with a preset threshold value, and when the output value exceeds the threshold value, the filter circuit and the loop filter are compared. A carrier recovery circuit having a comparator for setting a filter and a voltage controlled oscillator to a reset state. 4. A limiter for setting a reset state when an input value reaches a limiter value is provided in a feedback path of at least one of the loop filter and the voltage controlled oscillator. The carrier recovery circuit described. 5. The one-sample delay device provided in each feedback path of the loop filter, the voltage-controlled oscillator, and the filter circuit when the output value of the filter circuit exceeds the threshold value. 5. The carrier recovery circuit according to claim 3, wherein the output value of the carrier wave is controlled so as to be zero. 6. The carrier recovery circuit according to claim 4, wherein the limiter value of the limiter is set to a value in a synchronous pull-in state at a target value of a carrier wave capturing range.