JPH07249777A - Space charge limiting current element and its fabrication - Google Patents

Abstract

PURPOSE:To realize a SCLC element providing high picture quality for liquid crystal display while reducing power consumption and its fabrication. CONSTITUTION:The inventive current element comprises a gate insulating film 14 deposited on a translucent substrate 10, a first insular conductive a-Si layer 16a formed on the gate insulating film, and second conductive a-Si layers 18c, 18d touching the first a-Si layer. An insular shading film 12a for preventing the transmitted light from impinging on the first and second a-Si layers is also deposited on the substrate. The shading film is formed larger than the first and second a-Si layers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a space charge limited current device and a manufacturing method thereof, and more particularly to a space charge limited current device used in an active matrix liquid crystal display and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, an active matrix liquid crystal display which directly drives a liquid crystal for switching by using a thin film transistor array in which switching elements are arranged in a matrix has attracted attention. In addition, this thin film transistor (Thin Film Transistor:
A liquid crystal display using an array (hereinafter referred to as a TFT) is formed by forming a TFT array on a glass substrate or a ceramic substrate and sequentially laminating a liquid crystal layer and a glass plate provided with a transparent electrode (Reference I: "Latest Liquid Crystal Technology", Shoichi Matsumoto et al., Published by Industrial Research Board, 1984, P
P. 113-115). As a method of preventing static electricity generated during the manufacturing process of an active matrix liquid crystal display, an example in which a short ring is provided is disclosed in, for example, JP-A-59-16698 (hereinafter referred to as Document II). . Next, the liquid crystal display element disclosed in Document II will be briefly described.

The TFT array is arranged on a transparent substrate such that a plurality of address wirings and data wirings intersect each other in the row direction and the column direction. The gate electrode of the TFT is connected to the address wiring and the data wiring, and the drain electrode of the TFT and the data wiring are connected to each other. On the other hand, the source electrode of the TFT is connected to the display electrode. Further, a short ring is formed on the upper peripheral portion of the transparent substrate so as to surround the substrate, and the data wiring and the address wiring are connected to the short ring. As a result, static electricity is generated during the TFT manufacturing process,
Even if there is a high potential between the gate and drain electrodes of
The short ring causes a short circuit, and the potential between the address wiring and the data wiring becomes equal. Therefore, discharge due to static electricity between the gate electrode and the drain electrode of the TFT can be suppressed, and the dielectric breakdown or short circuit defect of the TFT can be reduced.

[0004]

However, the active matrix liquid crystal display disclosed in the above-mentioned conventional document II has a problem in that the TFT is not manufactured during the manufacturing process.
After joining the array and the substrate via the sealing material, the short ring is cut and removed along the cutting line, so static electricity is generated during the manufacturing process such as attaching the polarizing plate in the subsequent process and connecting the drive circuit. Then, there is a problem that the image on the liquid crystal display is deteriorated and the yield is lowered.

In order to solve this problem, the inventors of the present application repeated various trials and conducted experiments, and as a result, provided short-circuit wiring as a short ring on the upper peripheral edge of the transparent substrate. , The address wiring and the shorting wiring are space charge limited current elements (hereinafter referred to as SCLC elements).
And connect the data line and the short-circuit line with S
It has been found that the connection via the CLC element can prevent deterioration of the image (or image quality) of the liquid crystal display due to static electricity. The reason for this will be described below.

The two-terminal element (SCLC element) has a non-linear voltage-current characteristic, and the resistance of the SCLC element is sufficiently high at a driving voltage for performing normal liquid crystal display. However, when each component is mounted and static electricity is generated, and a high voltage is applied between the electrodes of the SCLC element, a large current flows through the SCLC element, and the address wiring and the data wiring are substantially short-circuited. Can be in a state. Therefore, the potential between the address wiring and the data wiring becomes equal, and the deterioration of the image quality of the liquid crystal display due to static electricity can be prevented (details will be described later).

However, according to this SCLC element, after mounting each component on the translucent substrate by, for example, attaching a polarizing plate or connecting a driving circuit, the backlight is irradiated to form the TFT array. When trying to drive,
Since the backlight is also applied to the SCLC element, photocurrent is also excited in the SCLC element, and a leak current flows. Therefore, the T connected to the address line
TFT connected to the gate electrode side of FT and the data line
A new problem arises that the resistance between the drain electrode sides of the liquid crystal display device is reduced, the image quality of the liquid crystal display is deteriorated (for example, the display color is uneven, the contrast is insufficient), or the power consumption is increased. Such a problem becomes more remarkable as a liquid crystal display has a larger area, a larger capacity, or a higher definition.

Therefore, an excellent SCLC protection device which improves the image quality of a liquid crystal display and has a small increase in power consumption, and a manufacturing method thereof have been desired.

[0009]

In order to solve the above-mentioned problems, the space charge limited current element (SCLC element) of the present invention.
Provides a gate insulating film on a light-transmitting substrate, has an island shape on the gate electrode insulating film, and contacts the conductive first amorphous silicon (a-Si) layer and the first amorphous silicon layer. Is provided with a conductive second amorphous silicon (a-Si) layer, and an island-shaped light-shielding film is provided to prevent light transmitted through the substrate from entering the first and second amorphous silicon layers. The light-shielding film is provided on the substrate and is larger than the outer circumferences of the island-shaped first and second amorphous silicon layers so that the amorphous silicon layers serve as a shade of incident external light.

According to the method of manufacturing an SCLC device of the present invention, first, a conductor layer for forming a gate electrode and a light-shielding film is formed on a transparent substrate, and then a conductive layer is formed by photolithography. The body layer is patterned into a predetermined shape to form island-shaped gate electrodes and light-shielding films which are separated from each other on the substrate. After that, the gate electrode and the light shielding film are filled with a gate insulating film. Further, a conductive first amorphous silicon forming layer and a conductive second amorphous silicon forming layer are sequentially formed on the gate insulating film. Then, the first and second amorphous silicon forming layers are etched to face the gate electrode and the light shielding film to form island-shaped first and second amorphous silicon layers, respectively.

[0011]

The present invention described above is based on the space charge limited current (SC
A light-shielding film is provided in the (LC) element. The light-shielding film is provided on the translucent substrate so as to be larger than the outer circumferences of the first and second amorphous silicon layers. Therefore, when the backlight is irradiated from the rear surface side of the translucent substrate, the light transmitted through the substrate is blocked by the light shielding film, so that the backlight is incident on the first and second amorphous silicon layers. Therefore, it is possible to suppress the leak current generated in the SCLC element due to the excitation of the photocurrent.

Further, when manufacturing an SCLC device, a thin film transistor (TFT) device can be simultaneously formed on a light-transmissive substrate, so that the S manufacturing process can be performed without increasing the number of conventional manufacturing processes.
Since the CLC element can be manufactured, the reliability and productivity of the liquid crystal display are improved.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A space charge limited current (SCLC) device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings by taking an active matrix liquid crystal display as an example. It should be noted that each drawing merely schematically shows the shape, size and arrangement of each constituent component to the extent that the present invention can be understood. Further, the embodiments described below are merely preferable examples, and therefore, the present invention is not limited to these embodiments.

Before explaining the structure of the SCLC device,
First, the overall configuration of the active matrix liquid crystal display will be briefly described with reference to FIG.

Address wirings 13 (G _{1 to} G _i, but G _{1 to} G ₄ are shown in FIG. 4) and data wirings 22 (D _{1 to} D) are formed on a transparent substrate (not shown). _j However, in FIG. 4, D _{1 to} D ₄ are shown) arranged in a matrix. Short-circuit wirings 20a and 20b are provided around the address wiring 13 and the data wiring 22.
The short circuit wirings 20a and 20b form a short ring.

The address wiring 13 side is connected to the gate electrode side of the thin film transistor (hereinafter referred to as TFT) 34, while the data wiring 22 side is connected to the TFT 34.
Is connected to the drain electrode side.

The source electrode side of the TFT 34 is connected to the capacitor 36 and the liquid crystal 38 which are connected in parallel. Further, one pixel 40 of the liquid crystal display is defined by the TFT 34, the capacitor 36, and the liquid crystal 38.

Further, two-terminal elements (hereinafter referred to as SCLC elements) 17 (A _G1 to
A _G4 ) is the address wiring 1 on the side of one connecting electrode 17a.
3 side, and the other connection electrode 17b side is connected to the short circuit wiring 20b.

Further, S arranged on the data wiring 22 side
The CLC element 17 (A _{D1 to} A _D3 ) has one connection electrode 1
The 7c side is connected to the data wiring 22 side, and the other connecting electrode 17d side is connected to the shorting wiring 20a side.

Next, the structure of the SCLC device of the present invention will be described with reference to FIGS. 1, 2 and 3. 1 and 2 are arranged in parallel with the short circuit wiring 20a of FIG.
The principal sectional drawing when it cut | disconnects along the XX line of a CLC element is shown.

[1] Structure of SCLC element FIG. 3 is a schematic view showing a part of a typical element constituting the SCLC element 17 of FIG. 4 described above.
FIG. This element portion is the portion of the SCLC element 17 (A _D1 ) connected to the data line 22 (D ₁ line) and the short-circuit line 20a, in the example of the active matrix liquid crystal display shown in FIG. .

A plurality of data wirings 22 are arranged in the column direction on the upper peripheral portion of the SCLC element 17 on the substrate 10, and a short-circuiting wiring 20a is arranged in a direction orthogonal to the data wirings 22. ing. The shorting wiring 2 is provided at the intersection of the data wiring 22 and the shorting wiring 20a.
An intersection insulating film 24 is provided to insulate the data line 22 from the data line 22a. Then, of the second amorphous silicon layer 18 formed on the upper surface of the SCLC element 17, one portion 18a side is connected to the connecting electrode 19a and the other portion 18b side is connected to the connecting electrode 19b. The connecting electrode 19a is connected to the short-circuit wiring 20a.
On the other hand, the connection electrode 19b is connected to the data wiring 2
2 (see FIG. 4).

Next, S is cut along the line X--X in FIG.
The cross-section cuts of the CLC element 17 are schematically shown in FIG. 1 and FIG. In order to make the drawings easy to understand, hatching lines are omitted in the cross-sectional portion of each layer except the light shielding film.

FIG. 1 shows the upper surface of the substrate 10 and the gate insulating film 1.
4 shows an example in which the light shielding film 12a is provided between the substrate 10 and the substrate 4, while FIG. 2 shows an example in which the light shielding film 12a is provided on the back surface side of the substrate 10.

First, as the translucent substrate 10, a glass substrate (for example, Corning 7057 manufactured by Corning Incorporated) is used. A gate insulating film 14 is provided on this substrate 10.
The material of the gate insulating film 14 is, for example, a silicon nitride film. At this time, before forming the gate insulating film 14, an island-shaped light shielding film 12a may be provided on the substrate 10 in advance in order to prevent the light from entering the first and second amorphous layers (FIG. 1).

On the gate insulating film 14, an island-shaped, first conductive amorphous layer 16a is provided. This first amorphous silicon (a-Si) layer 16a is a first conductivity type amorphous silicon layer (hereinafter, referred to as
n ⁻ type a-Si layer).

Further, conductive second amorphous silicon (a-Si) layers 18c and 18d are provided on the n ^-- type a-Si layer 16a. A material of the second a-Si layers 18c and 18d is a second conductivity type a-Si layer (hereinafter, referred to as "a-Si layer" in which impurities such as phosphorus (P) are added at a high concentration.
n ⁺ type a-Si layer). Then, the n ⁺ type a-Si layers 18c and 18d are provided with a stripe-shaped groove in a part thereof and are separated by this groove.

Further, the n ⁺ -type a-Si layer 18c side, is provided with the n ⁺ -type a-Si layer 18c and the connecting electrode 19a for ohmic contact, and the short-circuit wire 20a and the connection electrode 19a It is connected. On the other hand, n ⁺ type a-Si
A connection electrode 19b that makes ohmic contact with the n ⁺ type a-Si layer 18d is provided on the layer 18d side, and the connection electrode 19b and the short-circuit wiring 20b are connected.

The light shielding film 12a receives light from the outside of the substrate 10 from the first and second a-Si layers 16a and 18a.
The first and second a-Si layers 16a and 18c and 18d are island-shaped light-shielding films that prevent the light from entering the c and 18d.
Is provided on the substrate 10 so as to be larger than the outer circumference of the substrate. Therefore,
These a-Si layers 16a, 18c and 18d are shades of the light shielding film with respect to incident light.

Next, referring to FIG. 2, the structure of the SCLC element in the case where the light shielding film is provided on the back surface side of the substrate will be described.

In the second embodiment, the gate insulating film 14, the n ^-- type a-Si layer 16a, the n ⁺ -type a-Si layers 18c and 18d and the connection electrodes 19a and 19 formed on the substrate 10.
b is substantially the same as the shape and arrangement of the SCLC element in FIG. In addition, in the second embodiment, the light shielding film 12a is
n ⁻ type and n ⁺ type a-Si layers 16a and 18c, 18d
Is provided on the back surface side of the substrate 10 so as to face the substrate. Also in this second embodiment, the light shielding film 12a is provided on the back surface side of the substrate 10 so as to be larger than the outer circumferences of the n ⁻ type and n ⁺ type a-Si layers 16a and 18c, 18d. Therefore,
Even with this configuration, external light that enters the substrate 10 from the back side of the substrate 10 has the shielding film 12a, and thus the first and second a-Si.
The layers 16a and 18c, 18d are not reached.

As described above, S of the first and second embodiments
The CLC element 17 includes an n ⁻ type and an n ⁺ type a-Si layer 16a.
And is surrounded by the light-shielding film 12a larger than 18c and 18d, the incident light on the SCLC element 17 by the backlight is blocked when the backlight is driven to drive the TFT. Therefore, in the SCLC element 17, the photocurrent is not excited by the incident light, and the TFT
Since the resistance between the gate electrode and the drain electrode can be kept high, deterioration of image quality of the liquid crystal display, for example, unevenness in display color and lack of contrast can be reduced, or increase in power consumption can be suppressed.

Further, in this embodiment, the address wiring 13
The SCLC element 17 is provided between the short circuit wiring 20b and the data wiring 22 and the short circuit wiring 20a. Since the two-terminal element 17 (SCLC element) has a non-linear current-voltage characteristic, the drive voltage of a normal liquid crystal display is
The resistance of the SCLC element 17 is maintained in a sufficiently high state.
Here, the reason why the SCLC element 17 has nonlinearity will be briefly described.

In the SCLC element 17, when the voltage applied between the connecting electrodes 19a and 19b becomes high, the n ^-- type a--
Excess electrons injected into the Si layer 16a are n ⁻ type aS
Space charges are formed by being trapped in a localized level in the band gap of the i layer 16a. As a result, the Fermi level is displaced to the conduction band side, and the conduction electron density is increased. At this time, it is known that the current flowing in the n ⁻ -type a-Si layer exhibits an IV characteristic that is not proportional to the voltage and rapidly increases. The phenomenon of such space charge limited current is aS
In a semiconductor having a localized level such as an i layer, in particular,
A large non-linear IV characteristic appears remarkably. Therefore, S
In the CLC element 17, a current flows only when a predetermined high voltage is applied between the electrodes.

However, static electricity is generated during the manufacturing process of the liquid crystal display, and the connecting electrode 19 of the SCLC element 17 is generated.
When a high voltage is applied between a and 19b, this SCL
A large current flows through the C element 17. At this time, the address wiring 13 is connected to the short-circuit wiring 20b through the SCLC element 17 (A _G1 ) and the data wiring 22 is SCL.
Since it is connected to the short circuit wiring 20a via the C element 17 (A _D1 ), the address wiring 13 and the data wiring 22 are short-circuited and the potentials of the address wiring 13 and the data wiring 22 become equal. Therefore, even if a high voltage is generated between the gate electrode and the drain electrode of the TFT 34 due to static electricity generated during the manufacture of the TFT array, the discharge generated between the gate electrode and the drain electrode can be suppressed, so that TF can be suppressed.
There is an advantage that the dielectric breakdown or switching failure of T is significantly reduced.

Next, a method of manufacturing the SCLC element will be described with reference to FIGS. However, here, SC
Since the TFT array is formed at the same time as the LC element,
The manufacturing process of the device will also be described.

[2] Method for Manufacturing SCLC Element First, as the substrate 10, a translucent glass substrate is used.
On this substrate 10, chromium (Cr), tantalum (T
a), a conductor layer 1 using one kind of metal selected from aluminum (Al) by a sputtering method or a vapor deposition method.
2 is formed ((A) of FIG. 5). At this time, the conductor layer 1
The film thickness of 2 is preferably 0.1 μm to 0.3 μm.

Next, the conductor layer 12 is patterned into a predetermined shape by photolithography, and the island-shaped light-shielding film 12a, the island-shaped gate electrode 12b, the address wiring (not shown), and the direction of the address wiring. A short-circuit wiring (not shown) extending parallel to is formed (see FIG. 5B).

Next, using a plasma CVD method, an ammonia (NH ₃ ) gas and a silane (SH ₄ ) gas are supplied into the furnace and processed at, for example, a heating temperature of 250 ° C. to 350 ° C. to form a silicon nitride film. 14 is formed ((C) of FIG. 5).
At this time, the thickness of the silicon nitride film 14 is, for example, 0.1 μm.
m to 0.4 μm.

Next, the n ^- type a-Si forming layer 16 is formed by supplying silane gas into the furnace by plasma CVD and performing processing at a heating temperature of 250 ° C., for example. At this time, the film thickness of the n ⁻ -type a-Si forming layer 16 is set to, for example, 0.05.
μm to 0.2 μm. The n ⁻ type a-Si forming layer 16 becomes a channel layer when the TFT element is operated. Subsequently, silane gas and PH ₃ gas are supplied into the furnace and subjected to, for example, a treatment at a heating temperature of 250 ° C., and an n ⁺ type a
The -Si forming layer 18 is formed to obtain the structure shown in FIG. The film thickness of the n ⁺ -type a-Si forming layer 18 at this time is set to, for example, 0.01 μm to 0.1 μm. Note that this n
^{The +} -type a-Si forming layer 18 is used as a layer in ohmic contact.

Next, the n ^-- type a-Si forming layer 16 and the n ⁺
The type a-Si forming layer 18 is patterned into a predetermined shape by using a photolithographic etching method, and first, the island-shaped n ⁻ type a-Si layer 16a is formed on the light shielding film 12a side.
An n ⁻ -type a-Si layer 16b is formed on the gate electrode 12b side.

Further, the n ⁺ type a-Si forming layer 18 is etched and subjected to predetermined patterning, and then the light shielding film 12a is formed.
An n ⁺ type a-Si layer 18a is formed on the side. On the other hand, the n ⁺ -type a-Si layer 18b is formed on the gate electrode 12b side to obtain the structure shown in FIG.

As can be understood from the above steps, the SC
When the LC element 17 is formed, the SCLC element 17 can be formed at the same time as the TFT 34 array, so that there is an advantage that the SCLC element 17 can be formed without increasing the number of conventional manufacturing steps.

After that, a transparent conductive film (ITO film) 26 is formed on the upper surface of the structure of FIG. 6A by using any suitable method, for example, a sputtering method or an evaporation method (FIG. 6B). ), Etching is performed to form an ITO film 26 having a predetermined shape in a portion adjacent to the TFT 34 ((C) of FIG. 6). After that, aluminum (Al) or chromium (Cr) is deposited on the structure of FIG. 6C by using, for example, a vapor deposition method, and then etching is performed by any suitable method to connect to the SCLC element 17 side. The electrodes 19a and 19b are formed. On the other hand, the source electrode 28 and the drain electrode 30 are formed on the TFT 34 element side. Then S
On the CLC element 17 side, arbitrary suitable etching is performed using the connecting electrodes 19a and 19b as a mask to form an n ^{+ -type} a-
The Si layers 18c and 18d are formed. On the other hand, the TFT 34
On the side, using the source electrode 28 and the drain electrode 30 as a mask, any suitable etching is performed to form the n ⁺ -type a-Si layers 18e and 18f ((D) of FIG. 5).

The gate electrode 12b, the address wiring 13, the data wiring 22 and the short-circuit wirings 20a and 20b formed on the substrate 10 are gated through contact holes (not shown) formed in the gate insulating film 14. The connection electrodes 19a and 19b, the source electrode 28, and the drain electrode 30 are connected to the upper surface of the insulating film 14, respectively.

A lower substrate for a liquid crystal display is formed through the above manufacturing process. Then, using any suitable method, an upper substrate (not shown) in which a liquid crystal layer and a transparent electrode are provided on a glass substrate is prepared, and the upper substrate and the lower substrate are combined to complete a liquid crystal display.

[0047]

As is clear from the above description, the SCLC element of the present invention is an island-shaped light-shielding film for preventing light transmitted through the substrate from entering the first and second amorphous silicon layers. Is provided on the substrate so as to be larger than the first and second amorphous silicon layers, the incident light from the backlight is blocked by the blocking film, and therefore the first amorphous silicon layer is leaked by photocurrent. No current is generated. Therefore, since a high resistance can be maintained between the address wiring and the data wiring via the SCLC element, it is possible to suppress deterioration in image quality and increase in power consumption of the liquid crystal display. Further, in the SCLC element, when static electricity is generated between the electrodes of the SCLC element during the manufacturing process and a high voltage is applied, a current flows through the element, and the address wiring and the data wiring are substantially short-circuited. Therefore, the potential between the address wiring and the data wiring is equipotential, and the trouble due to the static electricity of the TFT is suppressed.

Also, when manufacturing an SCLC device, TF
Since it can be manufactured at the same time as the T-array, a highly reliable liquid crystal display can be manufactured without requiring any specially expensive device, jig, or manufacturing process.

[Brief description of drawings]

FIG. 1 is a structure of an SCLC device of the present invention (first embodiment).
FIG. 3 is a schematic cross-sectional view for explaining the above.

FIG. 2 Structure of SCLC element of the present invention (second embodiment)
FIG. 3 is a schematic cross-sectional view for explaining the above.

FIG. 3 is a plan view for explaining an SCLC element of the present invention.

FIG. 4 is a configuration diagram for explaining the overall configuration of an active matrix liquid crystal display used in the present invention.

5A to 5D are process drawings for explaining a method for manufacturing this SCLC element.

6A to 6D are process drawings for explaining a post-process of FIG.

[Explanation of symbols]

10: Glass substrate 12: Conductor layer 12a: Light-shielding film 13: Address wiring 14: Gate insulating film (silicon nitride film) 16: n ^- type a-Si formation layer 16a: n ^- type a-Si layer 17: SCLC element 17a, 17b, 17c, 17d: Connection electrode 18: n ⁺ type a-Si forming layer 18a, 18b, 18c, 18d, 18e, 18f: n
⁺ Type a-Si layer 19, 19a, 19b: connection electrode 20, 20a, 20b: short-circuit wiring 22: data wiring 24: intersection insulating film 34: thin film transistor 36: capacitor 38: liquid crystal 40: pixel

Claims (4)

[Claims] 1. A gate insulating film provided on a translucent substrate, an island-shaped and conductive first amorphous silicon (first a-Si) layer, and the first insulating film on the gate insulating film. A conductive second amorphous silicon (second a-Si) layer in contact with the one amorphous silicon layer, wherein light transmitted through the substrate is incident on the first and second amorphous silicon layers. A space-charge-limited current element, characterized in that an island-shaped light-shielding film for preventing the above is provided on the substrate so as to be larger than the outer circumferences of the first and second amorphous silicon layers. 2. The space charge limited current element according to claim 1, wherein the light shielding film is provided between an upper surface of the substrate and the gate insulating film. 3. The space charge limited current element according to claim 1, wherein the light shielding film is provided on the back surface side of the substrate. 4. In manufacturing the space charge limited current element according to claim 1, (a) a step of forming a conductor layer for forming a gate electrode and a light shielding film on a substrate, and (b)
Patterning the conductor layer using a photolithography method to form islands of a gate electrode and a light-shielding film on the upper surface of the substrate; and (c) forming the gate electrode and the light-shielding film with a gate insulating film. Step of embedding, (d)
A step of sequentially forming a conductive first a-Si forming layer and a conductive second a-Si forming layer on the gate insulating film;
(E) a step of etching the first and second a-Si forming layers to face the light shielding film to form island-shaped first a-Si layers and second a-Si layers. A method for manufacturing a space charge limited current element, comprising: