JPH11218788A - Manufacture of active matrix substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a active matrix substrate which makes it possible to actualize a panel with a high aperture rate by arranging a constant-voltage common line in shading area wherein a source line, a gate line, and thin-film transistor are shaded. SOLUTION: On an insulating substrate 6, a conductive film is deposited and pattered to obtain the constant-voltage common line 18. Then an insulating film 23 is deposited and further a semiconductor thin film 15 such as a polycrystalline silence thin film and an amorphous silicon thin film is deposited and patterned to form an active area. Then a gate insulating film 16 is formed by thermally oxidizing the semiconductor thin film 15 or by a CVD method and then a highly-doped polycrystalline silicone thin firm or metal thin film is deposited and patterned to form a gate line 17 as a gate electrode. This manufacturing method enables the constant-voltage common line 18 and source line 21 to be put close to or overlapping with the gate line 17, so the aperture rate of pixels can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of an active matrix substrate used for a flat panel display such as a liquid crystal panel.

[0002]

2. Description of the Related Art Amorphous silicon on an insulating substrate,
A liquid crystal panel in which thin film transistors using polycrystalline silicon thin films and the like as active areas are arranged in a matrix and the liquid crystal is sealed with another transparent insulating substrate is used for small liquid crystal televisions, wall-mounted televisions, projection liquid crystal displays, etc. Is wide.

FIG. 3 shows an equivalent circuit of an active matrix substrate of the liquid crystal panel. 1 is an n data line group (S1... Sn) and 2 is an m scan line group (G1...).
.. Gm), 3 is an m × n thin film transistor, 5 is a liquid crystal capacity, and 4 is an incapable capacity. The circles indicate the electrode terminals of the counter substrate and are commonly short-circuited. FIG. 4 is a schematic sectional view of the liquid crystal panel.

Reference numeral 6 denotes an active matrix substrate made of an insulating substrate, 7 denotes a transparent pixel electrode, 8 denotes an insulating opposing substrate, 9 denotes a transparent opposing electrode, 10 denotes a light leakage current of a thin film transistor and a distance between the pixel electrodes. A light-shielding film for blocking light, 11 is a liquid crystal, 12 is a sealant, 13 is a lower polarizing plate,
14 is an upper polarizing plate.

FIG. 5A is a plan view showing the structure of one pixel in the equivalent circuit of FIG. 3, and FIG.
It is a 'sectional drawing.

An amorphous silicon or polycrystalline silicon thin film 15 is deposited on a transparent insulating substrate 6 and patterned to form an active area. Next, after depositing the gate insulating film 16 by the CVD method or by oxidizing the silicon thin film,
A polycrystalline silicon thin film or a metal thin film serving as a gate electrode and a gate wiring (scanning line) 17 is deposited and patterned.
Next, another conductive thin film is deposited and patterned to form a constant voltage common line 18. The constant voltage common line 18 is connected to the gate line 17
Although the same material may be used, the transparent conductive film is often used because it often crosses the center of the pixel and causes a reduction in the aperture ratio of the pixel electrode.

Next, using the gate electrode 17 as a mask,
A source / drain region is formed by ion implantation of a phosphorus atom for forming a thin film transistor and a boron atom for forming a p-type thin film transistor. After appropriate annealing, an interlayer insulating film 19 is deposited, a contact hole is opened on the source / drain region, and a transparent conductive film is deposited and patterned to form a transparent pixel electrode 20. Next, a forbidden material is deposited and patterned to form a source line (data line) 21. The unusable capacity 4 in FIG.
It is formed by an interlayer insulating film 19 between the transparent pixel electrode 20 and the constant voltage common line 18.

A portion surrounded by a broken line 22 is an opening on the counter substrate, and a region on the source line 21 and the gate line 17 becomes the light shielding film 10.

[0009]

As described above, the constant voltage common line 18 is desirably transparent in order to increase the aperture ratio, and the transparent conductive film has a low melting point material. Is a material that can be formed at a low temperature, ie, CVD
There is a need for a film or a sputtered film. Normally, dust and flakes are easily generated in this type of film, so that the pixel electrode 20 and the low-voltage common line are often short-circuited due to pinholes, and defect points frequently occur. Larger capacity is preferable,
In this case, since it is difficult to reduce the film pressure of the interlayer insulating film, the electrode area is increased, but the occurrence rate of point defects further increases.

[0010] In order to suppress the occurrence of this point defect, there is a method in which a thermal oxide film having few pinholes is used as an insulating film for forming a capacitance. 6A and 6B show a method of forming an unusable capacity by a thermal oxidation gate insulating film, wherein FIG.
(B) is an aa ′ cross-sectional view in (a). Specifically, the non-capacitance is a gate insulating film capacitance between the low voltage common line 18 and the extension electrode of the drain electrode of the thin film transistor, and an interlayer insulating film capacitance between the pixel electrode 20 and the constant voltage common line 18. However, the former capacity occupies the majority due to the thickness of the insulating film. Therefore, compared to FIG. 5, when the additional capacitance is made approximately the same, the electrode area can be reduced by almost one digit, so that point defects due to pinholes are remarkably reduced from the area and film quality.

However, even if the material of the constant voltage common line 18 is a transparent material, the transmittance is reduced because the drain region is a semi-transparent semiconductor thin film, which causes the aperture ratio to be reduced.

If the constant voltage common line 18 is brought close to the gate line 17, the aperture ratio can be improved, but the distance W between the two wirings can be improved.
In the case of a long parallel wiring, there is a limit to the possibility of short-circuiting, so there is a limit, and it is difficult to avoid passing through the center of the pixel.

In particular, when the pixel pitch is high, the ratio of the area of the constant voltage common line, which reduces the aperture ratio, increases, and the aperture ratio decreases significantly. Specifically, the pixel pitch is 50 μ
In a high-density panel of about 50 μm in width and about 50 μm in width, the aperture ratio is about 20% when a sufficient additional capacity (about 3 to 5 times the liquid crystal capacity) is to be formed, and the entire panel is dark because the light-shielding area occupies most. It becomes a blue display.

An object of the present invention is to provide an active matrix substrate capable of producing a sufficient additional capacitance and realizing a panel having a high aperture ratio even in a high-density panel.

[0015]

An active matrix substrate according to the present invention comprises a first wiring layer comprising a group of data lines arranged in parallel on an insulating substrate and a second wiring layer comprising a group of scanning lines orthogonal to the group of data lines. And a thin film transistor in which a data line is connected to a source electrode, a scanning line is a gate electrode, and a drain electrode is connected to a transparent pixel electrode, and a dielectric film connected to the drain electrode is located at the intersection of the wiring group. And a third wiring layer composed of a group of constant voltage common lines opposed to each other, the first wiring layer or the second wiring layer and the third wiring layer approach or overlap with each other, and A first insulating film, a semiconductor film of a thin film transistor, and a second insulating film are sandwiched between layers.

[0016]

According to the present invention, in order to increase the aperture ratio, a constant voltage common line is arranged in a light shielding region for shielding a source line, a gate line and a thin film transistor. For this reason, a multilayer wiring is used so as not to short-circuit with a source line or a gate line. Specifically, a first insulating film, a semiconductor film of a thin film transistor, and a second insulating film are formed on the constant voltage common line, and a gate line or a source line is provided thereon.

If each of the first insulating film and the second insulating film is a thermal oxide film of a constant voltage common line, it becomes an insulating film with few pinholes, and a high-density panel with few point defects can be realized.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

[0019]

FIG. 1 shows a first embodiment of the present invention, in which a constant voltage common line is adjacent to or overlapped with a source line. (A) is a plan view of the structure, and (b) and (c) are aa ′ and bb ′ in (a).
It is sectional drawing.

In the order of steps, on the insulating substrate 6,
A conductive film is deposited and patterned to form a constant voltage common line 18. The conductive film may be a metal or a polycrystalline silicon thin film to which a high concentration impurity is added. Next, an insulating film 23 is deposited. The insulating film is made of S by CVD, sputtering or the like.
An iO ₂ film or an oxide film of a constant voltage common line by a thermal oxidation method may be used. Next, a semiconductor thin film 15 such as a polycrystalline silicon thin film or an amorphous silicon thin film is deposited and patterned to form an active region.

The additional capacitance depends on the film thickness and quality of the insulating film 23 and the electrode area of the semiconductor thin film 15 and the constant voltage common line 18 which constitute the capacitance. The insulating film formed by the thermal oxidation method has advantages in that pinholes are small and uniform, so that the thickness can be reduced and the electrode area can be reduced.

Next, the semiconductor thin film 15 is thermally oxidized, or a gate insulating film 16 is formed by a similar CVD method. Subsequently, a high-doped polycrystalline silicon thin film or a metal thin film is deposited and patterned. Electrode, gate line 17
To form Next, using the gate electrode as a mask, N
In the case of a type thin film transistor, phosphorus atoms are implanted, and in the case of a P type thin film transistor, boron atoms are ion-implanted and then annealed to form source / drain regions 24 and 25.

Next, an interlayer insulating film 19 is deposited by a CVD method, and a contact hole is opened. A transparent conductive film is deposited and patterned to deposit a transparent pixel electrode 20, a metal film, and a source line 21 is formed by patterning. By such a process, the thin film transistor is connected to the source line 21.
To the source region, the gate line to the gate electrode, the transparent pixel electrode 2
0, the drain region is connected, and the constant voltage common line 18 is opposed to the electrode connected to the drain region and the insulating film 23 which is a dielectric film.

The constant voltage common line is desirably set to the ground potential so that channel inversion does not occur when a channel silicon thin film is formed on the common line.
If the channel region is shifted from the constant voltage common line, the level of the constant voltage can be changed. The constant voltage common line may be slightly deviated from the source line, but the amount of deviation increases the light-shielding region and the broken line 22 is located inside the pixel electrode, so that the aperture ratio is slightly lowered.

FIG. 2 shows a second embodiment of the present invention, in which a constant voltage common line is adjacent to or overlapped with a gate line. (A) is a plan view of the structure, and (b) and (c) are aa ′ and bb ′ cross-sectional views.

The process is the same as that shown in FIG. Compared to FIG. 6, since the constant voltage common line and the gate line are arranged in a multilayer structure, it is possible to eliminate the sense of the constant voltage common line and the gate line.

Therefore, as compared with FIG. 6, the transmittance and the aperture ratio can be improved.

[0028]

According to the present invention, the aperture ratio of a pixel can be improved by forming a constant voltage common line, a source line, or a gate line in the vicinity of or in a superimposed structure.

This is more effective in the case of a panel having high-density pixels (for example, a light valve of a video projector).

When a thermal oxide film is used as the insulating film of the additional capacitance, a panel having few pinholes and few point defects can be realized, thereby improving the yield and reducing the cost.

[Brief description of the drawings]

FIG. 1 is a plan view of an active matrix substrate according to an embodiment of the present invention.

FIG. 2 is a sectional view of an active matrix substrate according to an embodiment of the present invention.

FIG. 3 is a basic circuit diagram of an active matrix substrate.

FIG. 4 is a structural sectional view of a liquid crystal panel using an active matrix substrate.

FIG. 5 is a plan view of a conventional active matrix substrate.

FIG. 6 is a sectional view of a conventional active matrix substrate.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Source line (data line) 2 Gate line (scanning line) 3 Thin film transistor 4 Additional capacitance 5 Liquid crystal capacitance 6 Insulating substrate 7 Pixel electrode 8 Counter substrate 9 Counter electrode 10 Light shielding layer 11 Liquid crystal 12 Sealant 13 Lower polarizing plate 14 Upper Polarizing plate 15 Semiconductor thin film 16 Gate insulating film 17 Gate line (gate electrode) 18 Constant voltage common line 19 Interlayer insulating film 20 Pixel electrode 21 Source line 22 Boundary between opening area and light-shielding area of opposing substrate 23 Additional capacitance insulating film 24 Source area 25 Drain region

[Procedure amendment]

[Submission date] December 21, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

Patent application title: Method for manufacturing active matrix substrate

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction contents]

[0001]

The present invention relates to a method for manufacturing an active matrix substrate used for a flat panel display such as a liquid crystal panel.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

[0015]

SUMMARY OF THE INVENTION The present invention is directed to a method for manufacturing an active matrix substrate having a substrate having a plurality of source lines, a plurality of gate lines, and a thin film transistor connected to each of the source lines and each of the gate lines. Forming a common line by forming and patterning a conductive film on the substrate, forming an insulating film on the common line, and forming an electrode on the insulating film so as to overlap the common line. Forming a silicon thin film to be a source / drain region of the thin film transistor, forming the gate line on the silicon thin film via a gate insulating film, and connecting to the source region of the silicon thin film. And forming the source line so as to overlap with the common line via the insulating film.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction contents]

[0028]

According to the present invention, since the common line and the source line have a structure overlapping with an insulating film interposed therebetween, it is possible to form an additional capacitor and improve the aperture ratio of a pixel without increasing the number of steps. it can.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0029

[Correction method] Deleted

Claims (1)

[Claims] A first wiring layer comprising a data line group disposed in parallel on an insulating substrate; a second wiring layer comprising a scanning line group orthogonal to the data line group; and an intersection of the wiring group. A thin-film transistor in which a source electrode is connected to a data line, a gate electrode is connected to a scanning line, and a drain electrode is connected to a transparent pixel electrode; and a constant voltage common line group facing the electrode connected to the drain electrode with a dielectric film therebetween. A first wiring layer or a second wiring layer and a third wiring layer approach or overlap with each other, and a first insulating film and a thin film transistor are provided between the wiring layers. An active matrix substrate, wherein a semiconductor thin film and a second insulating film are sandwiched.