JPH07248990A - Inter-device data transfer method - Google Patents

Inter-device data transfer method

Info

Publication number
JPH07248990A
JPH07248990A JP6038068A JP3806894A JPH07248990A JP H07248990 A JPH07248990 A JP H07248990A JP 6038068 A JP6038068 A JP 6038068A JP 3806894 A JP3806894 A JP 3806894A JP H07248990 A JPH07248990 A JP H07248990A
Authority
JP
Japan
Prior art keywords
address
transfer
processor
mpu
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6038068A
Other languages
Japanese (ja)
Other versions
JP3687684B2 (en
Inventor
Michihiro Aoki
道宏 青木
Katsuyuki Okada
勝行 岡田
Koichi Shimizu
浩一 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP03806894A priority Critical patent/JP3687684B2/en
Publication of JPH07248990A publication Critical patent/JPH07248990A/en
Application granted granted Critical
Publication of JP3687684B2 publication Critical patent/JP3687684B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To prevent a device of the transmitter side from being influenced by the change of the address of a device of the receiver side used for transfer of data by providing such a constitution where the device of the transmitter side receives the address information stored in a storage medium from the device of the receiver side before transfer of data. CONSTITUTION:An MPU 5 of a processor 2 of the transmitter side starts a command transmission program and produces the communication information including an address aquiring command to send this information to an MPU 5 of a processor 2 of the receiver side via a driver/receiver control part 4 and a bus 1. Thus the processor 2 of the receiver side receives the communication information, and the MPU 5 identifies the contents of a command. If the received command is identified as an address acquiring command, the MPU 5 of the processor 2 of the receiver side reads a transfer address out of an address holding part 3F based on an answer return processing program 3E. Then the MPU 5 produces the answer communication information and sends it in reply to the processor 2 of the transmitter side. The processor 2 of the transmitter side identifies the received answer and stores a transfer address in the part 3F.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、例えば交換システムや
情報処理システムで装置相互間データを転送するための
装置間データ転送方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device-to-device data transfer method for transferring data between devices in a switching system or an information processing system, for example.

【0002】[0002]

【従来の技術】装置相互間でデータを転送する方法とし
ては受信側装置のレジスタやメモリバッファのデータ記
憶領域のアドレスを転送先アドレスとして送受信装置間
で定めておき、送信側の装置が予め決められたアドレス
に対してデータを転送する方法が知られている。このよ
うなデータ転送方法では上記転送アドレスは固定化され
ているので、一方の装置側の都合でデータ容量、すなわ
ち、メモリバッファの容量や転送アドレスを簡単には変
更できない。
2. Description of the Related Art As a method for transferring data between devices, the address of a data storage area of a register or a memory buffer of a receiving device is set as a transfer destination address between transmitting and receiving devices, and the transmitting device predetermines. A method of transferring data to a given address is known. In such a data transfer method, since the transfer address is fixed, the data capacity, that is, the capacity of the memory buffer and the transfer address cannot be easily changed due to the convenience of one device.

【0003】[0003]

【発明が解決しようとする課題】もし、転送アドレスを
変更する場合には、例えば、送信側および受信側双方の
通信プログラム中に記載された転送アドレス情報を書き
直す必要がある。このような制約が送受信装置の双方に
生じることは、それぞれの装置が使用するアドレス空間
を変更できないことを意味し、新規に装置に新しい機能
を追加したり、データ転送量の追加する場合の阻害要件
になっていた。
If the transfer address is changed, for example, it is necessary to rewrite the transfer address information described in the communication programs of both the transmitting side and the receiving side. The fact that such restrictions occur on both the transmitting and receiving devices means that the address space used by each device cannot be changed, which impedes adding new functions to the device or adding data transfer amount. It was a requirement.

【0004】そこで、本発明の目的は、上述の点に鑑み
て、送受信装置のうちの少なくとも送信装置側では受信
装置側の転送アドレスの変更の影響を受けない装置間デ
ータ転送方法を提供することにある。
Therefore, in view of the above points, an object of the present invention is to provide an inter-device data transfer method in which at least the transmitting device of the transmitting and receiving devices is not affected by the change of the transfer address of the receiving device. It is in.

【0005】[0005]

【課題を解決するための手段】このような目的を達成す
るために、請求項1の発明は、受信側の装置のアドレス
空間の一部を送信側の装置が使用して送信側の装置から
受信側の装置にデータを転送する装置間転送方法におい
て、前記アドレス空間の一部を示すアドレス情報を前記
受信側の装置内の記憶媒体に保持しておき、前記データ
の転送に先立って、前記送信側の装置は前記記憶媒体に
保持されたアドレス情報を前記受信側の装置から受信す
ることを特徴とする。
In order to achieve such an object, the invention of claim 1 uses a part of the address space of the receiving side device by the transmitting side device so that the transmitting side device can In an inter-device transfer method for transferring data to a device on the receiving side, address information indicating a part of the address space is held in a storage medium in the device on the receiving side, and before the data transfer, The device on the transmission side receives the address information held in the storage medium from the device on the reception side.

【0006】請求項2の発明は、請求項1の発明に加え
て、前記記憶媒体は新たな書き込みにより保持内容を変
更可能であることを特徴とする。
The invention of claim 2 is, in addition to the invention of claim 1, characterized in that the contents held in the storage medium can be changed by new writing.

【0007】[0007]

【作用】請求項1の発明によれば、データ転送に使用す
る受信側の装置のアドレスが変わっても送信側の装置で
はその都度そのアドレスを入手できるので、アドレスの
変更の影響を受けない。
According to the first aspect of the invention, even if the address of the receiving side device used for data transfer is changed, the address of the transmitting side device can be obtained each time, so that it is not affected by the change of the address.

【0008】請求項2の発明では、記憶媒体の記憶内容
を変更可能とすることで受信側の装置でもハードウェア
についての変更を要せずアドレス情報の変更が可能とな
る。
According to the second aspect of the present invention, the contents stored in the storage medium can be changed so that the device on the receiving side can change the address information without changing the hardware.

【0009】[0009]

【実施例】以下、図面を使用して、本発明の実施例を詳
細に説明する。図1は本発明実施例のシステム構成を示
す。
Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the system configuration of an embodiment of the present invention.

【0010】図1において複数のプロセッサ(この場
合、演算処理装置)2が共通バス1に接続されている。
プロセッサ2は他のプロセッサ2との間でデータ転送を
行う。プロセッサ2が受信側となる場合の構成を図2に
示し、プロセッサ2が送信側となる場合の構成を図3に
示す。
In FIG. 1, a plurality of processors (processors in this case) 2 are connected to a common bus 1.
The processor 2 transfers data with another processor 2. 2 shows the configuration when the processor 2 is the receiving side, and FIG. 3 shows the configuration when the processor 2 is the transmitting side.

【0011】プロセッサ2はドライバ/レシーバ制御部
4、マイクロプロセッサ(以下、MPUと略す)5およ
び記憶部3を有する。ドライバ/レシーバ制御部4は通
信インターフェースとして機能する。MPU5は記憶部
3に格納されたコマンド送信処理プログラム3A、コマ
ンド受信処理プログラム3D、アンサ受信処理プログラ
ム3B、アンサ返送処理プログラム3Eを実行すること
により他のプロセッサ2と転送アドレスを用いたデータ
転送を実行する。また、記憶部3に格納された不図示の
プログラムにより各種の情報処理を実行する。記憶部3
にはさらに他のプロセッサ2に対して送信および受信す
るデータをそれぞれ記憶する転送データ記憶領域(不図
示)が設けられている。記憶部3にはさらに、アドレス
保持部(応答送信する転送アドレスの記憶領域)3Fと
アンサ保持部(受信した転送アドレスの記憶領域)3C
が設けられている。
The processor 2 has a driver / receiver control unit 4, a microprocessor (hereinafter abbreviated as MPU) 5, and a storage unit 3. The driver / receiver control unit 4 functions as a communication interface. The MPU 5 executes the command transmission processing program 3A, the command reception processing program 3D, the answer reception processing program 3B, and the answer return processing program 3E stored in the storage unit 3 to transfer data using another processor 2 and a transfer address. Run. Further, various information processing is executed by a program (not shown) stored in the storage unit 3. Storage unit 3
Is further provided with a transfer data storage area (not shown) for storing data to be transmitted to and received from another processor 2. The storage unit 3 further includes an address holding unit (a storage area for a transfer address to send a response) 3F and an answer holding unit (a storage area for a received transfer address) 3C.
Is provided.

【0012】アドレス保持部3Fは他のプロセッサから
問い合わせがあったときに応答する転送アドレスを記憶
する。この転送アドレスが記憶部3中の転送データ記憶
領域のアドレスと対応する。アドレス保持部3Fの記憶
データはMPU5の書き込み処理により変更可能であ
り、ユーザはキーボード等の入力装置を介してMPU5
に指示を与えてアドレス保持部3Fの記憶データすなわ
ち転送アドレスを設定する。
The address holding unit 3F stores a transfer address that responds when an inquiry is made from another processor. This transfer address corresponds to the address of the transfer data storage area in the storage unit 3. The data stored in the address holding unit 3F can be changed by the writing process of the MPU 5, and the user can change the MPU 5 via an input device such as a keyboard.
To set the storage data of the address holding unit 3F, that is, the transfer address.

【0013】このようなシステム構成において実行され
るデータ転送処理を図4および図5を参照しながら説明
する。なお、図4は記憶部3に格納された通信関連プロ
グラムの内容を示す。図5は送受信プロセッサ間で行わ
れる通信手順(プロトコル)の内容を示す。
A data transfer process executed in such a system configuration will be described with reference to FIGS. 4 and 5. Note that FIG. 4 shows the contents of the communication-related program stored in the storage unit 3. FIG. 5 shows the contents of the communication procedure (protocol) performed between the transmitting and receiving processors.

【0014】データを送信するプロセッサ2を送信側、
データを受信するプロセッサ2を受信側と略記する。送
信側のMPU5はコマンド送信プログラムを起動してア
ドレス収得コマンドを含む通信情報を作成する(図4の
S100、図5のP10)。アドレス収得コマンドは受
信側に対して転送アドレスを送信するように指示する命
令である。この通信情報のフォーマット自体にはプロセ
ッサ間の通信路の形態に合わせ、従来からよく知られて
いるものを使用することができる。
The processor 2 for transmitting data is set to the transmitting side,
The processor 2 that receives the data is abbreviated as the receiving side. The MPU 5 on the transmission side activates the command transmission program to create communication information including the address acquisition command (S100 in FIG. 4, P10 in FIG. 5). The address acquisition command is a command for instructing the receiving side to transmit the transfer address. As the format of this communication information, a well-known one can be used according to the form of the communication path between the processors.

【0015】作成された通信情報がドライバ/レシーバ
制御部4およびバス1を介して受信側のMPU5に送信
される(図4のS110)。受信側ではこの通信情報を
コマンド受信プログラムにより受信するとMPU5がコ
マンドの内容を識別する(図4のS200→S210、
図5のP100)。この識別の結果、受信コマンドがア
ドレス収得コマンドであることが識別されると、受信側
のMPU5はアンサ返送処理プログラム3Eに基づい
て、アドレス保持部3Fに保持されている転送アドレス
を読み出し、転送アドレスを含むアンサ、すなわち、応
答用の通信情報を作成して送信側に応答送信する(図4
のS220→S230→S240、図5のP110)。
The created communication information is transmitted to the MPU 5 on the receiving side via the driver / receiver control section 4 and the bus 1 (S110 in FIG. 4). On the receiving side, when this communication information is received by the command receiving program, the MPU 5 identifies the content of the command (S200 → S210 in FIG. 4,
P100 in FIG. 5). As a result of this identification, when the received command is identified as the address acquisition command, the MPU 5 on the receiving side reads the transfer address held in the address holding unit 3F based on the answer return processing program 3E and transfers the transfer address. An answer including "," that is, communication information for response is created, and the response is transmitted to the sender (Fig. 4).
S220 → S230 → S240, P110 of FIG. 5).

【0016】送信側のMPU5ではアンサ受信プログラ
ム3Bによりアンサを受信すると、アンサの内容がアド
レス収得コマンドに関するアンサであることを識別する
(図4のS120→S130、図5のP20)。この
後、MPU5は受信したアンサの中に含まれる転送アド
レスをアンサ保持部3Cに格納する(図4のS140、
図5のP30)。以下、送信側のMPU5はアンサ保持
部3Cに保持された転送アドレスを用いて従来と同様の
データ転送を行う(図4のS150、図5のP40)。
When the MPU 5 on the transmitting side receives the answer by the answer receiving program 3B, it identifies that the content of the answer is the answer regarding the address acquisition command (S120 → S130 in FIG. 4, P20 in FIG. 5). After that, the MPU 5 stores the transfer address included in the received answer in the answer holding unit 3C (S140 in FIG. 4,
P30 of FIG. 5). Thereafter, the MPU 5 on the transmission side uses the transfer address held in the answer holding unit 3C to perform the same data transfer as in the conventional case (S150 in FIG. 4, P40 in FIG. 5).

【0017】本実施例の他に次の例を実施できる。In addition to this embodiment, the following example can be implemented.

【0018】1)送信側の装置が受信側装置のアドレス
についての指定を行うデータ通信方法を採用するシステ
ムであれば本発明を適用できる。たとえば、送信側の装
置(MPU)がアドレス指定および読み/書きの指示を
行って受信側の装置内のメモリに直接、転送データをア
クセスするシステムなど受信装置側のアドレス空間の一
部を転送データのために使用するシステムに本発明は好
適である。
1) The present invention can be applied to any system that employs a data communication method in which a device on the transmission side specifies an address of a device on the reception side. For example, a part of the address space on the receiving device side such as a system in which a device on the transmitting side (MPU) performs address designation and a read / write instruction to directly access the transfer data in the memory on the receiving side. The present invention is suitable for the system used for.

【0019】2)本実施例では転送アドレス(本発明の
アドレス情報)を保持するアドレス保持部3FにはRA
Mの記憶領域を割り当てるようにしているがラッチ回路
やフロッピーディスク等、MPU5の新たな書き込みに
より記憶内容を変更できる記憶媒体であればどのような
記憶媒体をも用いることができる。
2) In this embodiment, the address holding unit 3F holding the transfer address (address information of the present invention) has RA.
Although the storage area of M is allocated, any storage medium such as a latch circuit or a floppy disk whose storage content can be changed by new writing of the MPU 5 can be used.

【0020】3)受信側に保持しておく転送アドレスを
変更不可能にしておきたい場合にはアドレス保持部3F
にはROMなどの読み出し専用メモリを用いるとよい。
この場合に、転送アドレスを変更するときは受信側では
ROMを交換することになるが送信側では何等のシステ
ム変更を要しない。
3) When it is desired to make the transfer address held on the receiving side unchangeable, the address holding unit 3F
For this purpose, a read-only memory such as a ROM may be used.
In this case, when changing the transfer address, the ROM is replaced on the receiving side, but no system change is required on the transmitting side.

【0021】[0021]

【発明の効果】以上説明したように、請求項1の発明に
よれば、送信側の装置では、アドレスの変更があっても
ハードウエア構成を変更する必要はない。
As described above, according to the first aspect of the present invention, it is not necessary to change the hardware configuration of the transmitting side device even if the address is changed.

【0022】また、請求項2の発明では受信側の装置で
もハードウェアの変更を要することなくアドレス情報を
変更できる。これにより、アドレスの制約がなくなるの
で、装置内のアドレス空間を自由に変更でき、自由な装
置設計、製造ができるという効果が得られる。さらに
は、新規に開発した装置と開発前の旧装置との間でデー
タ転送を行う場合でもアドレス情報を外部たとえばキー
ボードから与えることによりデータ転送が可能となる。
According to the second aspect of the invention, the address information can be changed even in the device on the receiving side without changing the hardware. As a result, the restriction of addresses is eliminated, and the address space in the device can be freely changed, and the effect that the device can be freely designed and manufactured can be obtained. Furthermore, even when data is transferred between a newly developed device and an old device before development, it is possible to transfer data by giving address information from an external device such as a keyboard.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例のシステム構成を示すブロック図
である。
FIG. 1 is a block diagram showing a system configuration of an embodiment of the present invention.

【図2】受信側のプロセッサ2のシステム構成を示すブ
ロック図である。
FIG. 2 is a block diagram showing a system configuration of a processor 2 on a receiving side.

【図3】送信側のプロセッサ2のシステム構成を示すブ
ロック図である。
FIG. 3 is a block diagram showing a system configuration of a processor 2 on a transmission side.

【図4】本発明に関わるデータ通信手順を示すフローチ
ャートである。
FIG. 4 is a flowchart showing a data communication procedure according to the present invention.

【図5】本発明に関わるデータ通信手順を示す説明図で
ある。
FIG. 5 is an explanatory diagram showing a data communication procedure according to the present invention.

【符号の説明】[Explanation of symbols]

1 共通バス 2 プロセッサ 3 記憶部 4 マイクロプロセッサ(MPU) 1 common bus 2 processor 3 storage unit 4 microprocessor (MPU)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 受信側の装置のアドレス空間の一部を送
信側の装置が使用して送信側の装置から受信側の装置に
データを転送する装置間転送方法において、 前記アドレス空間の一部を示すアドレス情報を前記受信
側の装置内の記憶媒体に保持しておき、 前記データの転送に先立って、前記送信側の装置は前記
記憶媒体に保持されたアドレス情報を前記受信側の装置
から受信することを特徴とする装置間データ転送方法。
1. An inter-device transfer method in which a device on the transmission side uses a part of the address space of a device on the reception side to transfer data from a device on the transmission side to a device on the reception side. Is stored in a storage medium in the device on the receiving side, and the device on the transmitting side transfers the address information stored in the storage medium from the device on the receiving side prior to the transfer of the data. An inter-device data transfer method characterized by receiving.
【請求項2】 前記記憶媒体は新たな書き込みにより保
持内容を変更可能であることを特徴とする請求項1に記
載の装置間データ転送方法。
2. The inter-device data transfer method according to claim 1, wherein the stored contents of the storage medium can be changed by new writing.
JP03806894A 1994-03-09 1994-03-09 Data transfer method between devices Expired - Lifetime JP3687684B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03806894A JP3687684B2 (en) 1994-03-09 1994-03-09 Data transfer method between devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03806894A JP3687684B2 (en) 1994-03-09 1994-03-09 Data transfer method between devices

Publications (2)

Publication Number Publication Date
JPH07248990A true JPH07248990A (en) 1995-09-26
JP3687684B2 JP3687684B2 (en) 2005-08-24

Family

ID=12515181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03806894A Expired - Lifetime JP3687684B2 (en) 1994-03-09 1994-03-09 Data transfer method between devices

Country Status (1)

Country Link
JP (1) JP3687684B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010027064A1 (en) * 2008-09-04 2012-02-02 日本電気株式会社 Data transmission method, data transmission system, data transmission device, data reception device, and control program

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010027064A1 (en) * 2008-09-04 2012-02-02 日本電気株式会社 Data transmission method, data transmission system, data transmission device, data reception device, and control program

Also Published As

Publication number Publication date
JP3687684B2 (en) 2005-08-24

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