JPWO2010027064A1 - Data transmission method, data transmission system, data transmission device, data reception device, and control program - Google Patents

Abstract

The simplification of the access processing of the reception data buffer is achieved. This communication system (data transmission system) 1 is a data transmission for sequentially transmitting data with a write address for storing data for each data transmission unit in a reception data buffer (reception side storage means) 115 in units of data transmission. The apparatus 10 includes a data reception apparatus 110 that stores sequentially received data in a storage position of a reception data buffer 115 specified by a write address added to the data.

Description

  The present invention relates to a data transmission method, a data transmission system, a data transmission device, a data reception device, and a control program. More specifically, the present invention relates to a data transmission method useful for avoiding complication of address control processing when receiving data, The present invention relates to a data transmission system, a data transmission device, a data reception device, and a control program.

As a means for successfully performing data communication, a frame retransmission control method has been conventionally known. This frame retransmission control method is an error control method for correctly receiving a frame even if an error occurs in a frame received by the data receiving device when performing frame communication between the data transmitting device and the data receiving device. is there.
One of the retransmission control methods is a Selective Repeat ARQ (Automatic Repeat request) method.

FIG. 9 shows a configuration example of a communication system as a related technique using the selective repeat ARQ.
The outline of transmission and reception in this communication system will be described as follows. When a sequential sequence number (SQN) is added to the frames that are sequentially transmitted by the data transmitting apparatus 90 and the data receiving apparatus 910 can correctly receive the frames, an ACK (Acknowledgement) frame of the sequence number is returned. However, if reception is not possible due to frame loss or bit error, an ACK frame is not returned.
In the data transmitting apparatus 90, when an ACK frame is returned within a certain time, it is considered that the frame with the sequence number has been transmitted correctly to the data receiving apparatus 910, while an ACK frame is not returned within the certain time. In this case, only the frame with the sequence number is retransmitted on the assumption that the frame with the sequence number did not reach the data receiving apparatus 910 correctly.

For example, as shown in FIG. 10, frames 1 to 3 are normally received by the data receiving apparatus and an ACK frame is returned to the data transmitting apparatus, but frame 4 is lost on the transmission path, and the data receiving apparatus ACK frame is not returned to the data transmitting apparatus, timeout occurs, and frame 4 is retransmitted from the data transmitting apparatus.
In this way, by efficiently retransmitting only frames that could not be received correctly, it is possible to efficiently use the transmission path.
There is also a method of returning a NACK (Negative Acknowledgment) frame to the data transmitting apparatus when the frame is not correctly received.

A specific example of the above-described frame retransmission will be described with reference to FIG.
When frame data is input to the data transmitter 90, first, the SQN adding circuit 91 adds a continuous transmission SQN value (transmission sequence number) for each frame, and transmits the frame data and the transmission SQN value to the transmission data buffer 92. To store.
Next, in response to a read instruction from the transmission data buffer control circuit 93, the frame data and the transmission SQN value are read out. A frame generation circuit 94 that receives this adds a header and a trailer to generate a transmission frame and sends it to the downstream transmission line 100. An example of the trailer is a CRC (Cyclic Redundancy Check) value for frame error detection.
Simultaneously with transmission of the transmission frame, the transmission SQN value is input to the retransmission timer 98, and counting of the retransmission timer corresponding to the transmission SQN value is started.

On the other hand, in the data receiving device 910, when a transmission frame is input, the frame inspection circuit 911 inspects the header and trailer. If the inspection result indicates that there is an abnormality in the transmission frame, the frame inspection circuit 911 discards the frame.
If the inspection result indicates normal reception of the transmission frame, the frame is transferred to the SQN detection circuit 912. The SQN detection circuit 912 extracts the received SQN value and transfers it to the ACK generation circuit 915, while transferring it to the reception data buffer control circuit 913 and storing the reception payload data in the reception data buffer 914.
The ACK generation circuit 916 that has received the received SQN value generates ACK frame payload data from the SQN value, and returns the ACK frame from the frame generation circuit 916 to the data transmission device 90 via the uplink transmission path 110.

When receiving a frame from the upstream transmission path 110, the frame inspection circuit 95 of the data transmission apparatus 90 performs a CRC inspection to confirm that there is no error in the frame.
Then, the reception SQN value stored in the ACK frame is extracted by the ACK reception circuit 96 and transferred to the transmission data buffer control circuit 93 and the retransmission timer 98.
The timer corresponding to the transmission SQN value of the retransmission timer 98 that starts counting simultaneously with the transmission of the transmission frame monitors whether or not the ACK frame is returned within a predetermined time, that is, whether or not a timeout has occurred. When a time-out occurs, the transmission data buffer control circuit 93 is notified of the time-out SQN value, and a retransmission is instructed.

The transmission data buffer control circuit 93 reads the time-out SQN value and the corresponding payload data from the transmission data buffer 92 again, and retransmits them to the transmission line 100 via the frame generation circuit 94.
When the reception SQN value is input from the ACK reception circuit 96, the transmission data buffer control circuit 93 releases an area in which the payload data of the transmission data buffer 92 corresponding to the SQN value is stored, and transmits other frames. Make writable.
When the retransmission frame is received by the data reception device 910, if the retransmission frame is normally received, the received payload data is stored in the reception data buffer 914.

Even in the communication system as the related technology described above, when a failure such as an error occurs in the received frame, the frame can be normally transmitted by retransmitting the frame by the Selective Repeat ARQ method.
However, for example, as shown in FIG. 10, during transmission of the frame, the frame 4 is discarded by the first transfer, the sequential frame transfer is performed as shown in FIGS. Is performed next, the storage order of the retransmitted frame 4 in the reception data buffer 914 is the arrival order of the frames as shown in FIG.

Such storage in the reception data buffer 914 is because the frame length information cannot be obtained by discarding the frame 4, and the storage area to be secured between the frame 3 and the frame 5 in the reception process is unknown. The payload data of the frame to which the sequence number is assigned cannot be stored in the continuous memory area of the reception data buffer. In such a storage state, it is necessary to secure the frame order in communication, and therefore a read process of reading from the received data buffer in order of SQN values is necessary.
Therefore, in order to process the frame sequence stored at non-consecutive addresses in order from the lowest number of SQN, it is necessary to manage the SQN value of the frame and the address where the frame is stored in association with each other. The data buffer frame write process and the read process are complicated, and an increase in the circuit scale of the control circuit is inevitable.
Since writing and reading to such non-consecutive addresses must be performed, the processing speed is restricted, and as a result, it is difficult to increase the bandwidth.

  The present invention has been made in view of the above circumstances, and provides a data transmission method, a data transmission system, a data transmission device, a data reception device, and a control program capable of achieving simplification of data access processing and the like. It is an object.

  In order to solve the above-described problems, a first configuration of the present invention relates to a data transmission method, and a data transmission side uses data as a write address for storing data for each data transmission unit in a reception-side storage means. In addition, the data to which the write address is added is sequentially transmitted in the data transmission unit, and the data received on the data receiving side is sequentially specified by the write address added to the data. The data is stored in the storage position of the side storage means.

  A second configuration of the present invention relates to a data transmission system, wherein the data transmission unit sequentially transmits the data to which the write address for storing the data for each data transmission unit is stored in the receiving side storage means in the data transmission unit. And a data receiving device for storing the sequentially received data in a storage location of the receiving storage means specified by the write address added to the data.

  According to the configuration of the present invention, since the write address or the write address head value on the data receiving side is generated on the data transmitting side and transmitted to the data receiving side, the access control processing on the data receiving side is simplified. Is obtained.

It is a block diagram which shows the electric constitution of the communication system which has the write address notification type retransmission control function which is Embodiment 1 of this invention. It is a figure which shows the structural example of the storage area of the transmission data buffer of the communication system which has the same write address notification type retransmission control function. It is a figure which shows the structural example of the reception data buffer of the communication system which has the same write address notification type retransmission control function. It is a figure which shows the structural example of the frame format transmitted / received by the communication system which has the same write address notification type retransmission control function. It is a block diagram which shows the electric constitution of the communication system which has the write address notification type retransmission control function which is Embodiment 2 of this invention. It is a figure which shows the frame format transmitted / received by the communication system which has the same write address notification type retransmission control function. It is a figure which shows the storage aspect in the transmission data buffer of the communication system which has the same write address notification type retransmission control function. It is a figure which shows the storage aspect in the reception data buffer of the communication system which has the same write address notification type retransmission control function. It is a block diagram of the electrical constitution of the retransmission control system as related technology. It is explanatory drawing of the example from which a flame | frame is missing in the retransmission control system as related technology. It is a figure which shows the specific example of the flame | frame missing in the retransmission control system as related technology. It is a figure which shows the storage state of the reception data buffer in the example of FIG.

1, 1A communication system (data transmission system)
11 SQN addition circuit (input means)
12 Frame length counter (address generating means, measuring means)
13 Write address calculation circuit (address generation means)
14, 55 Transmission data buffer (address generation means)
15, 56 Write address addition circuit (addition means)
16, 57 Transmission data buffer control circuit (transmission means)
18 Frame generation circuit 19, 60 Frame detection circuit 20 ACK reception circuit 21, 62 Retransmission timer (discriminating means)
54 Data block dividing circuit (address generating means, dividing means)
61 ACK / NACK receiver circuit 111 Frame inspection circuit (receiver)
112 SQN detection circuit (discriminating means)
113, 513 Write address detection circuit (storage control means)
114, 514 Reception data buffer control circuit 115 Reception data buffer (storage means)
116 ACK generation circuit 118, 518 Frame generation circuit 512 Data block inspection circuit 516 ACK / NACK reception circuit

The best mode of the present invention is realized by generating a write address required on the data receiving side on the data transmitting side and transmitting the write address to the receiving side.
Specifically, the data transmission device includes an input unit that sequentially inputs data in units of data transmission, and an address generation unit that generates a write address for storing the data for each data transmission unit in a reception-side storage unit. Adding means for adding the generated write address to the data for each data transmission unit; and transmitting means for sequentially transmitting the data to which the write address has been added by the adding means in the data transmission unit. It becomes. Further, the data receiving device adds the data sequentially received by the receiving means, the receiving-side storage means, and the receiving means to the data transmitted from the transmitting means in the data transmission unit. Storage control means for storing in the storage position of the receiving-side storage means designated by the written address.

  Another embodiment of the data transmission apparatus includes an input unit that sequentially inputs data in variable-length data transmission units, a measurement unit that measures the data length of the data for each input data transmission unit, and the data Address generation means for calculating and generating a start value of a write address for storing the data for each transmission unit in the reception-side storage means based on the start value of the write address given to the immediately preceding data and the data length; Adding means for adding the start value of the write address calculated and generated by the address generation means to the data for each data transmission unit; and adding the data to which the start value of the write address is added by the addition means. Transmitting means for sequentially transmitting in units of data transmission. In another form of the data receiving apparatus, the receiving unit that receives the data transmitted from the transmitting unit in units of the data transmission unit, the receiving-side storage unit, and the data sequentially received by the receiving unit, Storage control means for storing in the storage position of the receiving storage means designated by the leading value of the write address added to the data.

Embodiment 1

1 is a block diagram showing an electrical configuration of a communication system having a write address notification type retransmission control function according to Embodiment 1 of the present invention, and FIG. 2 is a transmission of the communication system having the same write address notification type retransmission control function. FIG. 3 is a diagram illustrating a configuration example of a storage area of a data buffer, FIG. 3 is a diagram illustrating a configuration example of a reception data buffer of a communication system having the same write address notification type retransmission control function, and FIG. It is a figure which shows the structural example of the frame format transmitted / received by the communication system which has a retransmission control function.
The communication system 1 having a write address notification type retransmission control function according to this embodiment relates to a system that can eliminate the complexity of write / read processing of a received data buffer before and after retransmission of data performed when an error occurs in received data. 1, the data transmission device 10 and the data reception device 110 include a transmission path 30 from the data transmission device 10 to the data reception device 110, and a transmission path 130 from the data reception device 110 to the data transmission device 10. Connected with.

  Then, the data transmitting apparatus 10 includes an SQN adding circuit 11, a frame length counting counter 12, a write address (WADR) calculating circuit 13, a transmission data buffer 14, a write address (WADR) adding circuit 15, and a transmission data buffer. The control circuit 16, the frame generation circuit 18, the frame inspection circuit 19, the ACK reception circuit 20, and the retransmission timer 21 are configured, while the data reception device 110 includes the frame inspection circuit 111 and the SQN detection. A circuit 112, a write address (WADR) detection circuit 113, a reception data buffer control circuit 114, a reception data buffer 115, an ACK generation circuit 116, a reception data buffer size notifying means 117, and a frame generation circuit 118; Configured.

First, each of each component of the data transmission apparatus 10 mentioned above is demonstrated.
The SQN addition circuit 11 responds to the input K data (K is a positive integer of 1 or more) (data for each data transmission unit) for each frame (data transmission unit) in response to the input Kth variable length. This is a circuit that adds a transmission sequence number incremented by 1 (SQN (K): K is a positive integer of 1 or more) to the data for frame K and supplies it to the transmission data buffer 14.

The frame length counting counter 12 is a circuit that counts the payload data size L (K) (data length) of the frame K in response to the input frame K data and supplies it to the write address calculation circuit 13. The address calculation circuit 13 calculates WADR (K) WADR (K) as the write address start address (hereinafter referred to as the write address start value) of the frame K to the reception data buffer 115 by the following formula: WADR (K) = WADR (K−1) + L ( K-1) ...... (1)
However, WADR (K-1) is the write address head value of the immediately preceding frame K-1, and L (K-1) is the payload data size of the frame K-1.
This is a circuit that calculates and supplies the write address head value to the transmission data buffer 14. The write address calculation circuit 13 also performs control so that WADR (K) does not exceed the reception data buffer size Bmax.

The transmission data buffer 14 stores the data for frame K, the SQN number, and the write address head value for each frame. On the other hand, the transmission data buffer 14 receives the frame K in response to a read instruction given from the transmission data buffer control circuit 16 via the read control line 17. Storage means for reading out the data for use, the SQN number, and the write address head value and supplying them to the write address (WADR) adding circuit 15.
As shown in FIG. 2, the storage mode of frames in the transmission data buffer 14 stores the SQN number of each frame, the write address head value WADR (K), and payload data in order from the lowest transmission SQN number. It is like going. In FIG. 2, SQN (1) is written at the head of the address. However, when the transmission data buffer 14 has a ring memory configuration, SQN (1) is not always stored at the head of the address.

The write address (WADR) addition circuit 15 is a circuit that sets the transmission SQN (K) and WADR (K) received from the transmission data buffer 14 in the transmission SQN area and WADR area of each frame and transfers them to the transmission data buffer control circuit 16 It is.
The transmission data buffer control circuit 16 transfers the frame received from the write address addition circuit 15 to the frame generation circuit 18, while the SQN received from the ACK reception circuit 20 when the timer corresponding to the reception SQN number of the retransmission timer 21 has not timed out. In addition to releasing the payload data storage area corresponding to the number to enable writing of another frame, when receiving a retransmission instruction from the retransmission timer 21, a read instruction is sent to the transmission data buffer 14 via the read control line 17. This is a control means for reading again the frame (SQN (K), WADR (K) and payload data) corresponding to the SQN number received from the ACK receiving circuit 20 from the transmission data buffer 14 and passing it to the frame generation circuit 18.

The frame generation circuit 18 is a circuit that adds a header and a trailer to the frame from the transmission data buffer control circuit 16 and transmits the frame to the downstream transmission path 30 and transfers the transmission SQN number to the retransmission timer 21.
The format of the variable length frame transferred via the downstream transfer path 30 is shown in FIG. The frame K includes a header area, a transmission SQN value (K), a write address head value WADR (K), payload data, and a trailer. Among these, the header portion may include the length information of the payload, and the length information of the payload may not be included in the frame header as in Ethernet (registered trademark) prescribed by the IEEE 802.3 committee. It may be a frame. An example of the trailer added by the frame generation circuit 18 is a CRC value for frame error.

  The retransmission timer 21 starts counting the timer corresponding to the transmission SQN number received from the frame generation circuit 18 and monitors whether the timer corresponding to the reception SQN number received from the ACK reception circuit 20 described later has timed out. Control circuit means for sending out the SQN number and the retransmission instruction to the transmission data buffer control circuit 16 when the ACK receiving circuit 20 does not receive the received SQN value and times out after a predetermined time elapses.

The frame check circuit 19 performs CRC check on the ACK frame received via the uplink transmission path 130 to confirm the presence / absence of a frame error, transfers the ACK frame to the ACK reception circuit 20, and is received from the uplink transmission path 130. The Bmax notification frame is transferred to the write address calculation circuit 13.
The ACK reception circuit 20 is a circuit that extracts the reception SQN number set in the ACK frame received from the frame check circuit 19 and transfers it to the transmission data buffer control circuit 16 and the retransmission timer 21.

Next, each component of the data receiving apparatus 110 described above will be described.
The frame inspection circuit 111 inspects the header and trailer (CRC value) of the frame received via the downlink transfer path 30 and transfers the frame to the SQN detection circuit 112 if it is normal reception. This circuit discards the frame if there is an abnormality.
The SQN detection circuit 112 is a circuit that extracts the SQN number set in the received frame and transfers it to the ACK generation circuit 116 and transfers the frame to the write address (WADR) detection circuit 113. The write address detection circuit 113 is a circuit that extracts the write address head value (received WADR (K) value) of the received frame and transfers the write address head value and the frame to the received data buffer control circuit 114.

The reception data buffer control circuit 114 is a circuit that controls writing of the received frame to the reception data buffer 115 based on the received write address head value. The reception data buffer 114 is a circuit unit that stores the payload data of the received frame based on the received write address head value, and sends the reception data buffer size Bmax to the reception data buffer size notification unit 117.
As shown in FIG. 3, the storage mode of the frames in the reception data buffer 115 is such that the payload data of each frame can be stored in order from the youngest reception SQN number. In FIG. 3, SQN = 1 is written at the head of access. However, when the reception data buffer 115 has a ring memory configuration, SQN (1) is not always stored at the head of the address.

The ACK generation circuit 116 is a circuit that generates ACK frame payload data from the received SQN value received from the SQN detection circuit 112 and transfers this to the frame generation circuit 118. The reception data buffer size notification unit 117 is a notification unit that generates a notification frame of the reception data buffer size Bmax received from the reception data buffer 115 and transfers it to the frame generation circuit 118.
The frame generation circuit 118 sends the ACK frame payload data received from the ACK generation circuit 116 to the upstream transfer path 130 as an ACK frame (also referred to as normal reception notification), and the reception data buffer size from the reception data buffer size notification means 117. This is a circuit for sending a Bmax notification frame to the upstream transfer path 130.

Next, the operation of this embodiment will be described with reference to FIGS.
In the communication system 1 having the write address notification type retransmission control function of this embodiment, the buffer size Bmax of the reception data buffer 115 is notified from the data reception device 110 to the data transmission device 10 prior to frame transmission / reception. . This notification is performed by sending a Bmax notification frame in which the Bmax value is stored in the payload to the write address calculation circuit 13 via the frame generation circuit 118, the upstream transmission path 130, and the frame inspection circuit 19. This notification may be performed only once if the buffer size of the reception data buffer 115 is not changed.

First, the operation of the data transmitting apparatus 10 after the notification of the buffer size Bmax will be described.
When frame K data (K is a positive integer of 1 or more) is input to the SQN adding circuit 11, the SQN adding circuit 11 increments the transmission sequence number (SQN (K): K is 1) for each frame. The above positive integer) is added to the frame K data and transferred to the transmission data buffer 14.
Each frame data is input to the frame length counter 12. The frame length counting counter 12 counts the payload data size L (K) of the frame K in response to the input frame data and supplies it to the write address calculation circuit 13.

  The write address calculation circuit 13 calculates the write address head value WADR (K) to the reception data buffer 115 from the WADR (K-1) and L (K-1) of the immediately preceding frame K-1 by the equation (1). The write address head value is transferred to the transmission data buffer 14. The write address calculation circuit 13 also performs control so that the calculated write address head value WADR (K) does not exceed the reception data buffer size Bmax.

The transmission data buffer 14 stores the data for frame K, the SQN number, and the write address head value for each frame, while in response to a read instruction from the transmission data buffer control counter 12 via the read control line 17. The write address head value, transmission SQN number, and frame K data are read and supplied to the write address (WADR) adding circuit 15.
As described above, an example of a manner of storing frames in the transmission data buffer 11 is to store the SQN number, the write address head value WADR (K), and the payload data in order from the youngest transmission SQN number. Although there is (FIG. 2), it is not restricted to this. For example, in FIG. 2, SQN (1) is written at the access head, but when the transmission data buffer 11 has a ring memory configuration, SQN (1) is not always stored at the address head.

The write address addition circuit 15 sets the transmission SQN (K) and WADR (K) received from the transmission data buffer 14 in the transmission SQN area and WADR area of each frame and transfers them to the transmission data buffer control circuit 16.
The transmission data buffer control circuit 16 transfers the frame received from the write address addition circuit 15 to the frame generation circuit 18.
The frame generation circuit 18 adds a header and a trailer to the frame from the transmission data buffer control circuit 16 and transmits the frame to the downstream transmission path 30. An example of a trailer added by the frame generation circuit 18 is a CRC value for a frame error.
The frame generation circuit 18 also transfers the transmission SQN number to the retransmission timer 21. The retransmission timer 21 starts counting the timer corresponding to the SQN number.

As described above, the frame transmitted to the downlink transmission path 30 is received by the data reception device 110.
When the frame inspection circuit 111 receives the frame, the frame inspection circuit 111 inspects the header and trailer (CRC value) of the frame. If the frame is normally received, the frame inspection circuit 111 transfers the frame to the SQN detection circuit 112. If there is an error, the frame is discarded.

The SQN detection circuit 112 extracts the SQN number (SQN (K)) set in the received frame, transfers it to the ACK generation circuit 116, and transfers the frame to the write address detection circuit 113.
The write address detection circuit 113 extracts the write address start value (received WADR (K)) of the received frame and transfers the write address start value and the frame to the received data buffer control circuit 114.
The reception data buffer control circuit 114 writes the received frame in the reception data buffer 115 based on the received write address head value.

As described above, when the data reception device 110 normally receives the frame, the reception SQN number (SQN (K)) is transferred from the SQN detection circuit 112 to the ACK generation circuit 116, and the ACK generated by the ACK generation circuit 116 is generated. The signal (ACK frame payload data) is transferred to a frame generation circuit 118 that generates an ACK frame.
The frame generation circuit 118 returns the generated ACK frame to the data transmission device 10 via the uplink transfer path 130.

In the data transmitting apparatus 10 that receives the ACK frame, the frame checking circuit 19 transfers the ACK frame to the ACK receiving circuit 20. The ACK reception circuit 20 obtains a reception SQN value from the ACK frame and sends it to the transmission data buffer control circuit 16 and the retransmission timer 21.
The retransmission timer 21 determines (determines) that the timer corresponding to the reception SQN value has not timed out, and in this case, does not send a retransmission instruction to the transmission data buffer control circuit 16.
In response to this, the transmission data buffer control circuit 16 releases the payload data storage area corresponding to the reception SQN value received from the ACK reception circuit 20 and enables writing of another frame.

Further, as described above, it is detected that the frame received by the data receiving apparatus 110 is abnormal, the frame is discarded, and the received SQN value is not sent from the SQN detection circuit 112 to the ACK generation circuit 116. In this case, In this case, no ACK frame is returned from the data receiving apparatus 110 to the data transmitting apparatus 10.
On the other hand, the retransmission timer 19 of the data transmission apparatus 10 monitors whether the timer corresponding to the SQN value of the transmission frame has timed out, and the transmission frame is discarded by the data reception apparatus 110 and When the timer corresponding to the SQN value times out, the retransmission timer 19 sends a retransmission instruction corresponding to the time-out SQN value to the transmission data buffer control circuit 16.

Upon receiving this retransmission instruction, the transmission data buffer control circuit 16 sends a read instruction to the transmission data buffer 14 via the read control line 17, and SQN (K), WADR (corresponding to the SQN number received from the retransmission timer 19. K) and the payload data are read again from the transmission data buffer 14 and passed to the frame generation circuit 18.
At this time, the frame K data, the SQN number, and the write address head value read from the transmission data buffer 14 are the frame K data, the SQN number, and the write address head value read when transmitting the discarded transmission frame. Is the same as the value.
Therefore, the storage location where the retransmitted frame is normally received by the data reception device 110 and written to the reception data buffer 115 will be written if it was written to the reception data buffer 115 without retransmission. It is the same as the memory location. That is, continuity of addresses is ensured. This also applies to reading from the reception data buffer 115.

  As described above, according to this embodiment, it is necessary to change the storage location depending on the presence / absence of retransmission, whether writing to or reading from the reception data buffer of the communication system having the write address notification type retransmission control function. Since it is possible to access the reception data buffer, it is possible to simplify the write or read processing in the reception data buffer, achieving a wider transmission band and especially a reduction in the circuit scale on the reception side. obtain.

Embodiment 2

  FIG. 5 is a block diagram showing an electrical configuration of a communication system having a write address notification type retransmission control function according to Embodiment 2 of the present invention, and FIG. 6 shows transmission / reception in the communication system having the same write address notification type retransmission control function. FIG. 7 is a diagram showing a storage mode in a transmission data buffer of a communication system having the same write address notification type retransmission control function, and FIG. 8 is a diagram showing the same write address notification type retransmission control function. It is a figure which shows the storage aspect in the reception data buffer of the communication system which has.

The configuration of this embodiment is greatly different from that of the first embodiment in that the frame payload is divided into a plurality of data blocks and retransmission control is performed for each data block.
That is, the communication system 1A having the write address notification type retransmission control function of this embodiment has a data block dividing circuit 54 between the SQN addition circuit 11 of the data transmission device 50 and the transmission data buffer 55 as shown in FIG. ACK / NACK receiving circuit 61 is provided between frame check circuit 60 and transmission data buffer control circuit 57, while SQN detecting circuit 112 of data receiving device 510 and write address detecting circuit (WADR detecting circuit) 513 A data block inspection circuit 512 is provided between them, and an ACK / NACK generation circuit 516 is provided between the SQN detection circuit 112 and the data block inspection circuit 512 and the frame generation circuit 518, and the main part thereof is configured.

As shown in FIG. 6, the data block dividing circuit 54 converts the input data for frame K (K is a positive integer of 1 or more) into N fixed-length data blocks (also referred to as fixed-length payload data) DATA ( K, n _K ) (one of n = 1, 2,..., N), and for each divided fixed-length payload data, a data block number (also referred to as a BNUM value) (BNUM (n _K ) ) And an address offset value O (n _K ), and transfers it to the transmission data buffer 55.

When the frame received from the frame check circuit 60 is an ACK frame, the ACK / NACK reception circuit 61 transmits the ACK type and reception SQN number (also referred to as reception SQN value) extracted from the ACK frame to the transmission data buffer control circuit 57 and the retransmission. When the received frame is a NACK frame to the timer 62, the NACK type extracted from the NACK frame, the received SQN value and the error data block number BNUM (n _K ) (also referred to as the BNUM value) are transmitted data buffer control circuit 57 and a circuit for transferring to the retransmission timer 62.

The data block inspection circuit 512 performs CRC inspection for each fixed-length payload, and when the data block is an error data block DATA (K, n _K ), the error data block number BNUM (n _K ) (both error BNM value) Is transferred to the ACK / NACK generation circuit 516, and when the data block is normal, the fixed-length data block DATA (K, n _K ) is replaced with the write address head value (reception WADR (K) value) and the data block. This is a circuit that transfers to the write address detection circuit 513 together with a corresponding (BNUM (K) compatible) address offset O (n _K ).

The ACK / NACK generation circuit 516 is a circuit that generates ACK / NACK frame payload data for a received frame from the reception SQN number from the SQN detection circuit 111 and the error BNUM value from the data block check circuit 512.
Specifically, the operation of the ACK / NACK generation circuit 516 generates an ACK signal when there is no error data block in the frame having the received SQN number, and transmits the ACK signal from the frame generation circuit 518 to the upstream transfer path 130 as an ACK frame. On the other hand, if there is an error data block DATA (K, n _K ), a NACK signal is generated and sent from the frame generation circuit 518 to the upstream transmission line 130 as a NACK frame (abnormal reception notification) of the error data block. .

Further, the following constituent elements of the constituent elements of the data transmission device 50 according to this embodiment are slightly different from the first embodiment.
The transmission data buffer 55 includes fixed-length payload data from the data block dividing circuit 54, fixed-length payload data number (BNUM (n _K )) and address offset value O (n _K ), and a write address from the write address calculation circuit 53. The head value (WADR (K)) is stored so as to be readable in units of these information.
The write address adding circuit 56 receives fixed length payload data, fixed length payload data number (BNUM (n _K) read from the transmission data buffer 55 in response to a read instruction given from the transmission data buffer control circuit 57 via the read line 58. )), The address offset value O (n _K ) and the write address head value (WADR (K)) are stored in the corresponding storage area of the frame to be transmitted and transferred to the transmission data buffer control circuit 57.

  The transmission data buffer control circuit 57 passes the frame from the write address addition circuit 56 to the frame generation circuit 18, and the release processing operation in response to the ACK type and reception SQN value from the ACK / NACK reception circuit 61 is the same. However, the data block retransmission processing operation in response to the retransmission instruction from the retransmission timer 62 and the NACK type, received SQN value, and BNUM value from the ACK / NACK receiving circuit 61 is different. That is, in the data block retransmission processing operation, the fixed length payload data corresponding to the BNUM value, the write address head value, and the address offset value in the frame specified by the received SQN value are to be retransmitted.

The frame check circuit 60 has a difference in transferring an ACK frame or a NACK frame received via the uplink transmission path 130 to the ACK / NACK receiving circuit 45.
The retransmission timer 62 is the same as transferring a retransmission instruction when an ACK frame is not received within a certain time to the transmission data buffer control circuit 57, but receives a NACK frame within a certain time or receives a NACK frame within a certain time. When the frame is not received, a retransmission instruction is transferred to the transmission data buffer control circuit 57.

Further, the following constituent elements of the constituent elements of the data receiving apparatus 510 of this embodiment are slightly different from those of the first embodiment.
The write address detection circuit 513 generates a write address [WADR (K) + O (n _K )] from the received WADR (K) value input from the data block inspection circuit 512 and the address offset value O (n _K ). This is a circuit that transfers the received data buffer control circuit 514 together with the corresponding fixed-length data block DATA (K, n _K ).
The reception data buffer control circuit 514 stores the fixed-length data block DATA (K, n _K ) input from the write address detection circuit 513 in the write address [WADR (K) + O (n _K )] of the reception data buffer 115. Circuit.
The frame generation circuit 518 is a circuit that transmits the ACK frame or NACK frame from the ACK / NACK generation circuit 516 and the Bmax notification frame from the reception data buffer size notification unit 117 to the uplink transmission path 130.
Since the constituent elements of this embodiment other than this constituent element are the same as those of the first embodiment, the same reference numerals are given to the same constituent portions, and the description thereof will be omitted.

Next, the operation of this embodiment will be described with reference to FIGS.
In the receiving system 1A of this embodiment, prior to frame transmission / reception, the data reception device 510 notifies the data transmission device 50 of the buffer size Bmax of the reception data buffer 115. This notification is performed by sending a Bmax notification frame in which the Bmax value of the buffer size is stored in the payload to the write address calculation circuit 13 via the frame generation circuit 518, the upstream transmission path 130, and the frame inspection circuit 60, as in the first embodiment. This notification need only be made once if the size of the reception data buffer 115 is not changed.

First, the operation on the transmission side of the communication system 1A in the state where the Bmax value of the buffer size is notified will be described.
When frame K data (K is a positive integer of 1 or more) is input to the SQN adding circuit 11, the SQN adding circuit 11 increments the transmission sequence number (SQN (K): K is 1) for each frame. The above positive integer) is added to the frame K data and supplied to the data block dividing circuit 54.
Each frame data is input to the frame length counter 12. The frame length counting counter 12 counts the payload data size L (K) of the frame K in response to the input frame data and supplies it to the write address calculation circuit 13.

  The write address calculation circuit 13 calculates the write address head value WADR (K) to the reception data buffer 115 from the WADR (K-1) and L (K-1) of the immediately preceding frame K-1 by the equation (1). The write address head value is transferred to the transmission data buffer 55. The write address calculation circuit 13 also performs control so that the calculated write address head value WADR (K) does not exceed the Bmax value of the received data buffer size notified by the Bmax notification frame supplied from the frame inspection circuit 60. Do.

As shown in FIG. 6, the data block dividing circuit 54 converts the input data for frame K into N fixed-length data blocks (fixed-length payload data) (also referred to as data blocks) DATA (K, n _K ). The data is divided, a data block number BNUM (n _K ) and an address offset value O (n _K ) are generated for each of the divided fixed-length data blocks DATA (K, n _K ), and the divided fixed-length data blocks DATA ( K, n _K ), data block number BNUM (n _K ), and address offset value O (n _K ) are transferred to the transmission data buffer 55.

The transmission data buffer 55 stores the SQN (K), WADR (K), data block, and BNUM (n _K ) and O (n _K ) for each data block for each frame in a readable manner. (See FIG. 6) On the other hand, the content of the read instruction given from the transmission data buffer control circuit 57 via the read control line 58, that is, the entire frame when transmitting a frame, or the data block when retransmitting a data block DATA (K, n _K ), WADR (K), and O (n _K ) are read and supplied to the write address (WADR) adding circuit 56.
As shown in FIG. 7, an example of a mode of storing frames in the transmission data buffer 55 is as follows. The SQN value (SQN (K)), the write address head value WADR (K), The block number BNUM (n _K ), the address offset value O (n _K ), and fixed-length payload data DATA (K, n _K ) are stored.

The write address (WADR) addition circuit 56 transmits the transmission SQN value received from the transmission data buffer 11 to each of the transmission SQN area, WADR area, BNUM area, and address offset area of each frame, WADR (K), BNUM (n _K ), and O (n _K ) is set and transferred to the transmission data buffer control circuit 57.
The transmission data buffer control circuit 57 transfers the frame received from the write address addition circuit 56 to the frame generation circuit 18.

The frame generation circuit 18 adds a header and a trailer to the frame from the transmission data buffer control circuit 57 and transmits the frame to the transmission path 30, and transfers the transmission SQN value to the retransmission timer 62. An example of a trailer added by the frame generation circuit 18 is a CRC value for a frame error.
The retransmission timer 62 starts counting the retransmission timer of the transmission SQN value received from the frame generation circuit 18 and starts monitoring whether the timer corresponding to the reception SQN value received from the ACK / NACK generation circuit 61 has timed out. .

Next, the operation on the receiving side of the communication system 1A will be described.
When the SQN detection circuit 112 receives a frame via the downlink transmission path 30, the SQN value set in the frame is extracted and transferred to the ACK / NACK generation circuit 516 and the frame is transferred to the data block check circuit 512. To do.

The data block inspection circuit 512 performs a CRC inspection for each data block of the frame. When the test result for the data block indicates that it is a normal data block, the write address detection circuit 513 uses the write address start value (received WADR (K)) and the address offset value as the write address for the data block. since the O _{(n K),} the as write address of the data block to generate a _{WADR (K) + O (n} K), the data block passes the data block and the write address to the receive data buffer controller 514 The data is stored in the write address of the reception data buffer 115.
Further, the ACK / NACK control circuit 516 generates an ACK signal from the received SQN value from the SQN detection circuit 112 and inputs the ACK signal to the frame generation circuit 518 as an ACK frame via the uplink transmission path 130. Send to.

The frame check circuit 60 of the data transmitting apparatus 50 transfers the ACK frame to the ACK / NACK receiving circuit 61, and transfers the ACK type and the received SQN value to the transmission data buffer control circuit 57 and the retransmission timer 62. The retransmission timer 62 does not output a retransmission instruction because the ACK type and the received SQN value are received within a certain time.
Receiving the ACK type and the received SQN value, the transmission data buffer control circuit 57 releases the payload storage area corresponding to the received SQN value to prepare for writing another frame.

If the check result for the data block indicates that it is an error data block DATA (K, n _K ), the data block check circuit 512 discards the data block and ACK / NACK BNUM (n _K ). Transfer to the generation circuit 516. The ACK / NACK check circuit 516 generates a NACK signal from the received SQN value input from the SQN detection circuit 112 and the BNUM value input from the data block check circuit 512, and transmits the NACK frame from the frame generation circuit 518 to the upstream transmission line 130. Send to.

When the frame check circuit 60 of the data transmission device 50 receives the NACK frame, the CRC check is performed to confirm that there is no frame error, and the frame is transferred to the ACK / NACK reception circuit 61. The ACK / NACK receiving circuit 61 extracts the NACK type, the received SQN value, and the BNUM value from the frame, and transfers them to the transmission data buffer control circuit 57 and the retransmission timer 62.
The retransmission timer 62 sends a retransmission instruction to the transmission data buffer control circuit 57 in response to receiving the NACK type, the received SQN value, and the BNUM value within a predetermined time. The retransmission timer 62 sends a retransmission instruction to the transmission data buffer control circuit 57 in response to not receiving the NACK type, the received SQN value, and the BNUM value within a predetermined time.

The transmission data buffer control circuit 57 uses the NACK type from the ACK / NACK reception circuit 61, the reception SQN value and the reception BNUM value, and the retransmission instruction from the retransmission timer 62, and the head of the write address for the frame determined by the reception SQN value. An instruction to read the value (WADR (K)), the data block data corresponding to the received BNUM value, and the address offset value is sent to the transmission data buffer 55 via the read line 58. Each piece of information read from the transmission data buffer 55 is framed by the frame generation circuit 18 and transmitted to the downstream transmission path 30.
The transmission data buffer control circuit 57 does not receive the NACK type, the reception SQN value, and the BNUM value within a predetermined time, and when a retransmission instruction is sent from the retransmission timer 62, the transmission data buffer control circuit 57 Perform retransmission control.

The data block check circuit 512 that has received the frame transmitted via the downlink transmission path 30 via the SQN detection circuit 112 of the data reception device 510 detects the write address when there is no error in the retransmitted data block of the frame. Transfer to circuit 513.
The write address detection circuit 513 performs the write address head value (reception WADR (K)) and the address offset value O (n _K ) as the write address for the data block in the same manner as described above for the case of normal reception of the data block. ), WADR (K) + O (n _K ) is generated as the write address of the data block, the data block and the write address are passed to the reception data buffer control circuit 514, and the data block is received by the reception data buffer 115. Is stored at the above write address.
Further, the ACK / NACK control circuit 516 returns an ACK frame for the data block data DATA (K, n _K ), which is an error data block, to the data reception device 50 via the frame generation circuit 518.

When the ACK / NACK receiving circuit 61 of the data transmitting apparatus 50 receives the ACK frame, the data block area notified by the ACK frame is released, and the corresponding data block of another frame can be written.
If there is no error data block other than the ACK frame for the data block data DATA (K, n _K ) that was the error data block, the frame area corresponding to the SQN value of the frame is released, and another frame Allows writing of payload data.

As described above, since the write address of the data block is determined for each data block, even if the data block is received in error and the data block is discarded, the data block received in the error data block is normally received. In this case, the write addresses in the address space (FIG. 8) of the reception data buffer 115 are consecutive addresses in the order of the sequence numbers.
Therefore, processing on the reading side of the reception data buffer 115 is facilitated, and downsizing and widening of the bandwidth can be enjoyed.
In FIG. 8, the write address head value WADR (K) + O (n _K ) in each frame is the write address of the reception data buffer 115 as it is. However, if the relative relationship of each frame does not change, WADR (K) Alternatively, an address obtained by uniformly adding an offset value may be used.

  Thus, according to this embodiment, the same effect as that of the first embodiment can be obtained also in the division of the payload of the frame to the receiving side of the communication system having the write address notification type retransmission control function. The effect is obtained in units of data blocks.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration of the present invention is not limited to these embodiments, and the design does not depart from the gist of the present invention. These changes are included in the present invention.
For example, in the embodiment, an example in which frame transmission or reception control is performed using a hardware configuration has been described. However, such control may be configured by software control.
In addition, when the frame is normally received, writing to the reception data buffer is performed. However, regardless of whether the reception is normal or abnormal, the writing is performed, and the frame that is retransmitted and normally received is overwritten. It may be.
Further, although an example in which the address offset value is added to each data block has been described, when the data block length is common, it is not always necessary to add it to each data block.
The write address may be generated by providing means other than measurement of the payload data size of the frame, for example, means for holding the size of fixed-length payload data. Further, the generation mode of the write address may not be based on the write address head value.

  The present invention can be applied to various communication systems that transmit and receive data in units of data transmission.

Claims (20)

On the data transmission side, a write address for storing data for each data transmission unit in the storage unit on the reception side is added to the data, and the data to which the write address is added is sequentially transmitted in the data transmission unit,
A data transmission method characterized in that the data received on the data receiving side is stored in the storage location of the receiving side storage means specified by the write address added to the data. On the data transmission side
Enter data sequentially in units of data transmission,
Generating a write address for storing the data for each data transmission unit in the receiving storage means;
Adding the generated write address to the data for each data transmission unit;
Sequentially transmitting the data with the write address added in the data transmission unit;
On the data receiving side,
A data transmission method comprising: sequentially receiving the data transmitted from the data transmission device and storing the data in a storage location of the receiving storage means specified by the write address added to the received data. On the data transmission side
Data is sequentially input to the data transmission device in variable-length data transmission units,
Measure and hold the data length of the data for each input data transmission unit,
The head value of the write address for storing the data for each data transmission unit in the receiving side storage means is calculated and generated based on the head value of the write address given to the immediately preceding data and the data length,
Adding the calculated first value of the write address to the data for each data transmission unit;
The data to which the head value of the write address is added is sequentially transmitted in the data transmission unit,
On the data receiving side,
Data that sequentially receives the data transmitted from the data transmission side, and stores the data in a storage location of the reception side storage means specified by a head value of the write address added to the received data Transmission method.   On the data receiving side, it is determined whether or not the data for each data transmission unit has been normally received.When the result of the determination indicates that normal reception is not received, the data receiving side receives a notification from the data receiving side, and 4. The data transmission method according to claim 2, wherein the data transmission side retransmits the data of the data transmission unit that has not been normally received. On the data transmission side, the data for each data transmission unit is divided into a predetermined number of data blocks, the head value of the write address is added to the data for each data transmission unit, and the data block for each data block A number and an offset value from the start value of the write address, and sequentially transmit the data to which the start value of the write address, the data block number and the offset value are added, in the data transmission unit,
4. The data transmission method according to claim 3, wherein the data receiving side stores the data block in a storage position of the receiving side storage means based on a head value of the write address and the offset value.   6. The data transmission method according to claim 5, wherein the data block is a fixed-length data block.   The data receiving side determines whether or not data has been normally received for each data block. When the result of the determination is that normal reception is not indicated, the data receiving side receives a notification from the data receiving side, and 6. The data transmission method according to claim 5, wherein the transmitting side retransmits the data block that has not been normally received. A data transmission device for sequentially transmitting the data in units of the data transmission, to which the write address for storing the data for each data transmission unit in the reception-side storage unit is added;
A data transmission system comprising: a data receiving apparatus for storing the data received sequentially in a storage position of the receiving storage means designated by the write address added to the data. Input means for sequentially inputting data in units of data transmission;
Address generating means for generating a write address for storing the data for each data transmission unit in the receiving storage means;
An adding means for adding the generated write address to the data for each data transmission unit;
A data transmission device comprising: transmission means for sequentially transmitting the data, to which the write address is added by the addition means, in the data transmission unit;
Receiving means for receiving the data transmitted from the transmitting means of the data transmitting apparatus in the data transmission unit;
The receiving side storage means;
A data receiving device comprising storage control means for storing the data sequentially received by the receiving means at a storage location of the receiving storage means specified by the write address added to the data. A data transmission system. Input means for sequentially inputting data in variable-length data transmission units;
Measuring means for measuring the data length of the data for each input data transmission unit;
Address generation for generating and generating the start value of the write address for storing the data for each data transmission unit in the receiving-side storage means based on the start value of the write address and the data length given to the immediately preceding data Means,
Adding means for adding a head value of the write address calculated and generated by the address generating means to the data for each data transmission unit;
A data transmission device comprising: transmission means for sequentially transmitting the data, to which the leading value of the write address is added by the addition means, in the data transmission unit;
Receiving means for receiving the data transmitted from the transmitting means of the data transmitting apparatus in the data transmission unit;
The receiving side storage means;
A data receiving device comprising: storage control means for storing the data sequentially received by the receiving means in a storage position of the receiving-side storage means specified by a head value of the write address added to the data; A data transmission system characterized by comprising:   The data receiving apparatus has a determining means for determining whether or not the data for each data transmission unit is normally received, and when the determining means does not indicate normal reception within a predetermined time, the data receiving apparatus 11. The data transmission system according to claim 9, wherein the data transmission apparatus retransmits the data of the data transmission unit that has not been normally received in response to the notification from. The data transmitting apparatus includes a dividing unit that divides the data for each data transmission unit into a predetermined number of data blocks, and the adding unit adds a leading value of the write address to the data for each data transmission unit. And, for each data block, an offset value from the data block number and the start value of the write address is added,
The transmitting means sequentially transmits the data to which the head value of the write address, the data block number and the offset value are added by the adding means in the data transmission unit,
11. The data transmission system according to claim 10, wherein the data receiving device stores the data block in a storage location of the receiving-side storage unit based on a head value of the write address and the offset value.   The data transmission system according to claim 12, wherein the data block is a fixed-length data block.   The data receiving apparatus includes a determining unit that determines whether or not data is normally received for each data block, and when the determining unit does not indicate normal reception within a predetermined time, the data receiving apparatus 13. The data transmission system according to claim 12, wherein upon receiving the notification, the data transmitting apparatus retransmits the data block that has not been normally received.   15. A data transmission device used in the data transmission system according to claim 8.   15. A data receiving apparatus used in the data transmission system according to claim 8.   A control program for causing a computer to execute the data transmission method according to claim 1.   15. A control program for causing a computer to function as a component of the data transmission system according to claim 7.   16. A control program for causing a computer to function as means for constituting the data transmission apparatus according to claim 15.   A control program for causing a computer to function as means for constituting the data receiving apparatus according to claim 16.

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