JP3457084B2 - Packet bus controller - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet bus control device for controlling packet transfer order in a packet bus having a retry function.

[0002]

2. Description of the Related Art In an information processing apparatus, packet processing capability depends on bus transfer capability. A packet bus system is adopted to improve the bus transfer capability. In this packet bus system, a master sends a packet to a slave, and another master acquires the right to use the packet bus and sends the next packet without waiting for a response from the slave to the packet.

FIG. 11 shows an example of a conventional packet bus control device of this type. In the packet bus control device, the direct memory access (DMA) master 2 stores the packet in the memory 6 by performing direct access to the memory 6 in the processor 5 through the packet bus master 3a, the packet bus 1, and the packet bus slave 4. ) Or reading a packet from the memory 6 (packet fetch).

In this case, the packet bus master 3a sends the packet from the DMA master 2 to the packet bus slave 4 through the packet bus 1. When the packet bus slave 4 receives the packet, it returns a normal response to the packet bus master 3a. If no packet is received, the packet bus slave 4 returns a retry response to the packet bus master 3a through the packet bus 1, and the packet bus master 3a sends the same packet again to the packet bus slave 4.

The packet bus controller performs a DMA end interrupt after performing a DMA transfer of a packet through the packet bus 1 having a retry function.

[0006]

However, the packet bus control device has the following problems. Figure 11
As shown in, the packet bus master 3 a sends the DMA store packet from the DMA master 2 to the packet bus slave 4 through the packet bus 1 (). Next, DM
The packet bus master 3a sends an interrupt packet for ending the DMA transfer from the A master 2 to the packet bus 1
To the packet bus slave 4 through ().

Next, since the packet cannot be received in the internal state of the packet bus slave 4, the packet bus slave 4
Returns a retry response to the packet bus master 3a (). Further, when the packet bus slave 4 sends the interrupt packet to the processor 5 (), the processor 5 ends the DMA transfer.

Next, the packet bus slave 4 transfers the retryed DMA store packet from the packet bus master 3a to the processor 5 (). DMA like this
The interrupt packet is received by the processor 5 before the store packet. That is, the order of the DMA store packet and the interrupt packet is exchanged. For this reason, the processor 5 ends the DMA transfer although the transfer of the DMA store packet to the memory 6 is not completely completed.

Therefore, the channel (packet bus master 3a) is transmitted from the packet bus slave 4 side using software.
It was confirmed whether or not the DMA transfer was completed by reading the status of the side. Therefore, even after the DMA end interrupt is generated, it takes extra time to read the channel status before confirming the normal end of the DMA transfer.

It is an object of the present invention to provide a packet bus control device which maintains packet order consistency and improves packet bus efficiency.

[0011]

The packet bus control device of the present invention adopts the following means in order to solve the above problems.

<Summary of the Device of the Present Invention> As shown in FIG. 1, the packet bus control device of the present invention sends a data packet from the master 2 by the direct memory access transfer and an interrupt packet for ending the transfer to the packet bus. A packet bus control device for transferring data packets from the master 2 to the slave 4 via a data packet storage unit 31 for storing data packets from the master 2, an interrupt packet storage unit 32 for storing interrupt packets from the master 2, Address information of the packet stored in the data packet storage unit 31 and the interrupt packet storage unit 32, packet type information, packet transmission waiting state information from the master 2 to the slave 4, and a response waiting state for the packet from the slave 4 Management unit 3 that manages information and
3 and a read control unit 34 that reads out a packet from one of the data packet storage unit 31 and the interrupt packet storage unit 32 based on the content managed by the management unit 33 and sends the packet to the slave 4. The read control unit 34, after receiving the interrupt packet after transmitting the data packet to the slave 4, after confirming that the response from the slave 4 to the transmitted data packet is a normal response, The interrupt packet is transmitted (corresponding to claim 1).

The point is that the master transmitting the data packet and the interrupt packet to the packet bus is controlled so as not to transmit the interrupt packet until the normal response of the DMA transfer is returned.

The structure will be described below. (Data Packet Storage Unit) The data packet storage unit 31 stores the data packet from the master 2.
For example, a buffer memory or the like. (Interrupt packet storage unit) Interrupt packet storage unit 3
Reference numeral 2 stores an interrupt packet from the master 2, and is, for example, a buffer memory or the like. (Management unit) The management unit 33 is the data packet storage unit 31.
Address information, packet type information, packet transmission waiting state information from the master 2 to the slave 4, and the slave 4 stored in the interrupt packet storage unit 32
For managing the response waiting state information for the packet from, for example, a plurality of shift registers or a buffer memory. (Read Control Unit) The read control unit 34 includes the management unit 3
Packets are read from one of the data packet storage unit 31 and the interrupt packet storage unit 32 based on the contents managed in 3, and sent to the slave 4.

The read control unit 34, after receiving the interrupt packet after transmitting the data packet to the slave 4, confirms that the response from the slave 4 to the transmitted data packet is a normal response. , Sending the interrupt packet. The read control unit 34 is, for example, a function realized by the central processing unit executing a program stored in the memory, that is, software.

The present invention can be realized by adding the following additional components. The other additional component is that the data packet is a store packet stored in the memory provided in the slave by the transfer (corresponding to claim 2).

With respect to other additional components, the management unit 33 has a plurality of priority storage units for storing the information regarding the data packet and the interrupt packet in the order received from the master 2. When the response from the slave 4 to the transmitted packet is a normal response, the priority storage unit corresponding to the transmitted packet erases the information, and the priority storage units other than the erased priority storage unit are erased. All priority storages have a priority of 1
It is to move up (corresponding to claim 3).

[0018] The other additional component is that, when the response from the slave 4 to the transmitted packet is a retry response, the priority storage unit corresponding to the transmitted packet stores the information. It is not erased, and the priority storage unit does not advance the priority.

The read control unit 34 reads the data packet from the data packet storage unit 31 again based on the information in the priority storage unit corresponding to the transmitted packet and sends it to the slave 4 (claim). (Corresponding to item 4).

The other additional component is that, when the read control unit 34 receives a new packet that is not an interrupt packet after receiving the interrupt packet, it sends the new packet before transmitting the interrupt packet. To the slave 4 (corresponding to claim 5).

[0021]

According to the present invention, the management unit 33 waits for the packet address information stored in the data packet storage unit 31 and the interrupt packet storage unit 32, the packet type information, and the packet transmission from the master 2 to the slave 4. It manages the state information and the response waiting state information for the packet from the slave 4.

Then, based on the contents managed by the management unit 33, the read control unit 34 sends the data packet to the slave 4
When the interrupt packet is received after being transmitted, the interrupt packet is transmitted after confirming that the response to the transmitted data packet from the slave 4 is a normal response.

In other words, the order of interrupt packets and data packets on the packet bus 1 can be prevented from changing, and the transfer process does not end before the data packets are stored in the memory. Further, since the work of confirming the end of transfer is unnecessary, no extra time is required.

If the response from the slave 4 is a normal response, the priority storage unit corresponding to the transmitted packet erases information, and all the priority storage units other than the erased priority storage unit Since the priority is increased by one, the next received packet can be read according to the information in the priority storage unit having the highest priority.

Further, when the response from the slave 4 is a retry response, the priority storage unit corresponding to the transmitted packet does not erase the information, the priority storage unit does not raise the priority, and the read control unit. 34 again sends the data packet from the data packet storage unit 31 to the slave 4 based on the above information. That is, the packet bus use waiting time can be shortened by increasing the transmission priority of the packet that receives the retry response.

When the read control unit 34 receives a new packet that is not an interrupt packet after receiving the interrupt packet, the read control unit 34 sends the new packet to the slave 4 before sending the interrupt packet. The transmission waiting time can be shortened and the bus can be effectively used.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a packet bus control device of the present invention will be described below with reference to the drawings. FIG. 2 is a configuration block diagram showing an embodiment of the packet bus control device of the present invention.
The packet bus control device includes a packet bus 1, a packet bus master 3 and a packet bus slave 4 connected to the packet bus 1, a DMA master 2 connected to the packet bus master 3, and a processor 5 connected to the packet bus slave 4. .

The DMA master 2 is a packet bus master 3,
By performing direct access to the memory 6 in the processor 5 through the packet bus 1 and the packet bus slave 4, packet store or packet fetch is performed.

The packet bus master 3 sends the DMA store packet and interrupt packet from the DMA master 2 to the packet bus slave 4 through the packet bus 1.
The packet bus master 3 receives the normal response and the retry response to the packet from the packet bus slave 4, and in the case of a retry response, transfers the same DMA packet to the packet bus slave 4 again.

The packet bus slave 4 is the packet bus 1
The DMA store packet and the interrupt packet from the packet bus master 3 are sent to the processor 5 through the. The packet bus slave 4 returns a normal response and a retry response to the packet to the packet bus master 3.

The processor 5 stores the input DMA store packet in the memory 6, and terminates the DMA transfer by the input interrupt packet. FIG. 3 is a detailed configuration diagram of the packet bus master 3. In FIG. 3, the packet bus master 3 includes a DMA buffer 31 connected to the DMA master 2, an interrupt buffer 32 connected to the DMA master 2, and a plurality of shift registers 33-1 to 33-33 connected to the DMA master 2. -N and DM
A buffer 31, an interrupt buffer 32, a buffer read controller 34 connected to the shift registers 33-1 to 33-N, and a packet bus transmission connected to the DMA buffer 31, interrupt buffer 32, and buffer read controller 34 And a part 35.

The DMA buffer 31 has a plurality of buffer addresses and stores the DMA packet from the DMA master 2. The interrupt buffer 32 has a plurality of buffer addresses different from the plurality of buffer addresses of the DMA buffer 31, and stores the interrupt packet from the DMA master 2.

A plurality of shift registers 33-1 to 33-N
Holds the packet status indicating the packet transmission wait or response wait in the first bit, the packet type in the second bit, and the buffer address in the third bit.

A plurality of shift registers 33-1 to 33-N
, The shift register 33-1 has the first priority read by the buffer read controller 34,
The shift register 33-N has the Nth priority.

The buffer read controller 34 determines the next transmission packet from the packets stored in the DMA buffer 31 and the interrupt buffer 32 based on the contents held in the shift registers 33-1 to 33-N. .
The packet bus transmitter 35 transfers the packet read by the buffer read controller 34 to the packet bus 1.

Next, the operation of the embodiment thus configured will be described with reference to the drawings. FIG. 4 is a flowchart showing the operation of the packet bus control device. FIG. 5 is a flowchart showing the operation of the buffer read control unit.

First, the packet bus master 3 receives a DMA store packet from the DMA master 2 (step 1
01). Next, the packet bus master 3 becomes the DMA master 2
The interrupt packet is received from (step 102).

Then, in the packet bus master 3 shown in FIG. 6, the DMA buffer 31 stores the DMA store packet (DW packet) from the DMA master 2 at the buffer address A1.

At the same time, the shift register 33-
1 stores a packet state S (waiting for transmission), a packet type DW, and a buffer address A1 as store information of the DW packet in the DMA buffer 31.

Next, the interrupt buffer 32 stores the interrupt packet (IT packet) from the DMA master 2 in the buffer address A5. At the same time, the shift register 33-2 sends the IT to the interrupt buffer 32.
A packet state S (waiting for transmission), a packet type IT, and a buffer address A5 are stored as packet store information. It should be noted that each packet is stored from the shift register having the highest priority in the order of reception.

Next, the buffer read control unit 34 determines the order of packets to be read from the DMA buffer 31 and the interrupt buffer 32 based on the contents sequentially stored in the plurality of shift registers (step 103). The packet read order by the buffer read control unit 34 is determined according to FIG.

First, the buffer read control unit 34 determines whether the state of the packet stored in the shift register 33-1 having the priority 1 is waiting for a response, waiting for transmission, or invalid (step 111).

When the state of the packet of priority 1 is the transmission waiting S, the buffer read control unit 34 reads the packet stored in the buffer indicated by the address of priority 1 and waits for the response of the packet state. (Step 112).

In the example shown in FIG. 7, since the buffer read control unit 34 stores the state of the packet stored in the shift register 33-1 having the priority 1 in the waiting S state, the priority 1
The DW packet stored in the DMA buffer 31 indicated by the address A1 is read and the state of the packet is changed from the transmission waiting S to the response waiting O.

Then, the packet bus transmitter 35 is
The A store packet (DW packet) is transmitted to the packet bus slave 4 via the packet bus 1 (step 104 in FIG. 4).

Next, a plurality of shift registers 33-1 to 3-3
3-N waits for a response from the packet bus slave 4 (step 105), and shift registers 33-1 to 33
-N determines whether the response is a normal response or a retry response (step 106).

When the response from the packet bus slave 4 is a normal response, the contents of the transmission shift register are cleared, the shift registers having a lower priority than the cleared shift register are shifted one by one, and the priority of the shift register is given. The rank is advanced by one (step 107).

In the example shown in FIG. 8, the contents of the shift register 33-1 having the priority 1 are cleared and the contents of the shift register 33-2 having the priority 2 are shifted to the shift register 33-1 having the priority 1. Shift register 3 with priority 1
The contents of 3-1 are the information regarding the interrupt packet, that is, the transmission waiting S, the packet type IT, and the buffer address A5.

Here, as shown in FIG. 9, the buffer read control unit 34 reads the IT packet from the interrupt huff buffer 32 according to the contents of the shift register 33-1 having the priority 1, and the packet bus transmission unit 35 reads the IT packet. It is sent to the packet bus slave 4 (step 108 in FIG. 4). Further, the shift register 33-1 is set to the response waiting O (step 112 in FIG. 5).

On the other hand, when the response is the retry response in step 106, the response waiting O of the shift register 33-1 is changed to the transmission waiting S as shown in FIG. 10 (step 109). At this time, the priority of each shift register does not change, and the shift register 3
The contents of 3-1 are the transmission waiting S, the packet type DW, and the buffer address A1.

Then, the process returns to step 103, and the processes from step 103 to step 105 are performed again.
That is, the buffer read control unit 34 causes the DMA buffer 3
The DMA store packet is read from 1 and transmitted. Therefore, the retry DMA store packet is read and transmitted.

On the other hand, when the state of the packet having the priority 1 is the response waiting O, the buffer read control unit 34 determines that the state of the packet stored in the shift register 33-2 having the priority 2 is the response waiting or the transmission waiting. It is determined whether it is invalid or invalid (step 113).

When the state of the packet of priority 2 is the transmission waiting S, the buffer read control unit 34 determines whether the packet type is interrupt (step 11).
4). If the packet is not an interrupt packet, the buffer read control unit 34 reads the packet stored in the buffer indicated by the address of priority 2 and sets the state of the packet to wait for response (step 115). That is, when the DMA store packets are set to the priority 1 and the priority 2, the processing of step 115 is performed.

Next, if the packet is an interrupt packet, the buffer read control unit 34 determines whether the packet of priority 1 is a DW packet (DMA store packet) (step 116).

If the packet of priority 1 is not a DW packet, for example, if it is a DMA fetch (read from memory to master) or an interrupt packet, the packet order may be reversed, so the processing of step 115 is performed. Proceed to.

When the packet with the priority 1 is a DW packet, the contents of the shift register 33-2 with the priority 2 are prohibited from being read so that the order of the packets on the packet bus 1 is not reversed. Since the contents of the shift register 33-2 of rank 2 is read-protected, the buffer read control unit 34 determines whether the state of the packet of priority 3 is waiting for transmission, waiting for response, or invalid (step 11
8). Then, step 119 is processed in the same manner as step 114, and step 120 is processed in the same manner as step 115.

If the packet state is invalid in steps 111, 113 and 118, step 1
Proceed to 17. Then, in step 121, it is judged whether any of the packets having the priorities 1 and 2 is a DW packet. Such processing is continued from the priority of 4 to N.

As described above, the packet bus master 3 controls so that the interrupt packet is not transmitted until a normal response to the DMA store packet is returned from the packet bus slave 4, so that the order of the packets on the packet bus 1 is prevented from being changed. it can. Further, since the order of the DMA store packet and the interrupt packet is guaranteed, it is not necessary to confirm the DMA end by software, and it does not take extra time.

Further, since the retry response is returned to the shift register 33-1 having the priority 1, the DMA store packet is transmitted next with the priority 1, so that the waiting time of the interrupt packet can be minimized.

Further, the first received packet is DMA
It is a packet that allows reversal of order such as fetch and interrupt packet, and the next received new packet is DMA.
It is a store packet. In this case, the buffer read control unit 34 sends the new packet to the slave 4 before sending the interrupt packet.

As a result, the packet transmission waiting time can be shortened and the bus can be effectively used.

[0062]

According to the present invention, when the read control unit receives the interrupt packet after transmitting the data packet to the slave based on the contents managed by the management unit, the response to the data packet transmitted from the slave is After confirming that the response is normal, send an interrupt packet.

That is, the order of interrupt packets and data packets on the packet bus can be prevented from being changed,
The transfer process never ends before the data packet is stored in memory. Further, since the work of confirming the end of transfer is unnecessary, no extra time is required.

If the response from the slave is a normal response, the priority storage unit corresponding to the transmitted packet erases information, and all the priority storage units other than the erased priority storage unit have priority. Since the rank is moved up by one, the next received packet can be read according to the information in the priority storage unit having the highest priority.

Further, when the response from the slave is a retry response, the priority storage unit corresponding to the transmitted packet does not erase the information, the priority storage unit does not advance the priority, and the read control unit Based on the information, the data packet from the data packet storage unit is sent again to the slave. That is, the packet bus use waiting time can be shortened by increasing the transmission priority of the packet that receives the retry response.

Further, when the read control unit receives a new packet which is not an interrupt packet after receiving the interrupt packet, it sends the new packet to the slave before transmitting the interrupt packet. The waiting time can be shortened and the bus can be effectively used.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a packet bus control device of the present invention.

FIG. 2 is a diagram showing an embodiment of a packet bus control device of the present invention.

FIG. 3 is a configuration diagram showing a packet bus master in the embodiment.

FIG. 4 is a flowchart showing the operation of the packet bus control device.

FIG. 5 is a flowchart showing an operation of a buffer read control unit.

FIG. 6 is a diagram illustrating reception of a DMA store packet and an interrupt packet.

FIG. 7 is a diagram illustrating transmission of a DMA store packet.

FIG. 8 is a diagram illustrating a normal response of a DMA store.

FIG. 9 is a diagram illustrating transmission of an interrupt packet.

FIG. 10 is a diagram showing a retry response of a DMA store.

FIG. 11 is a diagram showing an example of a conventional packet bus control device.

[Explanation of symbols]

1 ... Packet bus 2 ... DMA master 3 ... Packet bus master 4 ... Packet bus slave 5 ... Processor 6 ... Memory 31 ... DMA buffer 32..Interruption buffer 33-1 to 33-N ... Shift register 34 .. Buffer read control unit 35 .. Packet bus transmitter

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenichi Kazuki 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Kenji Hoshi, 1015 Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kiyoshi Sudo 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takanori Kato, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) References 2-224542 (JP, A) JP-A-4-189049 (JP, A) JP-A-7-235951 (JP, A) JP-A-5-103017 (JP, A) JP-A-6-303278 (JP, A) JP-A-6-168196 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/40-12/417 H04L 12/00-12/26 H04L 12/50- 12/66 H04L 13/00

Claims (5)

(57) [Claims] 1. A packet bus control device for transferring a data packet from a master and an interrupt packet for terminating the transfer to a slave through a packet bus by direct memory access transfer, and storing the data packet from the master. A data packet storage unit, an interrupt packet storage unit for storing interrupt packets from the master, address information of packets stored in the data packet storage unit and the interrupt packet storage unit, packet type information, master to slave Management unit for managing the transmission waiting state information of the packet and the response waiting state information for the packet from the slave, and one of the data packet storing unit and the interrupt packet storing unit based on the contents managed by the managing unit. Packets from storage A read control unit for reading and transmitting the data packet to the slave, wherein the read control unit normally transmits a response to the transmitted data packet from the slave when the interrupt packet is received after transmitting the data packet to the slave. A packet bus control device, wherein the interrupt packet is transmitted after confirming that it is a response. 2. The packet bus control device according to claim 1, wherein the data packet is a store packet stored in a memory provided in the slave by the transfer. 3. The management unit has a plurality of priority storage units for storing the information about the data packet and the interrupt packet in the order received from the master, and a response to the transmitted packet from the slave is provided. If it is a normal response, the priority storage unit corresponding to the transmitted packet erases the information, and all the priority storage units other than the erased priority storage unit have one priority. The packet bus control device according to claim 1, wherein the packet bus control device is moved up. 4. When the response from the slave to the transmitted packet is a retry response, the priority storage unit corresponding to the transmitted packet does not erase the information and stores the priority. The unit does not raise the priority, and the read control unit again reads the data packet from the data packet storage unit based on the information of the priority storage unit corresponding to the transmitted packet and sends the data packet to the slave. The packet bus control device according to claim 3. 5. The read control unit, when receiving a new packet that is not an interrupt packet after receiving the interrupt packet, transmits the new packet to the slave before transmitting the interrupt packet. The packet bus control device according to any one of claims 1 to 4.