JPH07244997A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To enhance product yield without giving any hindrance to the making of the cost reduction of a dynamic RAM, etc., by realizing the dynamic RAM in which redundant word lines having a leakage defect can be used without increasing a chip area. CONSTITUTION:In the dynamic RAM, etc., provided with redundant word lines, a redundant decoder is provided with storage means, in short, fuses for indicating that the defect of a word line W1 allotted to a redundant word line WR1 is a leakage defect. Moreover, the decoder is made to have a function making the word line W1 and redundant word line WR1 selection states simultaneously when the defect of the word line W1 allotted to the redundant word WR1 is the leakage defect. Thus, even when the redundant word line WR1 allotted to the word line W1 having the leakage defect has a same leakage defect, this can be relieved by expanding a substantial information storage capacity of the memory cell to be twice.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a dynamic RA having a redundant word line.
The present invention relates to a technology that is particularly effective when used for M (Random Access Memory) or the like.

[0002]

2. Description of the Related Art A dynamic RAM having a memory array including word lines and bit lines arranged orthogonally and dynamic memory cells arranged in a lattice at intersections of the word lines and bit lines is provided. is there. In addition, a dynamic array is provided by providing a predetermined number of redundant word lines in a memory array such as a dynamic RAM and selectively replacing these redundant word lines with word lines in which a failure is detected to perform so-called defect relief. A method for increasing the product yield of RAM and the like is known.

On the other hand, by suppressing the power consumption as much as possible,
There are low power consumption dynamic RAMs and pseudo dynamic RAMs that enable battery backup. In these dynamic RAMs and the like, since it is necessary to suppress the data holding current to about several tens of microamperes (microamperes), memory cells that can meet a refresh time of 1 second or more are used, and memory cells that do not satisfy this are combined. The selected word line is replaced with a redundant word line as a word line having a leak failure.

Dynamic RA with redundant word lines
M is described in, for example, Japanese Patent Laid-Open No. 3-214669.

[0005]

In a conventional low power consumption type dynamic RAM or the like having a redundant word line,
When a redundant word line replaced with a word line having a leak failure has a similar leak failure, the dynamic RAM or the like is treated as a defective product, so that the product yield of the dynamic RAM or the like can be improved as expected. Can not. Further, if the number of redundant word lines is increased in order to deal with this, the chip area of a dynamic RAM or the like increases, which hinders cost reduction.

An object of the present invention is to provide a dynamic RAM or the like which can use a redundant word line having a leak failure without increasing its chip area.
Another object of the present invention is to improve the product yield of a dynamic RAM or the like having redundant word lines without impeding cost reduction.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like having redundant word lines, when a defective word line is designated, a redundant address decoder that selectively selects the corresponding redundant word line is assigned to the redundant word line. In addition to providing a storage means for indicating that the failure of is a leak failure, if the failure of the word line assigned to the redundant word line is a leak failure,
A function is provided in which a word line in which a leak failure is detected and a corresponding redundant word line are simultaneously selected. Further, non-inversion and inversion signals of complementary bit lines corresponding to the drain of the address selection MOSFET of the memory cell coupled to the word line in which the failure is detected and the drain of the address selection MOSFET of the memory cell coupled to the redundant word line. The redundant word lines are assigned to be complementary coupled to the lines.

[0009]

According to the above means, even if the redundant word line assigned to the word line having the leak fault has the same leak fault, the substantial information storage capacity of the memory cell is doubled and Can be rescued. As a result,
The product yield of a dynamic RAM or the like having redundant word lines can be increased without increasing the number of redundant word lines, that is, without hindering cost reduction.

[0010]

1 is a block diagram of an embodiment of a dynamic RAM to which the present invention is applied. Further, FIG. 2 shows a circuit diagram of an embodiment of the memory array and the sense amplifier included in the dynamic RAM of FIG. Based on these figures, the outline of the configuration and operation of the dynamic RAM of this embodiment will be described first. The circuit elements shown in FIG. 2 and the circuit elements forming the blocks shown in FIG.
al Oxide Semiconductor Fi
eld Effect Transistor: Metal oxide semiconductor type field effect transistor. In this specification, M
It is formed on one semiconductor substrate surface such as single crystal silicon by a manufacturing technique of an integrated circuit, which is a general term for an insulated gate field effect transistor (OSFET). In FIG. 2, a MOSFET having an arrow on its channel (back gate) portion is a P-channel type MOSFET, and is shown separately from an N-channel MOSFET without an arrow.

In FIG. 1, the dynamic RAM of this embodiment has a memory array MARY, which occupies most of the surface of a semiconductor substrate, as a basic constituent element. The memory array MARY is not particularly limited, but as shown in FIG. 2, m + 1 word lines W0 to Wm and two redundant word lines WR0 to W0 arranged in parallel in the vertical direction.
WR1 and n + 1 sets of complementary bit lines B0 * to Bn * arranged in parallel in the horizontal direction (here, for example, the non-inverted bit line B0T and the inverted bit line B0B are combined to form a complementary bit line B0 *. It is indicated by adding *, and the so-called non-inverted signal which is selectively set to high level when it is validated is indicated by adding T at the end of its name,
A so-called inverted signal or the like that is selectively set to low level when it is validated is indicated by adding B to the end of its name. The same shall apply hereinafter) and. At the intersections of these word lines, redundant word lines, and complementary bit lines, a total of (m + 3) × (n + 1) dynamic memory cells composed of information storage capacitors Cs and address selection MOSFETs Qa are arranged in a grid pattern.

Address selection MOSFETs of m + 3 memory cells arranged in the same column of the memory array MARY
The drain of Qa has corresponding complementary bit lines B0 * to Bn.
The non-inverted or inverted signal lines of * are alternately coupled with a predetermined regularity. In addition, the address selection MO of n + 1 memory cells arranged in the same row of the memory array MARY.
The gate of the SFET Qa has a corresponding word line W0 to Wm.
Alternatively, they are commonly coupled to redundant word lines WR0 to WR1. Further, a predetermined plate voltage VP is commonly supplied to the other electrodes of the information storage capacitors Cs of all the memory cells that form the memory array MARY. The plate voltage VP is equal to the power supply voltage VCC and the ground potential V.
It is set to an approximately midpoint potential with respect to SS.

The word lines W0 to Wm and the redundant word lines WR0 to WR1 forming the memory array MARY are X
It is coupled to the address decoder XD and is brought into a selected state selectively. The X address decoder XD includes i + 1-bit internal address signals X0 to X from the X address buffer XB.
i is supplied. Further, the redundant address decoder RD supplies the redundant word line drive signals XR0 to XR1 and the redundant switching signal XR, and the timing generation circuit TG supplies the internal control signal XDG. The internal address signals X0 to Xi are supplied to the redundant address decoder RD from the X address buffer XB. Further, the X address buffer XB is supplied with the X address signals AX0 to AXi in a time division manner through the address input terminals A0 to Ai, and the timing generation circuit TG supplies the internal control signal XL.

The X address buffer XB has an X address signal AX supplied via address input terminals A0 to Ai.
0 to AXi are fetched and held according to the internal control signal XL, and internal address signals X0 to Xi are formed based on these X address signals and supplied to the redundant address decoder RD and the X address decoder XD.

The redundant address decoder RD includes two sets of redundant address memories and redundant address comparison circuits provided corresponding to the redundant word lines WR0 to WR1 of the memory array MARY. Among them, the redundant address memory includes a fuse that is selectively cut off and holds the address of the word line assigned to the corresponding redundant word lines WR0 to WR1 because it has some trouble, that is, a defective address. Further, the redundant address comparison circuit is provided with a defective address supplied from the corresponding redundant address memory and an X address signal AX supplied from the outside at the time of memory access.
0 to AXi, that is, internal address signals X0 to Xi are compared and collated bit by bit, and when all these address signals match, the output signal, that is, the corresponding redundant word line drive signal XR0 to XR1 is selectively set to a high level. And

In this embodiment, each of the redundant address memories constituting the redundant address decoder RD is a memory for indicating that the fault of the word line assigned to the corresponding redundant word line WR0 to WR1 is a leak fault. Including means or fuses. Then, when the corresponding fuse is cut off, the redundancy switching signal XR is set to the high level in addition to the redundancy word line drive signals XR0 to XR1.

On the other hand, the X address decoder XD is selectively activated when the internal control signal XDG is at high level. In this operating state, when the redundancy switching signal XR is at the low level, the X address decoder XD decodes the internal address signals X0 to Xi to selectively set the corresponding word lines W0 to Wm of the memory array MARY to the selection level. To do. When the redundancy switching signal XR is at high level, the internal address signals X0 to Xi
Of the redundant word line drive signal XR0
~ XR1 corresponding redundant word lines WR0-WR1
As the selection level. As a result, the defective word line is selectively replaced with the corresponding redundant word line WR0 to WR1, and the defect relief is realized.

In this embodiment, the X address decoder XD corresponds to the internal address signals X0 to Xi when the redundancy switching signal XR is at the low level and any of the redundancy word line drive signals XR0 to XR1 is at the high level. And the redundant word line drive signals XR0 to XR
The redundant word lines WR0 to WR1 corresponding to 1 are simultaneously selected. As a result, complementary bit lines B0 * to Bn *
Is connected to two memory cells connected to the selected word line and the redundant word line, and a minute read signal according to the data held in these memory cells is output. The effect obtained by simultaneously selecting the word line in which the failure is detected and the redundant word line corresponding thereto in this manner will be described later in detail.

Next, the complementary bit lines B0 * to Bn * forming the memory array MARY are coupled to the corresponding unit circuits of the sense amplifier SA. For the sense amplifier SA, Y
The address decoder YD supplies the bit line selection signals YS0 to YSn of n + 1 bits to the timing generation circuit T.
An internal control signal PA is supplied from G. The Y address decoder YD is supplied with the internal address signals Y0 to Yi of i + 1 bits from the Y address buffer YB and the internal control signal YDG from the timing generation circuit TG.
The Y address buffer YB is supplied with the Y address signals AY0 to AYi in a time division manner via the address input terminals A0 to Ai, and the timing control circuit TG supplies the internal control signal YL.

The Y address buffer YB is supplied with Y address signal AY via address input terminals A0 to Ai.
0 to AYi are fetched and held according to the internal control signal YL, and internal address signals Y0 to Yi are formed based on these Y address signals and supplied to the Y address decoder YD. The Y address decoder YD is selectively activated by the internal control signal YDG being at a high level, decodes the internal address signals Y0 to Yi, and outputs the corresponding bits of the bit line selection signals YS0 to YSn. Is alternatively set to the high level.

The sense amplifier SA is a memory array MAR.
It includes n + 1 unit circuits provided corresponding to Y complementary bit lines B0 * to Bn *. These unit circuits are not particularly limited, but as illustrated in FIG. 2, a pair of N-channel MOSFETs N5 and N5 provided between the non-inverted and inverted signal lines of the complementary bit lines B0 * to Bn *, respectively.
6, a bit line precharge circuit, a CMOS inverter composed of P-channel MOSFET P1 and N-channel MOSFET N1, and a P-channel MOS
It includes a unit amplifier circuit formed by cross-coupling a CMOS inverter composed of an FET P2 and an N-channel MOSFET N2.

Of these, the internal voltage HV is supplied to the commonly connected sources of the MOSFETs N5 and N6 forming the bit line precharge circuit of each unit circuit, and the internal control signal PC is commonly supplied to the gates thereof. To be done. The internal voltage HV is the power supply voltage VCC and the ground potential VS.
It is set to an intermediate potential between S. Further, the internal control signal PC is
When the dynamic RAM is in the non-selected state, it is selectively set to the high level. This allows MOSFET N5
And N6 are selectively turned on when the dynamic RAM is set to the non-selected state and the internal control signal PC is set to the high level, and the corresponding complementary bit lines B0 * to Bn * of the memory array MARY are not inverted and The inversion signal line is precharged to the internal voltage HV.

On the other hand, the sources of the P-channel MOSFETs P1 and P2 constituting the unit amplifier circuit of each unit circuit are
Commonly connected to the common source line SP. The common source line SP is coupled to the power supply voltage VCC through a P-channel drive MOSFET P3 which receives the inverted signal of the internal control signal PA by the inverter V1, that is, the inverted internal control signal PA at its gate. Similarly, the sources of the N-channel MOSFETs N1 and N2 forming each unit amplifier circuit are commonly coupled to the common source line SN. The common source line SN is coupled to the ground potential VSS through an N-channel drive MOSFET N7 which receives the internal control signal PA at its gate. As a result, each unit amplifier circuit is selectively and simultaneously activated by setting the internal control signal PA to the high level and the inverted internal control signal PA to the low level, and the selected word line of the memory array MARY is activated. The minute read signal output from the n + 1 memory cells coupled to the above through the corresponding complementary bit lines B0 * to Bn * is amplified to be a high level or low level binary read signal.

Each unit circuit of the sense amplifier SA further includes a pair of N-channel type switch MOSFETs N3 and N4 provided between the non-inverting and inverting input / output nodes of the unit amplifier circuit and the complementary common data line CD *, respectively. Including. The gates of these switch MOSFET pairs are commonly connected, and corresponding bit line selection signals YS0 to YSn are supplied from the Y address decoder YD. As a result, the switch MOSFETs N3 and N of each unit circuit are
4 is selectively turned on by setting the corresponding bit line selection signals YS0 to YSn to the high level, and the corresponding unit amplifier circuit of the sense amplifier SA, that is, the corresponding set of complementary bits of the memory array MARY. The line and the complementary common data line CD * are selectively connected.

Complementary bit line B0 of memory array MARY
Complementary common data line CD * to which one designated set of * to Bn * is selectively connected is coupled to data input / output circuit IO. The data input / output circuit IO includes a write amplifier, a main amplifier, a data input buffer, and a data output buffer, which are not shown. Of these, the output terminal of the write amplifier and the input terminal of the main amplifier are commonly coupled to the complementary common data line CD *. The input terminal of the write amplifier is coupled to the output terminal of the data input buffer, and the input terminal of the data input buffer is coupled to the data input terminal Din. The output terminal of the main amplifier is coupled to the input terminal of the data output buffer, and the output terminal of the data output buffer is coupled to the data output terminal Dout.

The data input buffer of the data input / output circuit IO fetches the write data supplied via the data input terminal Din and transmits it to the write amplifier when the dynamic RAM is selected in the write mode. This write data is converted into a predetermined complementary write signal by the write amplifier, and then the complementary common data line CD
The data is written to one selected memory cell of the memory array MARY via *. On the other hand, the data input / output circuit IO
Of the main amplifier further amplifies the binary read signal output from the selected memory cell of the memory array MARY through the complementary common data line CD * when the dynamic RAM is selected in the read mode. , To the data output buffer. This read data is
The data is output from the data output buffer via the data output terminal Dout.

The timing generation circuit TG selectively forms the above various internal control signals based on the row address strobe signal RASB, the column address strobe signal CASB, and the write enable signal WEB which are externally supplied as start control signals. And supplies it to each part of the dynamic RAM.

FIG. 3 shows a signal waveform diagram of the first embodiment of the read mode of the dynamic RAM of FIG. Further, FIG. 4 shows cycle A of the read mode of FIG.
5 is a connection diagram of the memory array in FIG. 5, and FIG. 5 is a connection diagram of the memory array in the cycle B thereof. Based on these drawings, a specific method of defect relief in the read mode of the dynamic RAM of this embodiment and its features will be described. 3 to 5, the memory cell C0 connected to the intersection of the word line W0 and the complementary bit line B0 *, that is, the inverted bit line B0B.
Is regarded as an unusable damaged cell and is replaced with a normal redundant memory cell R0 coupled to the intersection of the redundant word line WR0 and the complementary bit line B0 *, that is, the inverted bit line B0B. Further, the memory cell C coupled to the intersection of the word line W1 and the complementary bit line B0 *, that is, the non-inverted bit line B0T.
1 is a leak cell having a leak failure, and the redundant word line WR1 and the complementary bit line B0 *, that is, the non-inverted bit line B
Although assigned to the redundant memory cell R1 coupled to the intersection with 0T, this redundant memory cell R1 is also a leak cell having a similar leak fault. Hereinafter, a specific description of the defect relief will be made by taking these cells as an example. It goes without saying that the defect relief in the row address direction is performed in units of n + 1 memory cells coupled to the word line.

In FIG. 3, the dynamic RAM is
The row address strobe signal RASB is brought to the low level to bring it into the selected state, and the write enable signal WEB (not shown) is brought to the high level at the falling edge of the row address strobe signal RASB to enter the read mode. In the cycle A, the X address signal A is applied to the address input terminals A0 to Ai in synchronization with the fall of the row address strobe signal RASB.
X0 to AXi are supplied in a combination designating the word line W0, and Y address signals AY0 to AYi are supplied in synchronization with the fall of the column address strobe signal CASB. Among these, the X address signals AX0 to AXi are
In response to an internal control signal XL (not shown) formed in response to the fall of row address strobe signal RASB, it is taken into X address buffer XB and transmitted to redundant address decoder RD and X address decoder XD as internal address signals X0 to Xi. The Y address signals AY0 to AYi are the column address strobe signals C
It is taken into the Y address buffer YB according to an internal control signal YL (not shown) formed in response to the fall of ASB, and transmitted to the Y address decoder YD as internal address signals Y0 to Yi. The internal address signal PA is
When a predetermined time elapses after the row address strobe signal RASB is set to the low level, the row address strobe signal RASB is set to the high level for a predetermined period.

In this embodiment, the damaged cell C0 is coupled to the word line W0 designated in the cycle A as described above, and the word line W0 is replaced with the redundant word line WR0. Therefore, in the redundant address decoder RD, the redundant word line drive signal XR0 is set to the high level at the time when the internal address signals X0 to Xi are input, and since the failure of the word line W0 is not the leak failure, the redundancy switching signal XR is generated. Is a high level. As a result, the internal address signal X by the X address decoder XD
The decoding operation of 0 to Xi is stopped. In addition, as shown in FIG. 4, the redundant word line WR0 of the memory array MARY receives the high level of the redundant word line drive signal XR0.
Are set to a high level selected state, and the redundant word line WR
Complementary bit line B0 * to which a minute read signal according to the data held in n + 1 memory cells coupled to 0 corresponds
It is output to Bn *. These minute read signals are amplified by the corresponding unit amplifier circuits of the sense amplifier SA when the internal control signal PA is set to the high level, the power supply voltage VCC is set to the high level, and the ground potential VSS is set.
Is a low level binary read signal.

As described above, the redundant memory cell R0 coupled to the intersection of the redundant word line WR0 and the complementary bit line B0 *, that is, the inverted bit line B0B is regarded as a normal cell, and the redundant bit line B0 is connected to the redundant memory cell R0. The minute read signal output to * is set to a prescribed level. Therefore, this minute read signal is normally amplified by receiving the high level of the internal control signal PA, and becomes a binary read signal of a specified level.

Next, in the case of cycle B, the row address strobe signal RAS is applied to the address input terminals A0 to Ai.
X address signals AX0 to AX in synchronization with the falling edge of B
i is supplied in a combination designating the word line W1, and Y address signals AY0 to AYi are supplied in synchronization with the fall of the column address strobe signal CASB. X
The address signals AX0 to AXi are likewise internal control signals X.
According to L, it is taken into the X address buffer XB, and the X address decoder XD as the internal address signals X0 to Xi.
And the redundant address decoder RD. Also, Y
Address signals AY0 to AYi are taken into Y address buffer YB in accordance with internal control signal YL and transmitted to Y address decoder YD as internal address signals Y0 to Yi. Then, the row address strobe signal RASB
The internal address signal PA is set to the high level when a predetermined time elapses after the signal is set to the low level.

In this embodiment, the word line W1 designated by the cycle B has the leak cell C1 as described above.
, And the word line W1 is assigned to the redundant word line WR1, and a similar leak cell R1 is also connected to this redundant word line WR1. Therefore, in the redundant address decoder RD, the redundant word line drive signal XR1 is set to the high level at the time when the internal address signals X0 to Xi are input, but since the failure of the word line W1 is a leak failure, the redundancy switching signal is generated. XR remains low level. Therefore, the X address decoder XD is set in the operating state, and as shown in FIG.
At the same time that the word line W1 designated by Xi is selected, the redundant word line WR1 is also selected. As a result, the complementary bit lines B0 * to Bn * are connected to the word line W
1 and the minute read signals according to the data held in the two memory cells coupled to the redundant word line WR1 are output and amplified by the corresponding unit amplifier circuit of the sense amplifier SA.

As is well known, when a high level write is performed on a memory cell, the information storage capacitor Cs of the memory cell is written.
Is initially supplied with a write potential corresponding to the power supply voltage VCC. On the other hand, when the read mode is executed and this memory cell is selected, for example, for the corresponding complementary bit line B0 *, the total load capacitance of the bit line is set to Cb, and the electrostatic capacitance of the information storage capacitor Cs of the memory cell is set. Is Cs, a minute read signal having a signal amount Vb of Vb = VCC × Cs / (Cb + Cs) is obtained.

In the case of this embodiment, both the memory cell C1 connected to the word line W1 and the redundant memory cell R1 connected to the redundant word line WR1 have a leak fault. However, when the word line W1 and the redundant word line WR1 are simultaneously selected, two memory cells are connected to each of the complementary bit lines B0 * to Bn *, and the capacitance of the information storage capacitor Cs is The capacitance is equivalently doubled, that is, 2Cs, and the signal amount Vb of the minute read signal on the complementary bit line B0 * or the like is Vb = VCC × 2Cs / (Cb + 2Cs). As a result, although the redundant word line WR1 has a leak failure, a sufficient signal amount can be obtained for the complementary bit line B0 * and the like, so that the defect relief of the leak cell coupled to the word line W1 can be realized. As a result, the product yield of the dynamic RAM can be improved.

FIG. 6 is a signal waveform diagram of the second embodiment of the read mode of the dynamic RAM of FIG. Further, FIG. 7 shows cycle C of the read mode of FIG.
8 is a connection diagram of the memory array in FIG. 8, and FIG. 8 is a connection diagram of the memory array in the cycle D thereof. Based on these figures, another embodiment of defect relief in the read mode of the dynamic RAM of this embodiment and its characteristics will be described. It should be noted that this embodiment basically follows the embodiment of FIGS. 3 to 5, and therefore only the portions different from this will be described. 6 to 8, the memory cell C0 coupled to the intersection of the word line W0 and the complementary bit line B0 *, that is, the inverted bit line B0B is regarded as an unusable damaged cell, and the redundant word line WR1 and the complementary bit line B0. * That is, it is replaced with a normal redundant memory cell R1 coupled to the intersection with the non-inverted bit line B0T. Further, the memory cell C1 coupled to the intersection of the word line W1 and the complementary bit line B0 *, that is, the non-inverted bit line B0T is a leak cell having a leak failure, and the redundant word line WR0 and the complementary bit line B0.
0 *, that is, it is assigned to the redundant memory cell R0 coupled to the intersection with the inverted bit line B0B, and this redundant memory cell R0 is also a leak cell having a similar leak failure. That is, in this embodiment, the drain of the address selection MOSFET of the memory cell having the leak fault and the drain of the address selection MOSFET of the redundant memory cell are complementary to the non-inversion and inversion signal lines of the corresponding complementary bit line B0 *. Redundant word lines are assigned to be coupled.

In cycle C of FIG. 6, the row address strobe signal RA is applied to the address input terminals A0 to Ai.
X address signals AX0 to AX0 are synchronized with the falling edge of SB.
AXi is supplied in a combination designating the word line W0. These X address signals are taken in by the X address buffer XB in accordance with the internal control signal XL, and transmitted as the internal address signals X0 to Xi to the redundant address decoder RD and the X address decoder XD. In the redundant address decoder RD, the redundant word line drive signal XR1 is set to the high level and the redundancy switching signal XR is set to the high level when the internal address signals X0 to Xi are input. Therefore, the decoding operation of the X address decoder XD is stopped, and in the memory array MARY, as shown in FIG. 7, only the corresponding redundant word line WR1 is selected. As described above, since the redundant memory cell R1 coupled to the redundant word line WR1 is a normal cell, a minute read signal having a specified signal amount can be obtained on the complementary bit line B0 *.

Next, in the case of cycle D, the row address strobe signal RAS is applied to the address input terminals A0 to Ai.
X address signals AX0 to AX in synchronization with the falling edge of B
i is supplied in a combination designating the word line W1.
These X address signals are taken in by the X address buffer XB in accordance with the internal control signal XL, and transmitted as the internal address signals X0 to Xi to the redundant address decoder RD and the X address decoder XD. In the redundant address decoder RD, the redundant word line drive signal XR0 is set to the high level when the internal address signals X0 to Xi are input, but since the failure of the word line W1 is the leakage failure, the redundancy switching signal XR is set to the low level. Will be left as it is. Therefore, the X address decoder XD is activated,
As shown in FIG. 8, the word line W1 designated by the internal address signals X0 to Xi is selected, and at the same time, the redundant word line WR0 is also selected. As a result, minute read signals according to the data held in the two memory cells coupled to the word line W1 and the redundant word line WR0 are output to the complementary bit lines B0 * to Bn *, respectively, and the sense amplifier SA responds. Is amplified by the unit amplifier circuit.

By the way, as is well known, a leak failure in a memory cell becomes a problem when a high level write is performed, and in a memory cell in which a low level write is performed, the write level is a ground potential VS.
Almost no leak occurs because of S. However,
In this embodiment, as described above, the drain of the address selection MOSFET of the memory cell having the leakage fault and the drain of the address selection MOSFET of the redundant memory cell are connected to the corresponding non-inversion and inversion signal lines of the complementary bit line B0 *. When the redundant word line is allocated to be complementarily coupled and the leak cell C0 coupled to the word line W1 is coupled to the non-inverted bit line B0T, the redundant word line W is formed.
Redundant memory cell R0 coupled to R0 has an inverted bit line B
It is tied to 0B. Therefore, when a high level write is performed in one of these memory cells, a low level write is performed in the other memory cell, and as for the minute read signal, as shown in FIG. It has a normal signal amount. As a result, although the redundant word line WR0 has a leak failure,
The leak cell coupled to the word line W1 can be more reliably relieved, which can further increase the product yield of the dynamic RAM.

By applying the present invention to a semiconductor memory device such as a dynamic RAM having a redundant word line as shown in the above embodiment, the following operational effects can be obtained. That is, (1) In a dynamic RAM or the like having redundant word lines, when a word line in which a failure is detected is designated, a redundant address decoder which selectively brings the corresponding redundant word line into a selected state is used. Storage means is provided for indicating that the fault of the assigned word line is a leak fault, and if the fault of the word line assigned to the redundant word line is a leak fault, the word in which the leak fault is detected By providing the function of simultaneously selecting a line and the corresponding redundant word line in the selected state, even if the redundant word line assigned to the word line having the leak fault has the same leak fault, the substantial memory cell The effect that the information storage capacity can be doubled and relieved can be obtained. (2) According to the above item (1), it is possible to increase the product yield of a dynamic RAM or the like having a redundant word line without increasing the redundant word line, that is, without hindering the cost reduction. To be

(3) In the above items (1) and (2),
The drain of the address selection MOSFET of the memory cell coupled to the word line in which the failure is detected and the drain of the address selection MOSFET of the memory cell coupled to the redundant word line are connected to the non-inversion and inversion signal lines of corresponding complementary bit lines. By allocating the redundant word lines so that they are complementarily coupled to each other, it is possible to obtain the effect that the prescribed signal amount can be ensured in either of the two memory cells that are simultaneously selected. (4) According to the above item (3), even if a redundant word line assigned to a word line having a leak failure has a leak failure, it can be more reliably relieved and the dynamic RAM
It is possible to obtain the effect of increasing the product yield such as.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the dynamic RAM can have a so-called multi-bit configuration in which a plurality of bits of storage data are simultaneously input or output. Also, dynamic type R
The AM does not require the address multiplex method as an essential condition, and various embodiments can be adopted in the block configuration, the combination of the activation control signal and the address signal, and the like.

In FIG. 2, the memory array MARY is
An arbitrary number of redundant word lines can be provided, and redundant bit lines for relieving a complementary bit line in which a failure is detected can be provided. In addition, the memory array MARY
Can be divided into a plurality of sub memory arrays, and can be a drive MOSF for driving the unit amplifier circuit of the sense amplifier SA.
The ET can also be replaced with a plurality of drive MOSFETs that are in a parallel form and are sequentially turned on after a predetermined time. Furthermore, various embodiments can be adopted for the specific circuit configuration of the memory array MARY and the sense amplifier SA, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET, and the like.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic type RAM which is the field of application as the background has been described.
The present invention is not limited to this, and for example, a pseudo-static type R having a similar dynamic RAM as a basic configuration is used.
The present invention can also be applied to various memory integrated circuit devices including AM and redundant word lines, and logic integrated circuit devices including such memory integrated circuit devices. The present invention can be widely applied to a semiconductor memory device having at least a redundant word line and a semiconductor device incorporating such a semiconductor memory device.

[0045]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like having redundant word lines, when a defective word line is designated, a redundant address decoder that selectively selects the corresponding redundant word line is assigned to the redundant word line. Storage means is provided to indicate that the fault is a leak fault, and if the fault of the word line assigned to the redundant word line is the leak fault, the redundancy corresponding to the word line in which the leak fault is detected. The word line and the word line are simultaneously selected. Further, non-inversion and inversion signals of complementary bit lines corresponding to the drain of the address selection MOSFET of the memory cell coupled to the word line in which the failure is detected and the drain of the address selection MOSFET of the memory cell coupled to the redundant word line. The redundant word lines are assigned to be complementary coupled to the lines. As a result, even if the redundant word line assigned to the word line having a leak failure has a similar leak failure, the substantial information storage capacity of the memory cell can be doubled, and this can be remedied. . As a result, the product yield of a dynamic RAM or the like having redundant word lines can be increased without increasing the number of redundant word lines, that is, without hindering the cost reduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a circuit diagram showing an embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG.

FIG. 3 is a signal waveform diagram showing a first embodiment of a read mode of the dynamic RAM of FIG.

FIG. 4 is a connection diagram of a memory array in cycle A of the read mode of FIG.

5 is a connection diagram of a memory array in cycle B of the read mode of FIG.

FIG. 6 is a signal waveform diagram showing a second embodiment of the read mode of the dynamic RAM of FIG.

FIG. 7 is a connection diagram of the memory array in cycle C of the read mode of FIG.

FIG. 8 is a connection diagram of a memory array in cycle D of the read mode of FIG.

[Explanation of symbols]

MARY ... Memory array, XD ... X address decoder, RD ... Redundant address decoder, XB ...
X address buffer, SA ... Sense amplifier, YD
... Y address decoder, YB ... Y address buffer, IO ... data input / output circuit, TG ... timing generation circuit. W0 to Wm ... Word line, WR0 to W
R1 ... Redundant word line, B0 * to Bn * ... Complementary bit line, Cs ... Information storage capacitor, Qa ... Address selection MOSFET, SP, SN ... Common source line, YS0-YSn. ..Bit line selection signals, CD *
... Complementary common data line. P1 to P3 ... P channel MOSFET, N1 to N7 ... N channel MOS
FET, V1 ... Inverter. C0-C1, R0-R
1 ... Memory cell, USA ... Unit amplification circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/04 21/822 H01L 27/04 D

Claims (4)

[Claims] 1. A word line in which a fault is detected and a word line in which a fault is detected under a predetermined condition, comprising a plurality of word lines and a redundant word line selectively assigned corresponding to the word line in which the fault is detected. A semiconductor memory device characterized in that an assigned redundant word line is simultaneously selected. 2. The semiconductor device according to claim 1, wherein the redundant word line is selectively brought into the selected state simultaneously with the corresponding word line when the failure of the corresponding word line is a leak failure. Storage device. 3. The semiconductor memory device comprises a redundant address decoder which selectively sets a corresponding redundant word line into a selected state when a word line in which a fault is detected is designated, and the redundant address is provided. 3. The semiconductor memory device according to claim 2, wherein the decoder includes a storage means for indicating that the fault of the word line assigned to the corresponding redundant word line is a leak fault. 4. The semiconductor memory device is a dynamic RAM adopting a folded bit line system, wherein the redundant word line is coupled to a word line corresponding to a drain of an address selection MOSFET of a memory cell coupled thereto. 4. The drain of the address selection MOSFET of the memory cell is assigned to be complementary coupled to the non-inverted and inverted signal lines of the corresponding complementary bit line. Semiconductor memory device.