JP3942269B2 - Dynamic RAM - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, for example, a dynamic RAM (Random Access Memory) using a hierarchical IO system, and a technique particularly effective for use in improving defect repair efficiency and product yield.
[0002]
[Prior art]
Semiconductor memory device such as dynamic RAM having a memory array including word lines and complementary bit lines arranged orthogonally and dynamic memory cells arranged at the intersections of these word lines and complementary bit lines as basic components There is. As the dynamic RAM and the like increase in density and capacity, the memory array and its direct peripheral part are divided into a row direction, that is, a word line extending direction and a column direction, that is, a bit line extending direction, respectively. As a method for increasing the operation speed and reducing the power consumption, a lattice arrangement is known. Further, a sub IO line is provided for each of the memory mats arranged in a grid, and a main IO line is arranged in a direction orthogonal to these sub IO lines to select between the designated sub IO line and the main IO line. A so-called hierarchical IO system is generally becoming a connection state.
[0003]
On the other hand, a predetermined number of redundant word lines and redundant bit lines are provided in a memory array such as a dynamic RAM, and these redundant word lines and redundant bit lines are selectively replaced with word lines or bit lines in which a failure is detected. There is known a so-called defect relief method for increasing the product yield of a dynamic RAM or the like.
[0004]
[Problems to be solved by the invention]
Prior to the present invention, the inventors of the present application engaged in the development of a dynamic RAM adopting a hierarchical IO method, and noticed the following problems. That is, in this dynamic RAM, as illustrated in FIG. 14, the sub IO lines SI00 *, SI01 *, SI10 *, SI11 * and the like (here, for example, the non-inverted sub IO line SI00T and the inverted sub IO line SI00B are connected). In addition, a sub IO line SI00 * is attached with *, and a so-called non-inverted signal or the like that is selectively set to a high level when it is enabled is appended with T at the end of its name. The inverted signal that is selectively set to the low level when it is valid is indicated by adding B to the end of the name. The same applies to the memory array MARY00 or MARY01. The wiring length of the memory arrays MARY00 and MARY01 is substantially the same as the length in the row direction, that is, the word line length. The memory arrays MARY00 and MARY01 are provided with, for example, two sets, that is, four redundant bit lines RB0 * to RB3 *, respectively, for defect relief.
[0005]
Redundant bit lines RB0 * to RB3 * provided in the memory arrays MARY00 and MARY01, etc., have corresponding redundant bit line selection signals RYS0 or RYS1 set to high level, and corresponding switch MOSFETs of sense amplifiers SA00, SA01, SA10 or SA11 ( Metal oxide semiconductor field effect transistors (in this specification, MOSFETs are collectively referred to as insulated gate field effect transistors) are turned on so that two sets of sub IO lines SI00 *, Connected to SI01 *, SI10 *, SI11 * or the like.
[0006]
However, in the dynamic RAM, as described above, the wiring lengths of the sub IO lines SI00 *, SI01 *, SI10 *, SI11 *, etc. are almost the same as the row lengths of the memory arrays MARY00, MARY01, etc. The bit lines RB0 * to RB3 * can be used only for repairing defective bit lines detected in the corresponding memory array MARY00 or MARY01. Therefore, as illustrated in FIG. 14, for example, when three defective bit lines Bq + 1 *, Br + 1 *, and Bs * are detected in the memory array MARY01, redundant bit lines that are not used in the adjacent memory array MARY00 Although RB2 * and RB3 * remain, they cannot be remedied, thereby causing a problem that the product yield of the dynamic RAM is not improved as expected.
[0007]
An object of the present invention is to improve the defect repair efficiency of a dynamic RAM or the like that adopts a hierarchical IO system, and to increase the product yield.
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like that uses a hierarchical IO system, the sub IO line has a wiring length that is twice the length in the row direction of the memory array, for example, and is shared by, for example, two memory mats adjacent in the row direction. Each of these memory mats is provided with, for example, two sets of redundant bit lines, and is shared by, for example, two memory mats sharing the sub IO line. In addition, the sub IO line is, for example, half the length of the memory array in the row direction, and the redundant bit lines are integrated into one of, for example, q memory mats arranged adjacent to each other in the row direction. And shared by q memory mats arranged adjacent to each other.
[0010]
According to the first means, a total of four sets of redundant bit lines provided in two adjacent memory mats can be used for repairing defective bit lines detected in the two memory mats. It is possible to increase the defect repair efficiency of the type RAM or the like and increase the product yield. Further, according to the second means, the sub-IO line is shortened and the load capacity is reduced, and is provided in one of q pieces arranged adjacent to each other in the row direction. Since the redundant bit line can be used to relieve the defective bit line detected by q memory mats, the defect relieving efficiency of the dynamic RAM and the like can be further increased, and the product yield can be increased.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a dynamic RAM (semiconductor memory device) to which the present invention is applied. The outline of the configuration and operation of the dynamic RAM of this embodiment will be described first with reference to FIG. 1 are formed on one semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.
[0012]
In FIG. 1, the dynamic RAM of this embodiment includes four banks BNK0 to BNK3, and each of these banks occupies most of the layout area as represented by the bank BNK0 in FIG. The memory array MARY, an X address decoder XD, a sense amplifier SA and a Y address decoder YD, which are directly peripheral circuits, and a main amplifier MA.
[0013]
In the dynamic RAM of this embodiment, the memory array MARY constituting the banks BNK0 to BNK3 and its direct peripheral portion are actually divided into 16 in the row direction and the column direction, respectively, and a total of 256 memory mats are used as a lattice. Arranged. The dynamic RAM adopts a shared sense system, and the memory arrays MARY configuring each memory mat of the banks BNK0 to BNK3 are paired with the corresponding sense amplifier SA interposed therebetween. Specific configurations of the banks BNK0 to BNK3 and the memory mat will be described in detail later.
[0014]
The memory arrays MARY of the banks BNK0 to BNK3 include a predetermined number of word lines arranged in parallel in the vertical direction in the figure and a predetermined number of complementary bit lines and redundant bit lines arranged in parallel in the horizontal direction. Includes each. At the intersections of these word lines and bit lines, a large number of dynamic memory cells each consisting of an information storage capacitor and an address selection MOSFET are arranged in a grid pattern.
[0015]
The words constituting the memory array MARY of the banks BNK0 to BNK3 are coupled to the corresponding X address decoder XD in the lower part of the figure, and are selectively set in the selected state. The X address decoders XD of the banks BNK0 to BNK3 are commonly supplied with a predecode signal of a predetermined bit from the X predecoder XP and are also commonly supplied with the internal control signal XG from the timing generation circuit TG. The X predecoder XP is supplied with an internal X address signal of a predetermined bit from the X address buffer XB. Further, X address signals AX0 to AXi are supplied to the X address buffer XB from an external access device via address input terminals A0 to Ai in a time-sharing manner, and an internal control signal XL is supplied from the timing generation circuit TG. Is done. A part of the internal X address signal formed by the X address buffer XB is also supplied to the mat selection circuit MS.
[0016]
The X address buffer XB fetches and holds the X address signals AX0 to AXi supplied via the address input terminals A0 to Ai in accordance with the internal control signal XL, and performs non-inversion and inversion based on these X address signals, respectively. An internal X address signal composed of the signal is formed and supplied to the X predecoder XP and the mat selection circuit MS. Also, the X predecoder XP decodes the internal X address signal supplied from the X address buffer XB in combination with predetermined bits, and selectively sets the corresponding bit of each predecode signal to the high level. Further, the X address decoders XD of the banks BNK0 to BNK3 are selectively activated in response to the high level of the internal control signal XG, and the predecode signals supplied from the X predecoder XP are combined under a predetermined condition. The designated word line of the corresponding memory array MARY is alternatively set to a high level selected state. In this embodiment, a so-called hierarchical word line system is employed in which the word lines of the memory array MARY are hierarchized into a main word line and a sub word line. This will be described later together with a specific configuration of the memory array MARY. This will be described in detail.
[0017]
The mat selection circuit MS decodes a predetermined bit of the internal X address signal supplied from the X address buffer XB, and alternatively sets the corresponding bits of the mat row selection signals MRS0 to MRSF to the high level. The mat selection circuit MS generates a mat column selection signal for column selection (not shown) in addition to the mat row selection signals MRS0 to MRSF, but is omitted because it is not directly related to the present invention.
[0018]
Next, the complementary bit lines constituting the memory array MARY of the banks BNK0 to BNK3 are coupled to the corresponding sense amplifiers SA on the left side of the figure, and substantially eight sets of main IO lines MI0 * to 8K are connected via the sense amplifiers SA. Selectively connected to MI7 *. The sense amplifiers SA in the banks BNK0 to BNK3 are supplied with a bit line selection signal and a redundant bit line selection signal of a predetermined bit from the corresponding Y address decoder YD, and are also supplied with a sense amplifier drive signal PA and precharge from the timing generation circuit TG. A control signal PC and shared control signals SHL and SHR are supplied in common. The Y address decoder YD of each bank is commonly supplied with a predecode signal of a predetermined bit from the Y predecoder YP, and is commonly supplied with the internal control signal YG from the timing generation circuit TG.
[0019]
The Y predecoder YP is supplied with an internal Y address signal of a predetermined bit from the Y address buffer YB. The Y address buffer YB is supplied with the Y address signals AY0 to AYi from an external access device via the address input terminals A0 to Ai in a time division manner, and the internal control signal YL is supplied from the timing generation circuit TG. . The predecode signal formed by the Y predecoder YP is also supplied to the Y-system redundant circuit YR. The Y-system redundancy circuit YR is further supplied with mat row selection signals MRS0 to MRSF from the mat selection circuit MS and an internal control signal RFEB from the timing generation circuit TG.
[0020]
The Y address buffer YB fetches and holds the Y address signals AY0 to AYi supplied via the address input terminals A0 to Ai in accordance with the internal control signal YL, and non-inverted and inverted signals based on these Y address signals. An internal Y address signal is formed and supplied to the Y predecoder YP. The Y predecoder YP decodes the internal Y address signal supplied from the Y address buffer YB in combination with a predetermined number of bits, and alternatively sets the corresponding bit of each predecode signal to the high level. Further, the Y-system redundant circuit YR holds the address of the defective bit line assigned to each redundant bit line of the memory array MARY, that is, the relief address, and also supplies the relief address and the address supplied from the outside at the time of access, that is, the predecode. The signal is compared and collated, and the corresponding bit of the redundant bit line drive signal that is the output signal is alternatively set to an effective level. The specific configuration of the Y-system redundant circuit YR will be described later in detail.
[0021]
The Y address decoders YD of the banks BNK0 to BNK3 are selectively activated in response to the high level of the internal control signal YG, and are supplied from the predecode signal supplied from the Y predecoder YP and the Y redundant circuit YR. In combination with the redundant bit line drive signal, the bit line selection signal as the output signal or the corresponding bit of the redundant bit line selection signal is alternatively set to the high level.
[0022]
The sense amplifiers SA of the banks BNK0 to BNK3 include a predetermined number of unit circuits provided corresponding to each complementary bit line and redundant bit line of the memory array MARY, and each of these unit circuits is a pair of CMOS (complementary type). A unit sense amplifier in which MOS) inverters are cross-coupled, a bit line precharge circuit in which three N-channel type precharge MOSFETs are combined, and a pair of N-channel type switch MOSFETs. Among these, the unit sense amplifiers of each unit circuit are selectively and simultaneously activated in response to the high level of the sense amplifier drive signal PA, and a predetermined number of memory cells coupled to the selected word line of the memory array MARY. A minute read signal output from each through the complementary bit lines is amplified to obtain a high-level or low-level binary read signal.
[0023]
On the other hand, the three precharge MOSFETs constituting the bit line precharge circuit of each unit circuit are selectively turned on at the same time in response to the high level of the precharge control signal PC, and corresponding complementary of the memory array MARY. The non-inverted and inverted signal lines of the bit line or redundant bit line are precharged to an intermediate potential between the power supply voltage and the ground potential. In addition, the switch MOSFET pairs of each unit circuit are selectively turned on by eight pairs when the corresponding bit of the bit line selection signal is set to the high level, and the corresponding eight complementary bit lines of the memory array MARY. Alternatively, the redundant bit line and the main IO lines MI0 * to MI7 * are selectively connected. The dynamic RAM of this embodiment adopts a shared sense system, and each unit circuit of the sense amplifier SA further includes a shared MOSFET that is selectively turned on in response to the high level of the shared control signal SHL or SHR. Including.
[0024]
Main IO lines MI0 * to MI7 * are coupled to corresponding unit circuits of main amplifier MA, and these unit circuits are coupled to corresponding unit circuits of data input / output circuit IO via data input / output buses IOB0 to IOB7. Is done. The main amplifiers MA in the banks BNK0 to BNK3 include eight unit circuits provided corresponding to the main IO lines MI0 * to MI7 *, and each of these unit circuits includes a write amplifier and a read amplifier. The data input / output circuit IO includes eight unit circuits provided corresponding to the data input / output buses IOB0 to IOB7, and each of these unit circuits includes a data input buffer and a data output buffer.
[0025]
The input terminal of the write amplifier of each unit circuit of the main amplifier MA is coupled to the output terminal of the data input buffer of the corresponding unit circuit of the data input / output circuit IO via the data input / output buses IOB0 to IOB7. Are coupled to corresponding main IO lines MI0 * to MI7 *. The input terminals of the read amplifiers of each unit circuit are coupled to the corresponding main IO lines MI0 * to MI7 *, and their output terminals correspond to the data input / output circuits IO via the data input / output buses IOB0 to IOB7. Coupled to the input terminal of the data output buffer of the unit circuit. The input terminal of the data input buffer and the output terminal of the data output buffer of each unit circuit of the data input / output circuit IO are commonly coupled to the data input / output terminals D0 to D7, respectively. The internal control signal WP is commonly supplied from the timing generation circuit TG to the write amplifier of each unit circuit of the main amplifier MA, and the internal control signal OC (not shown) is supplied to the data output buffer of each unit circuit of the data input / output circuit IO. Are supplied in common. The main IO lines MI0 * to MI7 * are virtually represented in accordance with the number of unit circuits of the main amplifier MA, and are substantially the main IO lines provided in the memory mat after division, which will be described later. Does not necessarily correspond.
[0026]
When the dynamic RAM is selected in the write mode, the data input buffer of each unit circuit of the data input / output circuit IO captures a total of 8 bits of write data supplied via the data input terminals D0 to D7, The data is transmitted to the write amplifiers of the corresponding unit circuits of the main amplifiers MA in the banks BNK0 to BNK3 via the data input / output buses IOB0 to IOB7. At this time, the write amplifier of each unit circuit of the main amplifier MA is selectively activated in response to the high level of the internal control signal WP, and the write data transmitted from the corresponding data input buffer is changed to a predetermined complementary write signal. After that, the selected eight memory cells of the memory array MARY are written via the main IO lines MI0 * to MI7 *.
[0027]
On the other hand, when the dynamic RAM is selected in the read mode, the read amplifier of each unit circuit of the main amplifier MA is connected to the main IO lines MI0 * to MI7 * from the eight memory cells in the selected state of the memory array MARY. Is further amplified and then transmitted to the data output buffer of the corresponding unit circuit of the data input / output circuit IO via the data input / output buses IOB0 to IOB7. At this time, the data output buffer of each unit circuit of the data input / output circuit IO is selectively activated in response to the high level of the internal control signal OC, and is transmitted from the read amplifier of the corresponding unit circuit of the main amplifier MA. Read data is output to an external access device via data input / output terminals D0 to D7.
[0028]
The timing generation circuit TG selectively selects the various internal control signals based on the row address strobe signal RASB, the column address strobe signal CASB, and the write enable signal WEB supplied as activation control signals from an external access device. It is formed and supplied to each part of the dynamic RAM.
[0029]
FIG. 2 shows a substrate layout of one embodiment of the dynamic RAM of FIG. FIG. 3 is a partial enlarged layout diagram of an embodiment relating to the bank BNK0 of the dynamic RAM of FIG. Based on these drawings, an outline of the substrate layout of the dynamic RAM of this embodiment and its selection form will be described. FIG. 2 illustrates a memory mat row that is simultaneously activated by applying diagonal lines within the frame line, and a memory mat that is simultaneously activated by painting the frame line black. Further, in the following description regarding the substrate arrangement, the top, bottom, left, and right on the semiconductor substrate surface are expressed with the positional relationship of FIGS. 2 and 3.
[0030]
In FIG. 2, the dynamic RAM of this embodiment includes four banks BNK0 to BNK3 as described above. Among these, the bank BNK0 is disposed in the lower left portion of the semiconductor substrate CHIP, and the bank BNK1 is disposed on the right side thereof, that is, in the lower right portion of the semiconductor substrate CHIP. The bank BNK2 is disposed at the upper left portion of the semiconductor substrate CHIP, and the bank BNK3 is disposed at the upper right portion thereof. A total of 32 unit circuits of the main amplifier MA corresponding to the banks BNK0 to BNK3 are arranged in a portion along the vertical center line of the semiconductor substrate CHIP.
[0031]
Here, each of the banks BNK0 to BNK3 constituting the dynamic RAM is represented by p pieces in the row direction, that is, the word line direction, that is, the vertical direction in the figure, across the X address decoder XD, as represented by the bank BNK0. That is, it includes a total of 256 memory mats MAT00 and the like that are arranged in a grid of 16 each, and in the column direction, that is, the bit line direction, that is, in the horizontal direction in the figure. These memory mats are given and identified with selection addresses comprising memory mat rows MR0 to MRF and memory mat columns MC0 to MCF.
[0032]
In this embodiment, the banks BNK0 to BNK3 constituting the dynamic RAM are activated with independent access addresses. In each activated bank, as shown in the figure, for example, the memory mat columns MC0, MC0, With the combination of MC4, MC8 and MCC, four memory mat columns are simultaneously activated. In the four memory mat columns to be activated, for example, four memory mats arranged in the designated memory mat row MR0 are simultaneously activated, and in the four memory mats to be activated, A total of eight memory cells, two of each, are simultaneously selected.
[0033]
In this embodiment, the dynamic RAM adopts a hierarchical word line system, and the word lines constituting the memory array of each memory mat are main lines arranged on both sides of the X address decoder XD as illustrated in FIG. The main word line MWL coupled to the word line driving circuit MWD and the sub word line SWL in each memory array are hierarchized. Sense amplifiers SA are arranged on the left and right sides of the memory array constituting each memory mat, and sub word line drive circuits SWD for selectively selecting the sub word lines SWL are arranged above and below them.
[0034]
On the other hand, the dynamic RAM of this embodiment adopts a hierarchical IO system, and a common IO line (common data line) for connecting a designated memory cell, that is, a bit line and a main amplifier MA in the memory array. Are hierarchized into sub IO lines arranged in the vertical direction on the sense amplifier SA and main IO lines arranged in the horizontal direction on the sub word line drive circuit SWD. An intersection area IS is provided at the intersection of the arrangement area of the sense amplifier SA and the arrangement area of the sub word line drive circuit SWD, and a designated sub IO line and main IO line are selectively connected to each intersection area IS. A switch MOSFET and an auxiliary main amplifier AA are provided.
[0035]
Further, in the dynamic RAM of this embodiment, as will be described later, four sets of redundant bit lines are provided in each of the memory mats, and defect relief by these redundant bit lines is performed in 16 pieces arranged in the same column. This is performed independently in each memory mat. However, in this embodiment, as described above, only one memory mat is activated from each of the four memory mat columns activated simultaneously, so that the bit line selection signal YS and the redundant bit line selection signal are activated. RYS is shared by 16 memory mats arranged in the same column. Similarly, Y address decoders YD shared by 16 memory mats arranged in the same column are arranged on the vertical center line side of the semiconductor substrate CHIP.
[0036]
FIG. 4 is a block diagram showing an embodiment of the memory mat MAT00 included in the bank BNK0 of FIG. FIG. 5 shows a partial circuit diagram of an embodiment of the memory array MARY00 and its direct peripheral circuit included in the memory mat MAT00 of FIG. In the following description regarding FIG. 4 and FIG. 5, all the memory mats in the banks BNK0 to BNK3 will be described using the memory mat MAT00 in the bank BNK0. In the following circuit diagrams and the like, MOSFETs with an arrow attached to the channel (back gate) portion are P-channel type, and are distinguished from N-channel MOSFETs without an arrow.
[0037]
In FIG. 4, a memory mat MAT00 includes a memory array MARY00, a pair of sense amplifiers SA00 and SA10 arranged on the left and right sides thereof, and a pair of sub word line drive circuits SWD00 and SWD01 arranged on the upper and lower sides thereof. Intersection regions IS00, IS01, IS10, and IS11 are provided at intersections of the arrangement regions of these sense amplifiers and sub word line drive circuits. The sense amplifier SA10 is shared by the memory mat MAT00 and a memory mat MAT10 (not shown) arranged on the right side thereof, and the sub word line drive circuit SWD01 is connected to the memory mat MAT00 and a memory mat MAT01 (not shown) arranged on the upper side thereof. Shared by. Further, the intersection areas IS10 and IS01 are shared with the memory mats MAT10 and MAT01, respectively, and the intersection area IS11 is shared with the memory mat MAT11 and the memory mats MAT10 and MAT01 (not shown) arranged on the upper right side of the memory mat MAT00.
[0038]
Here, the memory array MARY00 of the memory mat MAT00 includes m + 1 sub-word lines SW0 to SWm arranged in parallel in the vertical direction in the drawing and n + 1 sets of complementary bit lines arranged in parallel in the horizontal direction in the drawing. B0 * to Bn * and four sets of redundant bit lines RB0 * to RB3 * are included. At the intersections of these word lines and bit lines, (m + 1) × (n + 5) dynamic memory cells made up of information storage capacitors and address selection MOSFETs are arranged in a lattice pattern. Electrodes serving as information storage nodes of information storage capacitors of m + 1 memory cells arranged in the same column of the memory array MARY00 are connected to complementary bit lines B0 * to Bn * or redundant bit lines RB0 * via corresponding address selection MOSFETs. Are alternately coupled to the non-inverted or inverted signal lines of RB3 * with a predetermined regularity. The gates of the address selection MOSFETs of n + 1 memory cells arranged in the same row are commonly coupled to the corresponding sub word lines SW0 to SWm.
[0039]
The sub word lines SW0 to SWm constituting the memory array MARY00 are respectively coupled to the corresponding unit circuits of the sub word line driving circuit SWD00 or SWD01 with a predetermined regularity, and complementary bit lines B0 * to Bn * and redundant bit lines RB0 * to RB3 * is coupled to the corresponding unit circuit of the sense amplifier SA00 or SA10 with a predetermined regularity.
[0040]
The sub word line drive circuit SWD00 includes m + 1 unit circuits provided corresponding to the sub word lines SW0 to SWm of the memory array MARY00, and each of these unit circuits is one as illustrated in FIG. Drive gates G1 to G8. One input terminal of the drive gates G1 to G4 and G5 to G8 of the four adjacent unit circuits of the sub word line drive circuits SWD00 and SWD01, in total, is commonly coupled to the corresponding main word line MW0, and the other one. Sub-word line selection drive signals x0 to x3 are sequentially supplied to the input terminals.
[0041]
The main word line MW0 and the like are set to a high voltage VPP that is higher than the power supply voltage VCC by at least the threshold voltage of the address selection MOSFET of the memory cell when the dynamic RAM is not selected, and the dynamic RAM is selected. When in the state, it is alternatively set to a low level such as the ground potential VSS according to predetermined bits of the X address signals AX0 to AXi. The sub word line selection drive signals x0 to x3 are set to a low level such as the ground potential VSS when the dynamic RAM is not selected, and when the dynamic RAM is selected, the corresponding memory mat column is selected. Is set to an active state, and is alternatively set to the high voltage VPP according to other predetermined bits of the X address signals AX0 to AXi.
[0042]
As a result, the drive gates G1 to G8 and the like of the unit circuits of the sub word line drive circuits SWD00 and SWD01 have the corresponding main word line MW0 and the like at a low level such as the ground potential VSS, and the corresponding sub word line selection drive signal x0. On the condition that .about.x3 is set to the high level such as the high voltage VPP, the corresponding sub word lines SW0 to SW7 are alternatively set to the selection level such as the high voltage VPP. At this time, the minute read signals corresponding to the data held in the n + 5 memory cells coupled to the selected sub word line are respectively applied to the complementary bit lines B0 * to Bn * and the redundant bit lines RB0 * to RB3 * of the memory array MARY00. The signal is output and transmitted to the sense amplifier SA via a shared MOSFET (not shown).
[0043]
Next, the sense amplifiers SA00 and SA10 include n + 5 unit circuits provided corresponding to the complementary bit lines B0 * to Bn * and the redundant bit lines RB0 * to RB3 * of the memory array MARY00. Each unit includes a unit sense amplifier UA in which a pair of CMOS inverters are cross-coupled, a switch means, that is, a pair of N-channel type switch MOSFETs N3 and N4 or N5 and N6, and two sets of shared MOSFETs not shown.
[0044]
One of the switch MOSFETs N3 and N4 and N5 and N6 of each unit circuit of the sense amplifiers SA00 and SA10 is non-inverted or inverted of the corresponding complementary bit lines B0 * to Bn * or redundant bit lines RB0 * to RB3 * of the memory array MARY00. The other is coupled to the signal line, and the other is commonly coupled to the non-inverted or inverted signal line of the sub IO line SI00 * or SI10 *. The gates of the switch MOSFETs N3 and N4 and N5 and N6 are commonly coupled, and the corresponding bit line selection signals YS0 to YSk or redundant bit line selection signals RYS0 to RYS1 are supplied from the Y address decoder YD. A shared control signal (not shown) that generates the shared control signals SHL and SHR for each memory mat row is supplied in common to the gate of the shared MOSFET (not shown) of each unit circuit, and a pair (not shown) is supplied to the unit sense amplifier UA. The high-potential side and low-potential side operation power supplies are selectively supplied through the common source line.
[0045]
As a result, the shared MOSFETs of the unit circuits of the sense amplifiers SA00 and SA10 are selectively turned on in response to the high level of the corresponding shared control signal, and the complementary input / output nodes of the corresponding unit sense amplifiers UA The complementary bit lines B0 * to Bn * and the redundant bit lines RB0 * to RB3 * of the memory array MARY00 are selectively connected. Further, the unit sense amplifiers UA of each unit circuit are selectively and simultaneously operated by being supplied with the high-potential side and low-potential side operation power via the common source line, and the selected word line of the memory array MARY00. Amplifying the minute read signals output from the n + 1 memory cells coupled to the complementary bit lines B0 * to Bn * and the redundant bit lines RB0 * to RB3 *, respectively. It is a binary read signal that sets the low-potential side operation power supply to low level. Further, the switch MOSFETs N3 and N4 and N5 and N6 of each unit circuit are selectively turned on in pairs by receiving the high level of the corresponding bit line selection signals YS0 to YSk or the redundant bit line selection signals RYS0 to RYS1, respectively. The complementary input / output nodes of the total two unit sense amplifiers UA corresponding to the sense amplifiers SA00 and SA10 and the sub IO line SI00 * or SI10 * are selectively connected.
[0046]
The sub IO line SI00 * is coupled to the auxiliary main amplifier AA provided in the crossing region IS00 below the sub IO line SI00 *, and via the N channel type switch MOSFETs N1 and N2 receiving the sub IO line selection signal IS0 at the gate. Coupled to main IO line MI0 * arranged orthogonally. Similarly, the sub IO line SI10 * is coupled to the auxiliary main amplifier AA provided in the crossing region IS11 above the sub IO line SI10 *, and via the N channel type switch MOSFETs N7 and N8 receiving the sub IO line selection signal IS01 at its gate. Are coupled to the main IO line MI1 * arranged orthogonally. Needless to say, sub IO lines SI20 *, SI40 * to SIG0 * of even-numbered row numbers of other memory mats arranged in the memory mat column MC0 are coupled to the main IO line MI0 *, and the main IO line MI1 * is coupled to the main IO line MI1 *. Sub IO lines SI30 *, SI50 through SIF0 * of odd row numbers of other memory mats arranged in memory mat column MC0 are coupled.
[0047]
In this embodiment, the sub IO line SI00 * is shared by two memory mats MAT00 and MAT01 adjacent in the row direction, and the sub IO line SI10 * is also two memory mats MAT00 and MAT01 adjacent in the row direction. Are shared by two memory mats MAT10 and MAT11 (not shown). In other words, four redundant bit lines RB0 * to RB3 * provided in each of four sets in the memory arrays MARY00 and MARY01 can be connected to a common sub IO line SI00 * or SI10 * although the included memory arrays are different. Thus, it can be used to repair defective bit lines detected in the memory arrays MARY00 and MARY01 of the two memory mats MAT00 and MAT01 sharing these sub IO lines. As a result, the defect relief efficiency of the dynamic RAM can be increased and the product yield can be increased.
[0048]
FIG. 6 shows a block diagram of an embodiment of a Y-system redundant circuit YR included in the dynamic RAM of FIG. FIG. 7 shows a block diagram of an embodiment of the unit Y-system redundancy circuit UYR0 included in the Y-system redundancy circuit YR of FIG. 6, and FIGS. 8 and 9 show the unit Y-system redundancy circuit UYR0. Circuit diagrams of one embodiment of the included redundancy enable circuit YREN and relief address storage circuit RYM0 are respectively shown. Further, FIG. 10 shows a block diagram of one embodiment of the redundant bit line selection circuit YRS0 included in the unit Y-system redundant circuit UYR0 of FIG. 7, and FIG. 11 shows the redundant bit line selection circuit YRS0. A circuit diagram of one embodiment of the redundant address comparison circuit RYAC0 is shown. In addition, FIG. 12 shows a conceptual diagram of an embodiment for explaining bit line relief, that is, column relief by the Y-system redundant circuit YR of FIG. Based on these drawings, the specific configuration and operation of the Y-system redundant circuit YR included in the dynamic RAM of this embodiment and its features will be described.
[0049]
In the description relating to FIG. 7, the unit Y-system redundancy circuits UYR0 to UYR3 will be described with the unit Y-system redundancy circuit UYR0. Further, in the description relating to FIG. 9, the relief address storage circuits RYM0 to RYM7 are described using the relief address storage circuit RYM0, and in the description relating to FIGS. explain.
[0050]
In FIG. 6, Y-system redundancy circuit YR includes four unit Y-system redundancy circuits UYR0 to UYR3 provided corresponding to banks BNK0 to BNK3. For example, three sets of predecode signals YPD00 to YPD07, YPD30 to YPD37 and YPD60 to YPD67 are commonly supplied from the Y predecoder YP to these unit Y-system redundant circuits. Also, 16-bit mat row selection signals MRS0 to MRSF are commonly supplied from the mat selection circuit MS, and the internal control signal RFEB is commonly supplied from the timing generation circuit TG.
[0051]
The predecode signals YPD00 to YPD07 are not particularly limited. For example, the predecode signals YPD30 are alternatively set to a high level by decoding a 3-bit internal Y address signal corresponding to the Y address signals AY0 to AY2. ... To YPD 37 are alternatively set to the high level by decoding the 3-bit internal Y address signals corresponding to the Y address signals AY3 to AY5. Predecode signals YPD60 to YPD67 decode 3-bit internal Y address signals corresponding to Y address signals AY6 and AY7 and Y address signal AY8 for selectively designating memory mats adjacent in the row direction. Therefore, it is alternatively set to a high level. Further, the mat row selection signals MRS0 to MRSF are alternatively set to a high level such as the power supply voltage VCC by decoding an internal X address signal corresponding to predetermined four bits of the X address signals AX0 to AXi. The control signal RFEB is selectively set to the low level such as the ground potential VSS after the mat row selection signals MRS0 to MRSF are alternatively set to the high level.
[0052]
In this embodiment, the number n + 1 of complementary bit lines constituting the memory array of each memory mat of the banks BNK0 to BNK3 is not particularly limited, but is 512, and the number k + 1 of the bit line selection signals YS0 to YSK is One half or 256. Therefore, the bit line selection signals YS0 to YSk are alternatively generated according to the 8-bit Y address signals AY0 to AY7, and the upper bits, that is, the Y address signal AY8, alternatively select the memory mat columns MC0 to MCF. It is the least significant bit to specify. As described above, redundant bit lines RB0 * to RB3 * provided in the memory array of each memory mat are shared by two adjacent memory mats. Therefore, Y-system redundancy circuit YR has Y address signal AY8 for identifying adjacent memory mats in addition to Y address signals AY0 to AY7 for alternatively generating bit line selection signals YS0 to YSk. Necessary.
[0053]
On the other hand, in the dynamic RAM of this embodiment, as shown in FIG. 2, four memory mat columns are simultaneously activated by a combination of memory mat columns MC0, MC4, MC8 and MCF, for example. The complementary bit line selection operation by the signals YS0 to YSk and the defect relief by the redundant bit lines RB0 * to RB3 * are performed in units of four memory mats which are simultaneously activated. In other words, in the banks BNK0 to BNK3, two sets of redundant bit lines are provided corresponding to four memory mat columns, and a total of eight sets of redundant bit lines are provided, and a Y-system redundant circuit provided corresponding to each bank. The YR unit Y-system redundant circuits UYR0 to UYR3 are configured to selectively generate eight redundant bit line selection drive signals YR000B to YR031B, YR100B to YR131B, YR200B to YR231B, and YR300B to YR331B, respectively.
[0054]
Here, the unit Y-system redundancy circuits UYR0 to UYR3 of the Y-system redundancy circuit YR correspond to the redundancy bit line selection drive signals YR000B to YR031B, as represented by the unit Y-system redundancy circuit UYR0 in FIG. Eight relief address storage circuits RYM0 to RYM7 and redundant bit line selection circuits YRS0 to YRS7 provided, and one redundancy enable circuit YREN provided in common to these relief address storage circuits and redundancy bit line selection circuits are included. . Among them, the redundancy enable circuit YREN and the relief address storage circuits RYM0 to RYM7 are commonly supplied with the mat row selection signals MRS0 to MRSF from the mat selection circuit MS and the internal control signal RFEB from the timing generation circuit TG. Supplied.
[0055]
On the other hand, the predecode signals YPD00 to YPD07 to YPD60 to YPD67 are commonly supplied from the Y predecoder YP to the redundant bit line selection circuits YRS0 to YRS7 of the unit Y-system redundant circuit UYR0 and the corresponding relief address storage circuit RYM0. The RYM7 supplies 9-bit relief address signals RYA00 to RYA08 to RYA70 to RYA78, respectively, and the redundant enable circuit YREN supplies the redundant enable signal YREB in common. Output signals of the redundant bit line selection circuits YRS0 to YRS7 are supplied as redundant bit line drive signals YR000B to YR001B to YR030B to YR031B to the Y address decoder YD of the corresponding bank BNK0.
[0056]
As shown in FIG. 8, the redundancy enable circuit YREN of the unit Y-system redundancy circuit UYR0 includes two fuse blocks FB1 and FB2. Each of the fuse blocks FB1 and FB2 includes eight fuses F1 or F2. Among these, the upper terminal of the fuse F1 constituting the fuse block FB1 is commonly coupled to the internal node na, that is, the input terminal of the inverter V3 via the corresponding N-channel MOSFETNA, and the lower terminal is coupled to the ground potential VSS. Similarly, the upper terminal of the fuse F2 constituting the fuse block FB2 is commonly coupled to the internal node na via the corresponding N-channel MOSFET NB, and the lower terminal is coupled to the ground potential VSS.
[0057]
In this embodiment, as described above, the defective bit lines are repaired independently by the redundant bit lines RB0 * to RB3 * for each memory mat row, and the redundant bit line selection signals RYS0 to RYS1 are stored in the same column. Are shared by 16 memory mats. For this reason, the fuses F1 and F2 of the fuse blocks FB1 and FB2 are associated with the memory mat rows MR0 to MRF of the corresponding four memory mats of the bank BNK0, and defect relief by redundant bit lines is performed in the corresponding memory mat rows. Selectively disconnected when done.
[0058]
Redundancy enable circuit YREN further includes a NOR gate NO1. The internal control signal RFEB is supplied to one input terminal of the NOR gate NO1 through two inverters V1 and V2, and the other input terminal is coupled to the output terminal of the inverter V3. Two P-channel MOSFETs P1 and P2 are provided between the power supply voltage VCC and the internal node na, that is, the input terminal of the inverter V3. Among these, the inverted signal of the internal control signal RFEB is supplied to the gate of the MOSFET P1 through the inverter V1, and the output signal of the inverter V3 is supplied to the gate of the MOSFET P2. The output signal of the NOR gate NO1 is inverted by the inverter V4 and then becomes the redundancy enable signal YREB.
[0059]
When the dynamic RAM is not selected and the internal control signal RFEB is set to the high level, in the redundancy enable circuit YREN, the output signal of the inverter V2 becomes a high level like the power supply voltage VCC, and the redundancy enable signal YREB Regardless of the node na, it is set to an invalid level, that is, a high level. At this time, the output signal of the inverter V1 becomes a low level like the ground potential VSS, and the MOSFET P1 is turned on. Further, the mat row selection signals MRS0 to MRSF are all set to the low level, and the MOSFETs NA and NB of the fuse blocks FB1 and FB2 are all turned off. Therefore, the internal node na is precharged to a high level like the power supply voltage VCC via the MOSFET P1, and the output signal of the inverter V3 is set to a low level. As a result, the MOSFET P2 is also turned on to assist the precharge operation of the internal node na.
[0060]
When the dynamic RAM is selected, the mat row selection signals MRS0 to MRSF are alternatively set to the high level, and the internal control signal RFEB is set to the low level with a slight delay. In the redundancy enable circuit YREN, the corresponding MOSFETNA or NB of the fuse blocks FB1 and FB2 are alternatively turned on in response to the alternative high level of the mat row selection signals MRS0 to MRSF. In response to the low level of the internal control signal RFEB, the output signal of the inverter V2 is set to low level, the output signal of the inverter V1 is set to high level, and the MOSFET P1 is turned off. Therefore, when the fuse F1 or F2 corresponding to the MOSFET NA or NB in the on state is not in the cut state, that is, in the memory mat row designated by the mat row selection signals MRS0 to MRSF, the defect due to the redundant bit lines RB0 * to RB3 * When the relief is not performed, the high level of the internal node na is discharged through the fuse F1 or F2 which is not in the cut state, and becomes the low level. As a result, the output signal of the inverter V3 becomes high level, and the redundancy enable signal YREB remains high level.
[0061]
On the other hand, if the fuse F1 or F2 corresponding to the MOSFETNA or NB in the ON state of the fuse blocks FB1 and FB2 is in a disconnected state, in other words, a redundant bit line in the memory mat row designated by the mat row selection signals MRS0 to MRSF. When defect repair is performed by RB0 * to RB3 *, the level of the internal node na is maintained at a high level regardless of whether the MOSFETNA or NB is in an on state. For this reason, the output signal of the inverter V3 changes to the low level, the output signal of the NOR gate NO1 becomes the high level, and the redundancy enable signal YREB is set to the effective level, that is, the low level. For these reasons, the redundancy enable signal YREB is selectively set to the low level when the dynamic RAM is in the selected state and the defect relief by the redundant bit line is performed in the designated memory mat row of the designated bank. It will be said that.
[0062]
Next, the relief address storage circuits RYM0 to RYM7 are, as representatively shown in the relief address storage circuit RYM0 of FIG. 9, 18 fuse blocks FB10 to FB10 having the same configuration as the fuse blocks FB1 and FB2 of FIG. Includes FB18 as well as FB20-FB28. These fuse blocks are paired in combinations of FB10 and FB20, FB11 and FB21, FB12 and FB22, FB13 and FB23, FB14 and FB24, FB15 and FB25, FB16 and FB26, FB17 and FB27, and FB18 and FB28, respectively. The commonly coupled drains of MOSFETNA and NB constituting the paired fuse blocks are coupled to corresponding internal nodes n0 to n8, respectively.
[0063]
Internal nodes n0-n8 are respectively coupled to the input terminals of corresponding inverter V6. Further, P channel type precharge MOSFETs P3 and P4 are provided between the power supply voltage VCC and the internal nodes n0 to n8, respectively, and the output signal of the inverter V6 passes through the corresponding inverter V7, and the relief address signal RYA00 to RYA00. RYA08. An inverted signal of the internal control signal RFEB by the inverter V5 is commonly supplied to the gate of the MOSFET P3, and the gate of the MOSFET P4 is coupled to the output terminal of the corresponding inverter V6.
[0064]
The fuse blocks FB10 and FB20, FB11 and FB21, FB12 and FB22, FB13 and FB23, FB14 and FB24, FB15 and FB25, FB16 and FB26, FB17 and FB27, and FB18 and FB28, respectively, a total of 16 fuses F1 and F2 is selectively disconnected when the corresponding bit of the relief address assigned to the corresponding redundant bit line of the corresponding memory mat row is set to logic "1". The fuses F1 and F2 are cut off when the corresponding mat row selection signals MRS0 to MRSF are set to the high level and the internal control signal RFEB is set to the low level, as in the case of the redundancy enable circuit YREN. Determined selectively. As a result, the relief address signals RYA00 to RYA08 select the corresponding memory mat row and the dynamic RAM is selected, and the fuse blocks FB10 and FB20, FB11 and FB21, FB12 and FB22, FB13 and FB23, FB14 and When the fuses F1 and F2 corresponding to FB24, FB15 and FB25, FB16 and FB26, FB17 and FB27, and FB18 and FB28 are in the cut state, they are selectively set to the high level.
[0065]
Next, the redundant bit line selection circuits YRS0 to YRS7 include three redundant address comparison circuits RYAC1 to RYAC3 and their second to fourth, as representatively shown by the redundant bit line selection circuit YRS0 in FIG. The input terminal includes a 4-input NAND gate NA1 for receiving address match signals RAM1 to RAM3 as output signals of redundant address comparison circuits RYAC1 to RYAC3.
[0066]
The redundant address comparison circuit RYAC1 constituting the redundant bit line selection circuit YRS0 is supplied with 8-bit predecode signals YPD00 to YPD07 from the Y predecoder YP and at the same time a 3-bit relief address signal RYA00 from the relief address storage circuit RYM0. ~ RYA02 is supplied. The redundant address comparison circuit RYAC2 is supplied with 8-bit predecode signals YPD30 to YPD37 from the Y predecoder YP and is supplied with 3-bit relief address signals RYA03 to RYA05 from the relief address storage circuit RYM0. The address comparison circuit RYAC3 is supplied with 8-bit predecode signals YPD60 to YPD67 from the Y predecoder YP and 3-bit relief address signals RYA06 to RYA08 from the relief address storage circuit RYM0. The first input terminal of the NAND gate NA1 is supplied with an inverted signal by the inverter V8 of the redundant enable signal YRE as an output signal of the redundant enable circuit YREN, and the output signal becomes the redundant bit line drive signal YR000B.
[0067]
Here, redundant address comparison circuits RYAC1 to RYAC3 include eight unit redundant address comparison circuits UAC0 to UAC7 as representatively shown in redundant address comparison circuit RYAC1 in FIG. Each includes a 3-input NAND gate NA2, two inverters VC and VD, and one clocked inverter VE, as representatively shown in the unit redundant address comparison circuit UAC0 of FIG. The first to third input terminals of the NAND gate NA2 constituting the unit redundant address comparison circuits UAC0 to UAC7 have a predetermined combination of non-inverted signals of the rescue address signals RYA00 to RYA02 or inverted signals of the inverters V9 to VB, respectively. Supplied.
[0068]
That is, for example, the first to third input terminals of the NAND gate NA2 constituting the unit redundant address comparison circuit UAC0 are supplied with the inverted signals by the inverters V9 to VB of the relief address signals RYA00 to RYA02, respectively. A non-inverted signal of the rescue address signal RYA00 and inverted signals of the rescue address signals RYA01 and RYA02 by the inverters VA and VB are supplied to the first to third input terminals of the NAND gate NA2 constituting the UAC1, respectively. Further, for example, the inverted signal of the relief address signal RYA00 by the inverter V9 and the non-inverted signals of the relief address signals RYA01 and RYA02 are supplied to the first to third input terminals of the NAND gate NA2 constituting the unit redundant address comparison circuit UAC6, respectively. The non-inverted signals of the relief address signals RYA00 to RYA02 are supplied to the first to third input terminals of the NAND gate NA2 constituting the unit redundant address comparison circuit UAC7.
[0069]
On the other hand, the inverted signals of the corresponding predecode signals YPD00 to YPD07 by the inverter VD are supplied to the input terminals of the clocked inverter VE constituting the unit redundant address comparison circuits UAC0 to UAC7, respectively. The non-inverted control terminal of the clocked inverter VE is supplied with the inverted signal of the output signal of the corresponding NAND gate NA2 by the inverter VC, and the inverted control terminal is supplied with the output signal of the corresponding NAND gate NA2. The All the output terminals of the clocked inverter VE are commonly coupled, and the potential thereof is the output signal of the redundant address comparison circuit RYAC1, that is, the address match signal RAM1.
[0070]
As a result, the output signal of the unit redundancy address comparison circuit UAC0 is the same as that of the relief address signal RYA00 when the output signal of the NAND gate NA2 constituting the unit redundancy address comparison circuit UAC0 is at the low level and the corresponding predecode signal YPD00 is at the high level. When all of RYA02 are set to logic "0" and the lower 3 bits of Y address signals AY0 to AY2 supplied from the outside at the time of access are all set to logic "0", a high level such as power supply voltage VCC is selectively set. Become a level. When the output signal of the NAND gate NA2 is low level and the predecode signal YPD00 is low level, the output signal of the unit redundant address comparison circuit UAC0 is low level like the ground potential VSS, and the output signal of the NAND gate NA2 is high level. When it is done, it becomes a high impedance state.
[0071]
Similarly, the output signal of the unit redundancy address comparison circuit UAC1 is selectively high when the logical values of the relief address signals RYA00 to RYA02 and the Y address signals AY0 to AY2 are both “001”, and the unit redundancy address comparison is performed. The output signals of the circuits UAC6 and UAC7 are selectively set to the high level when the logical values of the relief address signals RYA00 to RYA02 and the Y address signals AY0 to AY2 are both “110” or “111”.
[0072]
As a result, the redundant address comparison circuit RYAC1 outputs the lower 3 bits of the relief address signals RYA00 to RYA02 output from the relief address storage circuit RYM0 and the lower 3 bits of the Y address signals AY0 to AY0 supplied from the external access device upon access. AY2 acts to compare and collate 3 bits at a time, and when both addresses match, the output signal, that is, the address match signal RAM1 is selectively set to the high level. Similarly, the redundant address comparison circuits RYAC2 and RYAC3 are supplied from an external access device when accessing the middle and upper 3 bits of the relief address signals RYA03 to RYA05 or RYA06 to RYA08 output from the relief address storage circuit RYM0. 3 bits of Y address signals AY3 to AY5 or AY6 to AY8 of the upper or upper 3 bits are collectively compared and verified, and when the two addresses match, the output signal, that is, the address match signal RAM2 or RAM3 is selectively selected. High level.
[0073]
As described above, the address match signals RAM1 to RAM3 output from the redundant address comparison circuits RYAC1 to RYAC3 are supplied to the second to fourth input terminals of the NAND gate NA1 of the redundant bit line selection circuit YRS0, respectively. The first input terminal of the NAND gate NA1 is supplied with an output signal of the redundancy enable circuit YREN, that is, an inverted signal of the redundancy enable signal YRE by the inverter V8, and the output signal becomes the redundancy bit line drive signal YR000B.
[0074]
As a result, the output signal of the NAND gate NA1, that is, the redundant bit line drive signal YR000B, corresponds to the corresponding memory mat when the redundant enable signal YREB is set to high level and the address match signals RAM1 to RAM3 are both set to high level. Defect relief is performed by redundant bit lines in a row, and relief address signals RYA00 to RYA08 held by relief address storage circuit RYM0 and Y address signals AY0 to AY8 supplied from an external access device at the time of access match all bits In this case, the low level is selectively set. Redundant bit line drive signal YR000B is supplied to Y address decoder YD and receives the high level of redundant bit line drive signal YR000B to select redundant bit lines corresponding to redundant bit lines RB0 * and RB1 * of the specified memory mat. The signal RYS0 is selectively set to the high level.
[0075]
As described above, in the dynamic RAM of this embodiment, the sub IO lines provided in the memory mats of the banks BNK0 to BNK3 are shared by two memory mats adjacent in the row direction. Therefore, the redundancy bit line selection circuits YRS0 to YRS7 provided in the unit Y-system redundancy circuits UYR0 to UYR3 of the Y-system redundancy circuit YR, as described above, need relief for identifying two memory mats adjacent in the row direction. The address signals RYA08 to RYA78 and the Y address signal AY8 are compared and verified. For this reason, in the dynamic RAM of this embodiment, as shown in FIG. 12, for example, of the paired memory mats MAT00 and MAT01, three sets of complementary bits that have some obstacle in the memory array MAT01 on the memory mat MAT01 side. Even when the lines Bq + 1 *, Br + 1 *, and Bs * are detected, the redundant bit lines RB2 * and RB3 * remaining on the memory array MARY00 side can be repaired. As a result, it is possible to increase the defect repair efficiency of the dynamic RAM and increase the product yield.
[0076]
FIG. 13 shows a conceptual diagram of the second embodiment for explaining column relief by the Y-system redundant circuit YR of the dynamic RAM of FIG. Since the present embodiment basically follows the embodiment of FIG. 12, only the portions different from this will be described.
[0077]
In FIG. 13, in the dynamic RAM of this embodiment, eight memory mats arranged in the same memory mat row are divided into groups, and for example, eight memory arrays MARY00 to MARY07 constituting one memory mat group are , 6 sets of redundant bit lines provided in a predetermined memory mat, that is, in a memory array MARY07, are shared. As illustrated in the figure, these redundant bit lines are selectively selected two by two when the corresponding redundant bit line selection signals RYS0 to RYS2 are set to the high level. For example, the memory array MARY01, It can be used to relieve defective bit lines detected by MARY04 and MARY05. As a result, the required number of redundant bit lines can be reduced, the defect repair efficiency of the dynamic RAM can be further increased, and the product yield can be increased.
[0078]
In this embodiment, the wiring length of the sub IO line SIO * provided in each sense amplifier is half the word line direction of the memory arrays MARY00 to MARY07, that is, the row direction length. For this reason, the load capacity of the sub IO line SIO * is reduced, and the dynamic RAM can be speeded up. However, since the wiring length of the sub IO line SIO * is one half of the length in the row direction of the memory array, the defective bit line and the redundant bit line cannot be connected to the common sub IO line.
[0079]
In order to cope with this, in the dynamic RAM of this embodiment, when any memory mat included in the same memory mat group is activated, the memory array MARY07 including six sets of redundant bit lines is always activated. State. At this time, when the dynamic RAM is set to the read mode, the main IO lines MI7 * and MI8 * corresponding to the memory array MARY07 are selectively read in response to the redundant bit lines being selected. When the dynamic RAM is set to the write mode, the write signal is transmitted to the main IO lines MI7 * and MI8 * regardless of the redundant bit line selection state, and the redundant bit line is selected. In response to this state, a substantial write operation is performed, and the speed of the write operation of the dynamic RAM is increased.
[0080]
The effects obtained from the above embodiments are as follows. That is,
(1) In a dynamic RAM or the like using a hierarchical IO system, the sub IO line has a wiring length that is twice the row length of the memory array, for example, and is shared by, for example, two memory mats adjacent in the row direction. Each of these memory mats is provided with, for example, two sets of redundant bit lines, and is shared by, for example, two memory mats sharing the sub IO line, so that a total of four sets provided in two adjacent memory mats are provided. The redundant bit lines can be used for repairing defective bit lines detected by two memory mats.
(2) According to the above item (1), it is possible to increase the defect repair efficiency of a dynamic RAM or the like and increase the product yield.
[0081]
(3) The sub IO line is, for example, half the length of the memory array in the row direction, and the redundant bit line is, for example, one of q memory mats arranged adjacent to each other in the row direction. The redundant bit lines that are aggregated and provided in any one of the q memory mats arranged adjacent to each other in the row direction are shared by the q memory mats arranged in an aggregate and arranged in q memories. An effect is obtained that it can be used to relieve defective bit lines detected by the mat.
(4) According to the above item (3), it is possible to further improve the defect relief efficiency of the dynamic RAM or the like and increase the product yield.
(5) According to the above item (3), it is possible to shorten the wiring length of the sub IO line and reduce the load capacity, thereby obtaining the effect that the dynamic RAM or the like can be operated at high speed.
[0082]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the dynamic RAM can include an arbitrary number of banks, and can have an arbitrary bit configuration such as × 4 bits or × 16 bits. The dynamic RAM does not require the address multiplex system to be an indispensable condition, and the block configuration, the names and combinations of the start control signal, the address signal, the internal control signal, etc., the effective level, etc. adopt various embodiments. sell.
[0083]
2 and 3, the banks BNK0 to BNK3 can be divided into an arbitrary number of memory mats. In addition, the number of memory mats that are simultaneously activated can be arbitrarily set, and the combinations thereof are also the same. The semiconductor substrate CHIP can take an arbitrary shape, and its specific arrangement can also take various embodiments.
[0084]
4 and 5, each of the memory arrays represented by the memory array MARY00 can include an arbitrary number of redundant bit lines, and can also include redundant sub word lines. Redundant bit lines provided in each memory array can be shared by any number of memory mats adjacent in the row direction on condition that the sub IO lines are similarly shared. The specific configuration of each memory array, sense amplifier, intersection region, MOSFET conductivity type, and the like are not limited by this embodiment. 6 to 11, the block configuration of the Y-system redundant circuit YR and the specific configuration of each part configuring the Y-system redundant circuit YR can take various embodiments.
[0085]
In FIG. 13, the number of memory mats constituting the memory mat group can be arbitrarily set. Redundant bit lines can be provided in an arbitrary memory array, and the number of redundant bit lines can be set arbitrarily. Further, the wiring length of each sub IO line may be the same as the length in the row direction of the memory array, for example.
[0086]
In the above description, the case where the invention made mainly by the present inventor is applied to the dynamic RAM, which is the field of use behind it, has been described. However, the present invention is not limited to this. The present invention can also be applied to various types of memory integrated circuit devices configured and logic integrated circuit devices including such memory integrated circuit devices. The present invention can be widely applied to at least a semiconductor memory device adopting a hierarchical IO system and a device or system including the same.
[0087]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like that employs a hierarchical IO system, the sub IO line has a wiring length that is twice the row length of the memory array, for example, and is shared by, for example, two memory mats adjacent in the row direction. Each of these memory mats is provided with, for example, two sets of redundant bit lines, and is shared by two memory mats sharing the sub IO line. In addition, the sub IO line is, for example, half the length of the memory array in the row direction, and the redundant bit lines are integrated into one of, for example, q memory mats arranged adjacent to each other in the row direction. And shared by q memory mats arranged adjacent to each other. As a result, a total of four sets of redundant bit lines provided in two adjacent memory mats are used to repair defective bit lines detected in the two memory mats, or the wiring length of the sub IO line is shortened. Then, while reducing the load capacity, the redundant bit lines collectively provided in any of q pieces arranged adjacent to each other in the row direction can be relieved for defective bit lines detected by q memory mats. Therefore, it is possible to increase the defect repair efficiency of a dynamic RAM or the like and increase the product yield.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.
FIG. 2 is a substrate layout diagram showing one embodiment of the dynamic RAM of FIG. 1;
FIG. 3 is an enlarged layout view showing an example of a bank BNK0 included in the dynamic RAM of FIG. 1;
4 is a block diagram showing an embodiment of a memory mat MAT00 included in the bank BNK0 of FIG.
5 is a partial circuit diagram showing a first embodiment of a memory array MARY00 and its peripheral circuits included in the memory mat MAT00 of FIG. 4; FIG.
6 is a block diagram showing an embodiment of a Y-system redundant circuit included in the dynamic RAM of FIG. 1. FIG.
7 is a block diagram showing an embodiment of a unit Y-system redundant circuit UYR0 included in the Y-system redundant circuit of FIG.
8 is a circuit diagram showing one embodiment of a redundancy enable circuit YREN included in the unit Y-system redundancy circuit UYR0 of FIG.
FIG. 9 is a circuit diagram showing one embodiment of a relief address storage circuit RYM0 included in the unit Y-system redundant circuit UYR0 of FIG.
10 is a block diagram showing one embodiment of a redundant bit line selection circuit YRS00 included in the unit Y-system redundant circuit UYR0 of FIG.
11 is a circuit diagram showing one embodiment of a redundant address comparison circuit RYAC1 included in the redundant bit line selection circuit YRS00 of FIG.
12 is a conceptual diagram showing a first embodiment for explaining column relief by a Y-system redundant circuit of the dynamic RAM in FIG. 1; FIG.
13 is a conceptual diagram showing a second embodiment for explaining column relief by the Y-system redundant circuit of the dynamic RAM of FIG. 1; FIG.
FIG. 14 is a conceptual diagram showing an example for explaining column relief by a Y-system redundant circuit of a dynamic RAM developed by the inventors of the present application prior to the present invention.
[Explanation of symbols]
BNK0 to BNK3 ... Bank, MARY ... Memory array, XD ... X address decoder, XP ... X predecoder, MS ... Mat selection circuit, XB ... X address buffer, SA ... Sense amplifier, YD ... Y address decoder, YR ... Y redundant circuit, YP ... Y predecoder, YB ... Y address buffer, MA ... main amplifier, IO ... data input / output circuit, TG ... timing generation circuit, IOB0 to IOB7 ... I / O data bus.
D0 to DF: Input or output data or input / output terminal thereof, RASB: Row address strobe signal or input terminal thereof, CASB: Column address strobe signal or input terminal thereof, WEB: Write enable signal or input terminal thereof, A0 to Ai: Address signal or its input terminal.
CHIP: Semiconductor substrate, MR0 to MRF: Memory mat row, MC0 to MCF: Memory mat column, MWD: Main word line drive circuit.
SWD: Sub word line drive circuit, MAT00 to MAT0F to MATF0 to MATFF ... Memory mat, MWL ... Main word line, SWL ... Sub word line, BL ... Bit line, IS ... Intersection region, YS ... Bit line Selection signal, RYS: Redundant bit line selection signal.
SWD00 to SWD03... Sub word line drive circuit, SA00 to SA11... Sense amplifier, IS00 to IS11... Crossing region, MW0 to MWj ... main word line, SW0 to SWm. ~ Bs * ... complementary bit lines, RB0 * to RB3 * ... redundant bit lines, YS0 to Ysk ... bit line selection signals, RYS0 to RYS1 ... redundant bit line selection signals, MI0 * to MI8 * ... main IO Line, SI00 * to SI11 *, SIO ... Sub IO line.
UA: Unit sense amplifier, AA: Auxiliary main amplifier, x0 to x3: Sub word line selection drive signal, G1 to G8: Drive gate, IS0 to IS1: Sub IO line selection signal.
UYR0 to UYR3... Unit Y system redundancy circuit, YPD00 to YPD07 to YPD60 to YPD67... Y predecode signal, MRS0 to MRSF... Mat row selection signal, YR000B to YR031B to YR300B to YR331B. .
YREN: redundancy enable circuit, YREB: redundancy enable signal, RYM0 to RYM7: relief address storage circuit, RYA00 to RYA08 to RYA70 to RYA78: relief address signal, YRS0 to YRS7: redundancy bit line selection circuit.
FB1 to FB2, FB10 to FB18, FB20 to FB28... Fuse block, F1 to F2... Fuse, na, n0 to n8.
RYAC1 to RYAC3... Redundant address comparison circuit, RAM1 to RAM3... Address match signal.
P1 to P4... P channel MOSFET, N1 to N8, NA to NB... N channel MOSFET, V1 to VE... Inverter, NA1 to NA2... NAND gate, NO1.

Claims (4)

A plurality of memory mats each including a memory array divided in a word line direction and a bit line direction, and sense amplifiers including switch means for selectively connecting a designated bit line and a sub IO line When,
A main IO line to which the designated sub IO line is selectively connected;
The sub IO line is extended along the sense amplifier, and the sub IO line is arranged in the word line direction, and is shared by a predetermined number of memory mats that do not compete with the simultaneously selected main IO lines,
The main IO line is extended along the word line selection circuit of the memory array including a plurality in the bit line direction, and is selectively selected by a selection switch at an intersection with the sub IO line of the memory array including the plurality. Connected,
Each of the memory arrays includes a predetermined number of redundant bit lines,
The redundant bit lines, dynamic RAM, wherein the redundant bit line selection circuit is intended to be enabling replaced by any of the defective bit line in the memory mat of a predetermined number of sharing the sub IO line. In claim 1,
The dynamic RAM includes a plurality of banks,
Each of the banks includes p × q memory mats arranged in a lattice in the word line direction and the bit line direction,
The dynamic RAM, wherein the redundant bit line selection circuit for selecting the redundant bit line is shared by q memory mats arranged in the same bit line direction. A plurality of memory mats each including a memory array divided in a word line direction and a bit line direction, and sense amplifiers including switch means for selectively connecting a designated bit line and a sub IO line When,
A main IO line to which the designated sub IO line is selectively connected;
The sub IO line is extended along the sense amplifier, and the sub IO line is arranged in the word line direction, and is shared by a predetermined number of memory mats that do not compete with the simultaneously selected main IO lines,
The main IO line is extended along the word line selection circuit of the memory array including a plurality in the bit line direction, and is selectively selected by a selection switch at an intersection with the sub IO line of the memory array including the plurality. Connected,
Redundant bit lines are collectively provided in any one of the predetermined number of the memory mats corresponding to the sub IO lines,
The redundant bit lines, dynamic RAM, wherein the redundant bit line selection circuit is intended to be enabling replaced by any of the defective bit line in the memory mat of a predetermined number of sharing the sub IO line. In claim 1 or claim 3,
The main IO line provided corresponding to the memory mat including the redundant bit line is selectively provided on condition that the redundant bit line is selected when the dynamic RAM is in the read mode. A dynamic RAM characterized in that when a read signal is transmitted and the dynamic RAM is set to a write mode, the write signal is transmitted regardless of the selected state of the redundant bit line.

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