JPH09180439A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a chip size and reduce the cost by a method wherein the predetermined parts of a culumn decoder and a column predecoder are commonly used by a plurality of banks and the unit column decoders are provided so as to correspond to bit line selection signals of (q) bits. SOLUTION: A synchronous DRAM has a bank (BNK) 0 and a BNK 1 and, further, a block writing mode in which identical data are written in (p) (in this case p=8) addresses which are continuous in a column direction simultaneously. Further, the parts of a column decoder(CD) and a column predecoder(CPD) are shared by the BNK 0 and the BNK 1. At the same time, the unit CD's of the CD are provided so as to correspond to bit line selection signals of (q) bits (in this case q=8) and (q) (8) column addresses are successively allocated to every (p)th (8th) unit CD. With this constitution, the chip size of the synchronous DRAM can be reduced and the cost can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, for example, to a synchronous DRAM (dynamic random access memory) having a block write mode and a technique which is particularly effective in reducing the cost thereof.

[0002]

2. Description of the Related Art There is a synchronous DRAM which operates in synchronization with a clock signal and has, for example, a x8 bit structure. This synchronous DRAM is often used as an image memory, and for example, there is one having a so-called block write mode for simultaneously writing the same data to eight addresses continuous in the column direction.

[0003]

In recent years, advances in miniaturization and high integration technology in semiconductor integrated circuits have been remarkable, and semiconductor memory devices such as synchronous DRAM have also been increased in scale.
The capacity is increasing. Under such circumstances, the inventors of the present application have found that the synchronous DRA having the block write mode is used.
The following problems were encountered in an attempt to further increase the size and capacity of M. That is, the conventional synchronous DR that the inventors of the present application have targeted for large scale and large capacity.
AM is a pair of banks BNK as illustrated in FIG.
Column predecoders CPD0 and CP1 and column decoders CD0 and CD1 provided with 0 and BNK1 and used for bit line selection are individually provided corresponding to these banks. In addition, the column decoder CD0
, And CD1 include a predetermined number of unit column decoders provided corresponding to a predetermined number of continuous column addresses, that is, a bit line selection signal of a predetermined bit, and laid out in the order of addresses.

On the other hand, in the block write mode of the synchronous DRAM, as described above, for example, eight consecutive addresses in the column direction are simultaneously accessed, so that each unit column decoder of the column decoder is connected to a predetermined number of consecutive columns. In the conventional method of arranging addresses in the order of assigned addresses, one unit column decoder must simultaneously set a plurality of bit line selection signals to an effective level, so that sufficient driving capability cannot be obtained. As a result, restrictions are imposed on the address allocation of the column decoder, and column decoders and column predecoders are provided for each bank, which increases the chip size as the synchronous DRAM becomes larger and larger in capacity. The cost reduction of the synchronous DRAM is hindered.

An object of the present invention is to provide a method of constructing a column selection circuit suitable for a synchronous DRAM having a plurality of banks and having a block write mode. Another object of the present invention is to reduce the chip size of a synchronous DRAM having a block write mode,
It is to reduce the cost. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a synchronous DRAM or the like having a plurality of banks and having a block write mode for simultaneously writing the same data to p consecutive addresses in the column direction, a predetermined part of a column decoder and a column predecoder is provided in a plurality of banks. In addition, the unit column decoders of the column decoders are provided corresponding to the q-bit bit line selection signals, and q column addresses are sequentially assigned to these unit column decoders at intervals of p.

According to the above means, it is possible to assign an address suitable for the block write mode to the column decoder and reduce the layout required area of the column decoder and the column predecoder by partially sharing the address. As a result, the chip size of a synchronous DRAM or the like having a plurality of banks and having a block write mode can be reduced and the cost thereof can be reduced.

[0008]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM (semiconductor memory device) to which the present invention is applied. First, an outline of the configuration and operation of the synchronous DRAM of this embodiment will be described with reference to FIG. The circuit elements forming each block in FIG. 1 are not particularly limited, but known MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are generically called insulated gate field effect transistors. It is formed on one semiconductor substrate such as single crystal silicon by the manufacturing technology of integrated circuits.

In FIG. 1, the synchronous DRAM of this embodiment includes a pair of banks BNK0 and BNK1.
Each of these banks has a memory array ARY0 or ARY arranged to occupy most of its layout area.
1 and row decoders RD0 and RD1 and sense amplifier SA0 which are direct peripheral circuits of these memory arrays.
And SA1, and main amplifiers MA0 and MA1 including a write amplifier and a read amplifier, respectively. A column decoder CD, a part of which is shared by both banks, is provided between the banks BNK0 and BNK1.

Each of the memory arrays ARY0 and ARY1 constituting the banks BNK0 and BNK1 is not particularly limited, but substantially 2,048 word lines arranged in parallel in the vertical direction in the figure and parallel to the horizontal direction. And substantially 4,096 sets of complementary bit lines arranged in parallel. At the intersections of these word lines and complementary bit lines, there are substantially 2,048 × 4,096 pieces of information storage capacitors and address selection MOSFETs, that is, 8,388,6.
08 dynamic memory cells are arranged in a grid pattern. As a result, each of the memory arrays ARY0 and ARY1 has a so-called 8 megabit storage capacity, and the synchronous DRAM has a 2 × 8 mega or 16 megabit storage capacity.

The word lines forming the memory arrays ARY0 and ARY1 of the banks BNK0 and BNK1 are connected to the corresponding row decoders RD0 or RD1 below the word lines and are selectively set to the selected state. These row decoders include 11-bit internal address signals X0 to X excluding the most significant bit from the row address buffer RB.
10 is commonly supplied, and an internal control signal RG (not shown) is commonly supplied from the timing generation circuit TG. Further, the row address buffer RB has X address signals AX0 to AX11 via address input terminals A0 to A11.
Are supplied in a time division manner, and the internal control signal RL is supplied from the timing generation circuit TG.

The row address buffer RB takes in and holds the X address signals AX0 to AX11 input via the address input terminals A0 to A11 in accordance with the internal control signal RL, and at the same time, based on these X address signals, the internal address is stored. The signals X0 to X11 are formed. Among these, the internal address signal X11 of the most significant bit is supplied to the bank selection circuit BS, and the other internal address signals X11
0 to X10 are row decoders RD0 and RD of both banks
1 is commonly supplied.

The bank selection circuit BS decodes the most significant bit internal address signal X11 supplied from the row address buffer RB, and outputs the corresponding bank selection signal BS.
0 or BS1 is selectively set to an effective level, that is, a high level. The bank selection signals BS0 and BS1 are supplied to the corresponding banks BNK0 and BNK1, respectively, and their peripheral circuits, row decoders RD0 and RD1, sense amplifiers SA0 and SA1 and main amplifiers MA0 and M1.
This is a substantial selection control signal for selectively setting A1 in the operating state. Further, these bank selection signals are also supplied to the column predecoder CPD, and the predecode signal A
Y300 to AY370 and AY301 to AY371
Also serves as a selection control signal for selectively generating.

The row decoders RD0 and RD1 of the banks BNK0 and BNK1 are selectively activated by setting the internal control signal RG to high level and the corresponding bank selection signal BS0 or BS1 to high level, respectively. By decoding the internal address signals X0 to X10,
The designated word line of the corresponding memory array ARY0 or ARY1 is selectively set to the high level selected state.

Complementary bit lines forming the memory arrays ARY0 and ARY1 of the banks BNK0 and BNK1 are respectively coupled to the corresponding unit circuits of the sense amplifier SA0 or SA1. For the sense amplifiers SA0 and SA1,
From the column decoder CD, 512-bit bit line selection signals YS00 to YS5110 and YS01 to
YS5111 is supplied to each of them, and an internal control signal PA (not shown) is commonly supplied from the timing generation circuit TG. Further, the column decoder CD includes 8-bit predecode signals YM0 to YM7, AY300 to AY370, A from the column predecoder CPD.
Y301 to AY371 and AY60 to AY67 are supplied.

The column predecoder CPD has a 9-bit internal address signal Y from the column address counter CC.
0 to Y8 are supplied and data input / output circuit IO
To 8-bit mask data MD0 to MD7. Further, the bank selection circuit BS supplies the bank selection signals BS0 to BS1 and the timing generation circuit TG supplies the internal control signals YSE, YOE and BW. Further, the column address counter CC is supplied with its output signal from the column address buffer CB, that is, internal address signals YC0 to YC8 (not shown), and an internal control signal CU from the timing generation circuit TG to supply it to the column address buffer CB. Are Y address signals AY0-A via address input terminals A0-A8.
Y8 is supplied in a time division manner, and an internal control signal CL is supplied from the timing generation circuit TG.

In this embodiment, the synchronous DRA
M has a block write mode in which the same data is simultaneously written to p consecutive addresses in the column direction, that is, 8 addresses. The internal control signal YSE is a synchronous DRAM.
When it is selected in various operation modes including the block write mode, it is set to the high level for a predetermined period at a predetermined timing. Further, the internal control signal YOE is selectively set to high level at the same time as the internal control signal YSE, and returned to low level prior to the internal control signal YSE. Further, the internal control signal BW is set to low level when the synchronous DRAM is selected in the normal operation mode, and selectively set to high level at a predetermined timing when selected in the block write mode.

The column address buffer CB fetches the Y address signals AY0 to AY8 supplied via the address input terminals A0 to A8 in accordance with the internal control signal CL,
The internal address signals YC0 to YC8 are transmitted to the column address counter CC. Further, the column address counter CC takes in and holds the internal address signals YC0 to YC8 transmitted from the column address buffer CB, forms internal address signals Y0 to Y8 based on these internal address signals, and Predecoder C
Supply to PD. When the synchronous DRAM is set to the burst mode, the column address counter CC
Are internal address signals Y0 to Y0 according to the internal control signal CU.
It also has the function of counting up Y8.

The column predecoder CPD is supplied with the internal address signals Y0 to Y8 supplied from the column address counter CC, the mask data MD0 to MD7 supplied from the data input / output circuit IO, and the bank selection circuit BS. Bank selection signals BS0 to BS1 and internal control signals YSE and Y supplied from the timing generation circuit TG.
Based on OE and BW, predecode signals YM0-
YM7, AY300 to AY370, AY301 to AY3
71 and AY60 to AY67 are selectively formed and supplied to the column decoder CD. Also, the column decoder C
D includes 64 unit column decoders UCD provided corresponding to q bits of the bit line selection signal, that is, 8 bits, and predecode signals YM0 to YM7, AY300 to AY370, supplied from the column predecoder CPD.
The bit line selection signal YS00 is obtained by combining AY301 to AY371 and AY60 to AY67.
~ YS5110 or YS01 to YS5111 corresponding bits are alternatively set to the high level. Specific configurations and operations of the column decoder CD and the column predecoder CPD will be described later in detail.

The sense amplifiers SA0 and SA1 of the banks BNK0 and BNK1 are connected to the memory array ARY0 or AR, respectively.
Substantially 4,0 provided corresponding to each complementary bit line of Y1
Each of the 96 unit circuits includes a unit amplifier circuit in which a pair of CMOS inverters are cross-coupled, and a pair of N-channel type switch MOSFETs. Among them, the unit amplifier circuits of the respective unit circuits are selectively and simultaneously activated by setting the internal control signal PA to the high level and the corresponding bank selection signal BS0 or BS1 to the high level, and the memory array. A high level or low level binary read is performed by amplifying a minute read signal output from substantially 4,096 memory cells coupled to a selected word line of ARY0 or ARY1 through a corresponding complementary bit line. Signal.

The switch MOSFETs of each unit circuit are selectively turned on by 8 pairs by the corresponding bit line selection signals YS00 to YS5110 or YS01 to YS5111 being selectively set to the high level, and the memory array ARY0 or 8 sets of corresponding complementary bit lines of ARY1 and complementary common data lines CD00 * to CD70 * or C
D01 * to CD71 * (here, for example, the non-inverted common data line CD00T and the inverted common data line CD00B are collectively denoted by * like the complementary common data line CD00 *. Further, it is validated. A so-called non-inverted signal or the like which is selectively set to the high level at this time is represented by adding T to the end of the name, and an inverted signal or the like which is selectively set to the low level when it is enabled is represented by its name. It is indicated by adding B to the end. The same applies hereinafter) to selectively establish a connection state.

Complementary common data lines CD00 * to CD70 *
Is coupled to the corresponding unit circuit of the main amplifier MA0 on the other side, and complementary common data lines CD01 * to CD
71 * is coupled to the corresponding unit circuit of the main amplifier MA1. The main amplifiers MA0 and MA1 have complementary common data lines CD00 * to CD70 * or CD01 * to
It includes eight unit circuits provided corresponding to the CD 71 *, and each of these unit circuits includes a write amplifier and a read amplifier. Of these, the input terminals of each write amplifier are connected to corresponding internal data buses DBUS0 to DBUS.
7 and its output terminal corresponds to the corresponding complementary common data line CD00 * to CD70 * or CD01 * to CD.
Bound to 71 *. The input terminal of each read amplifier has a corresponding complementary common data line CD00 * to CD70 *.
Alternatively, it is coupled to CD01 * to CD71 *, and its output terminals have corresponding internal data buses DBUS0 to DBUS.
7. For the main amplifiers MA0 and MA1,
Internal control signals RP and WP (not shown) are commonly supplied from the timing generation circuit TG.

Internal data buses DBUS0 to DBUS7
Is coupled to the corresponding unit circuit of the data input / output circuit IO on the other side, and is coupled to the data register DR. The internal control signal DS is supplied to the data register DR from the timing generation circuit TG. here,
The data register DR is an internal data bus DBUS0-D
It includes an 8-bit latch provided corresponding to BUS7. These latches have data input / output terminals D0 to D7 in the set cycle prior to the block write mode.
Write data input from the data input / output circuit IO in accordance with the internal control signal DS is held and supplied to the data input / output circuit IO in the block write mode in which the write operation is executed.

Data input / output circuit IO includes eight unit circuits provided corresponding to internal data buses DBUS0 to DBUS7, and each of these unit circuits includes a data input buffer and a data output buffer. Of these, the input terminals of the respective data input buffers are coupled to the corresponding data input / output terminals D0 to D7, and the output terminals thereof are coupled to the corresponding internal data buses DBUS0 to DBUS7. The input terminal of each data output buffer is coupled to the corresponding internal data bus DBUS0 to DBUS7,
The output terminals are corresponding data input / output terminals D0 to D7.
Is combined with The data input / output circuit IO is supplied with an internal control signal BW and an output control signal DOC (not shown) from the timing generation circuit TG.

The data input buffer of each unit circuit of the data input / output circuit IO stores 8-bit write data input via the data input / output terminals D0 to D7 when the synchronous DRAM is in the normal write mode. The captured data is transferred to the write amplifier corresponding to the main amplifier MA0 or MA1. Further, when the synchronous DRAM is set in a set cycle prior to the block write mode, it is input through the data input / output terminals D0 to D7.
The write data of the bit is fetched and transmitted to the corresponding latch of the data register DR. Furthermore, when the synchronous DRAM is set to the block write mode,
The 8-bit mask data MD0 to MD7 input via the data input / output terminals D0 to D7 are transmitted to the column predecoder CPD, and the write data held by the data register DR is transferred to the main amplifiers MA0 and M0.
It is transmitted to the corresponding write amplifier of A1.

When the synchronous DRAM is set to the write mode including the block write mode, the main amplifier M
Each write amplifier of A0 and MA1 has an internal control signal WP
Is set to the high level and the corresponding bank selection signal BS0
Alternatively, when BS1 is set to a high level, it is selectively activated, and the write data transmitted from the corresponding data input buffer of the data input / output circuit IO via the internal data buses DBUS0 to DBUS7 is used as a predetermined write signal. Then, through the complementary common data lines CD00 * to CD70 * or CD01 * to CD71 *, the memory array A
Write to the selected 8 to 64 memory cells of RY0 or ARY1.

The read amplifiers constituting the main amplifiers MA0 and MA1 of the banks BNK0 and BNK1 operate selectively when the internal control signal RP is set to high level and the corresponding bank selection signal BS0 or BS1 is set to high level. Is set to the complementary common data line CD00 * to CD70 * or CD01 * to from the selected eight memory cells of the corresponding memory array ARY0 or ARY1.
The read signal output via the CD 71 * is amplified and output to the internal data buses DBUS0 to DBUS7. At this time, each data output buffer of the data input / output circuit IO receives the high level of the output control signal DOC to be selectively brought into an operating state, and the main amplifier MA0 or MA1.
The read data output from the corresponding read amplifier is output to the external device via the data input / output terminals D0 to D7.

The timing generation circuit TG has a clock signal CLK and a clock enable signal CKE supplied from the outside, a chip selection signal CSB, a row address strobe signal RASB, and a column address strobe signal CA.
Based on the SB, the write enable signal WEB, and the function control signals DQM and DSF, the various internal control signals and output control signals are selectively formed and supplied to each section.

FIG. 2 is a block diagram of an embodiment of the column predecoder CPD included in the synchronous DRAM of FIG. 1, and FIGS. 3 to 5 are partial circuit diagrams of the embodiment. It is shown. 6 is a block diagram of an embodiment of the column decoder CD included in the synchronous DRAM of FIG. 1, and FIG. 7 is a unit column decoder UCD0 included in the column decoder CD of FIG.
The circuit diagram of one embodiment is shown. Further, FIG. 8 shows a signal waveform diagram of an embodiment of a portion relating to the column predecoder CPD and the column decoder CD, that is, the column selection circuit, of the synchronous DRAM of FIG. Based on these figures, the synchronous D of this embodiment is
The specific configurations and operations of the column predecoder CPD and the column decoder CD included in the RAM and the features thereof will be described. In the circuit diagram below, a MOSFE whose channel (back gate) is marked with an arrow
T is a P-channel type and is shown in distinction from an N-channel MOSFET without an arrow. Further, in FIG. 7, the description of the exemplified unit column decoder UCD0 will be made of the unit column decoders UCD0 to UCD63.

In FIG. 2, the column predecoder CPD
Is a YSE signal generation circuit YSEG for receiving bank selection signals BS0-BS1 and an internal control signal YSE, and three unit column predecoders UPD0 for receiving 3-bit internal address signals Y0-Y2, Y3-Y5 or Y6-Y8, respectively. , UPD3 and UPD6 and output signals U00 to U07, U30 of each unit column predecoder
.About.U37 or U60 to U67 respectively, four predecoder latches PL0, PL30 and PL31 and PL6 are provided. Of these, the predecoder latch PL0 is supplied with mask data MD0 to MD7 from the data input / output circuit IO, internal control signals YOE and BW from the timing generation circuit TG, and redundant from a column system redundancy switching circuit (not shown). Control signal Y
RB is supplied.

Predecoder latches PL30 and PL31
From the YSE signal generation circuit YSEG to the internal signal YSE.
0 and YSE1 are supplied respectively, and the predecoder latch PL6 is supplied with the internal control signal YOE from the timing generation circuit TG. Predecoder latch PL0, PL
The output signals of 30, PL31 and PL6 are the predecode signals YM0 to YM7, AY300 to AY37.
0, AY301 to AY371 and AY60 to AY6
7 is supplied to the column decoder CD.

The unit column predecoder UPD0 is not particularly limited, but as shown in FIG. 3, eight AND (each of which receives the internal address signals Y0 to Y2 or the inversion signals of the inverters V3 to V5 in a predetermined combination). AND) gates A1 to A8. Needless to say, the output signal U00 of the AND gate A1 is set to the high level when the inverted signals of the internal address signals Y0 to Y2 by the inverters V3 to V5 are both set to the high level, in other words, the internal address signals Y0 to Y2 are set to the low level. When selectively set to high level. The output signal U07 of the AND gate A8 is the internal address signal Y0.
To Y2 are both set to a high level, the output signals U01 of AND gates A2 to A7 are selectively set to a high level.
.About.U06 are selectively set to a high level when the internal address signals Y0 to Y2 supplied to the first to third input terminals or the inversion signals of the inverters V3 to V5 are set to a high level. .

The predecoder latch PL0 comprises eight unit predecoder latches UPL00 to UPL07, each of these unit predecoder latches being its first
AND gate A9 which receives the corresponding output signals U00 to U07 of the unit column predecoder UPD0 at its input terminals and commonly receives the redundancy control signal YRB at its second input terminals, and a mask corresponding to its first input terminals. It includes an AND gate AA which receives data MD0-MD7 and has its second input terminal commonly receiving internal control signal BW. The output signals of the AND gates A9 and AA are supplied to the first and second input terminals of the corresponding OR gate O1, respectively.

The output signal of the OR gate O1 is supplied to the corresponding inverter V8 via the corresponding clocked inverter C1 and, after being inverted by the corresponding inverter V9, becomes the predecode signals YM0 to YM7. The output terminal of the inverter V8 is coupled to the input terminal of the corresponding clocked inverter C2, and the output terminal of the clocked inverter C2 is connected to the output terminal of the corresponding clocked inverter C1, that is, the input terminals of the corresponding inverters V8 and V9. Commonly combined. An inversion signal of the internal control signal YOE by the inverter V6 is commonly supplied to the inversion control terminal of the clocked inverter C1 and the non-inversion control terminal of the clocked inverter C2 that form each unit predecoder latch, and the clocked inverter C1
The non-inversion control terminal of the above and the inversion control terminal of the clocked inverter C2 are commonly supplied with an inversion signal from the inverter V7, that is, a substantial internal control signal YOE.

The redundancy control signal YRB is normally set to the high level, and the memory array AR of the bank BNK0 or BNK1.
When redundancy repair of the complementary bit line is performed in either Y0 or ARY1, it is selectively set to low level. Further, as shown by the dotted line in FIG. 8, the internal control signal BW is selectively set to a high level at a predetermined timing when the synchronous DRAM is set to the block write mode, and the internal control signal YOE is set to the synchronous DRAM. When is selected in various operation modes including the block write mode, it is temporarily set to a high level at a predetermined timing and for a relatively short period. Further, the internal address signals Y0 to Y8 including Y0 to Y2 are the column addresses Ca to C input via the address input terminals A0 to A8.
c is obtained as a result of being taken into the column address buffer CB and the column address counter CC at the rising edge of the clock signal CLK, and the mask data M
D0 to MD7 are input via the data input / output terminals D0 to D7 when the synchronous DRAM is set to the block write mode.

From these points, first of all, Synchronous D
When the RAM is in the normal operation mode and the internal control signal BW is at low level, the banks BNK0 and BNK are
In either case, the redundancy repair of the complementary bit lines is not performed and the redundancy control signal YRB is at the high level, the decoder result of the internal address signals Y0 to Y2, that is, the output signals U00 to U of the unit column predecoder UPD0.
07 is transmitted to the clocked inverter C1 via the AND gates A9 and OR gates O1 of the unit predecoder latches UPL0 to UPL7 of the predecoder latch PL0. At this time, the clocked inverter C1 selectively receives the high level of the internal control signal YOE to be in the transmission state, and the output signal U0 of the unit column predecoder UPD0 transmitted through the AND gate A9 and the OR gate O1.
0 to U07 are respectively inverted to inverters V8 and V9
To communicate. Further, the clocked inverter C2 receives the low level of the internal control signal YOE and selectively enters the transmission state, forms a latch circuit together with the inverter V8, and is transmitted from the AND gate A9 and the OR gate O1 via the clocked inverter C1. Holds the inverted logic level of the output signals U00 to U07 of the unit column predecoder UPD0.

As a result, the output signals of the unit predecoder latches UPL00 to UPL07 of the predecoder latch PL0, that is, the predecode signals YM0 to YM7, are from the rising edge of the internal control signal YOE to the next rising edge, as illustrated in FIG. Y address signals AY0 to A
Y8, that is, 1-bit YMa corresponding to column addresses Ca to Cc given as internal address signals Y0 to Y8
.About.YMc are sequentially set to the high level.

When the synchronous DRAM is set to the block write mode and the internal control signal BW is set to the high level,
The output signal of the AND gate A1 is set to the high level on condition that the corresponding mask data MD0 to MD7 are at the high level, and the predecode signals YM0 to YM7 are independent of the output signals U00 to U07 of the unit column predecoder UPD0. In other words, lower r bits, that is, 3-bit Y address signals, that is, internal address signals Y0 to Y
It is forced to a high level in the form of invalidating 2. As a result, in the column decoder CD described later, 8 consecutive
The bit line selection signal of the bit becomes high level at the same time,
It is possible to simultaneously write the same data to eight consecutive addresses in the column direction. The predecode signals YM0 to YM7 correspond to the corresponding mask data MD0 to M.
When D7 is set to the low level, it is selectively kept at the low level, which enables the write mask for each column address in the block write mode.

The unit column predecoder UPD3 is not particularly limited, but as shown in FIG. 4, eight NANDs (each of which receives the internal address signals Y3 to Y5 or the inverted signals of the inverters VA to VC in a predetermined combination). NAND) gates G1 to G8. Needless to say, the output signal U30 of the NAND gate G1 is high when the inverted signals of the internal address signals Y3 to Y5 by the inverters VA to VC are both at the high level, in other words, when the internal address signals Y3 to Y5 are both at the low level. Selectively set to low level. The output signal U37 of the NAND gate G8 is the internal address signal Y.
When 3 to Y5 are both set to the high level, they are selectively set to the low level, and the output signals U3 of the NAND gates G2 to G7 are output.
1 to U36 are selectively set to low level when the internal address signals Y3 to Y5 supplied to the first to third input terminals or the inversion signals of the inverters VA to VC are set to high level. .

On the other hand, predecoder latches PL30 and P30
L31 is an eight unit predecoder latch UPL300
-UPL370 and UPL301-UPL371, respectively, and each of these unit predecoder latches has at its first input terminal an inverted signal of the corresponding output signal U30-U37 of the unit column predecoder UPD3 by the clocked inverter C3. The second input terminal thereof includes a NAND gate G9 commonly receiving the internal signal YSE0 or YSE1 and a latch circuit including an inverter VF and a clocked inverter C2. Of these, the internal signal YSE0 or YSE1 is commonly supplied to the inverting control terminal of the clocked inverter C3 and the non-inverting control terminal of the clocked inverter C4, and the non-inverting control terminal of the clocked inverter C3 and the clocked inverter C4 are commonly supplied. Inversion control terminals are commonly supplied with an inversion signal from the inverter VD or VE. The output signal of the NAND gate G9 is inverted by the corresponding inverter VG, and then the predecode signal AY300 to AY370 or AY301 to AY.
It is supplied to the column decoder CD as Y371.

As shown in FIG. 8, the internal control signal YSE is temporarily set at a predetermined timing and for a relatively long period when the synchronous DRAM is selected in various operation modes including the block write mode. High level. Further, the internal signal YSE0 is the bank BNK0.
Is specified and the bank selection signal BS0 is set to the high level, the internal control signal YSE is set to the high level, and the internal signal YSE1 is set to the bank BNK1 and the bank selection signal BS1 is set to the high level. It is set to a high level in synchronization with the internal control signal YSE.

From these facts, first, the clocked inverter C3 receives the low level of the internal signal YSE0 or YSE1 and selectively enters the transmission state, and the corresponding output signals U30 to U30 of the unit column predecoder UPD3.
Each U37 is inverted and transmitted to the corresponding inverter VF and NAND gate G9. Further, the clocked inverter C4 receives the high level of the internal signal YSE0 or YSE1 to be selectively in the transmission state, constitutes a latch circuit together with the inverter VF, and is transmitted through the clocked inverter C3. The logic level immediately before the inversion of the output signals U30 to U37 of the decoder UPD3 is held. Furthermore, Nand Gate G9
Receives the high level of the internal signal YSE0 or YSE1 and selectively enters the transmission state, and the clocked inverter C3
Output signals U30 to U of the unit column predecoder UPD3 that are transmitted via the latch circuit or are held by the latch circuit including the clocked inverter C4 and the inverter VF.
The inverted logic level of 37 is further inverted and transmitted to the corresponding inverter VG.

As a result, the unit predecoder latch UP
L300 to UPL370 and UPL301 to UPL
371 output signal, that is, predecode signal AY300-
As illustrated in FIG. 8, the AY370 and the AY301 to AY371 are arranged such that the Y address signals AY0 to AY8, that is, the column addresses Ca to which the internal address signals Y0 to Y8 are given, while the internal signal YSE0 or YSE1 is at a high level. 1-bit AY3a0 corresponding to Cc,
AY3b1 and AY3c0 are sequentially and alternately set to the high level only for a predetermined period.

Similarly, the unit column predecoder UPD6
Is not particularly limited, but as shown in FIG. 5, internal address signals Y6 to Y8 or their inverters VH to VH.
Eight NAND gates GA to GH are provided, each of which receives an inversion signal by VJ in a predetermined combination. Needless to say, the output signal U60 of the NAND gate GA is high when the inverted signals of the internal address signals Y6 to Y8 by the inverters VH to VJ are both at the high level, in other words, when the internal address signals Y6 to Y8 are both at the low level. Selectively set to low level. The output signal U67 of the NAND gate GH is the internal address signal Y6 ...
When Y8 is both set to the high level, it is selectively set to the low level, and the output signals U61 to U66 of the other NAND gates GB to GG are the internal address signals Y6 to Y8 supplied to the first to third input terminals thereof. When the inversion signals of the inverters VH to VJ are both set to the high level, they are selectively set to the low level.

The predecoder latch PL60 is provided with eight unit predecoder latches UPL60 to UPL67, and each of these unit predecoder latches has its input terminal corresponding to the output signal U60 to U67 of the unit column predecoder UPD6. A clocked inverter C5 that receives the clock signal and a latch circuit including an inverter VM and a clocked inverter C6. Among these, the inversion control terminal of the clocked inverter C5 and the non-inversion control terminal of the clocked inverter C6 are commonly supplied with the inversion signal of the internal control signal YOE by the inverter VK, and the non-inversion control terminal of the clocked inverter C5. In addition, the inversion control terminal of the clocked inverter C6 is commonly supplied with the inversion signal by the inverter VL, that is, the substantial internal control signal YOE. The output signals of the clocked inverters C5 and C6 are supplied to the column decoder CD as the predecode signals AY60 to AY67 after passing through the corresponding two inverters VN and VO.

From the above, the clocked inverter C5 forming the unit predecoder latches UPL60 to UPL67 receives the high level of the internal control signal YOE and is selectively brought into the transmission state, and the unit column predecoder UP is provided.
The corresponding output signals U60 to U67 of D6 are respectively inverted and transmitted to the inverters VM and VN. Further, the clocked inverter C6 receives the low level of the internal control signal YOE and selectively enters the transmission state, and constitutes a latch circuit together with the inverter VM, and the clocked inverter C6.
Unit column predecoder UPD6 transmitted via
Holds the logic level immediately before the inverted output signals U60 to U67.

As a result, the output signals of the unit predecoder latches UPL60 to UPL67 of the predecoder latch PL6, that is, the predecode signals AY60 to AY67 are from the rising edge of the internal control signal YOE to the next rising edge, as illustrated in FIG. Y address signal AY0
.About.AY8, that is, one bit corresponding to the column addresses Ca to Cc given as the internal address signals Y0 to Y8, that is, AY6a to AY6c are sequentially and alternately set to the high level.

As shown in FIG. 6, the column decoder CD includes 64 unit column decoders UCD provided corresponding to the q bits of the bit line selection signals YS00 to YS5110 and YS01 to YS5111, that is, 8 bits.
0 to UCD63 are provided. These unit column decoders include predecode signals YM0 to YM7, AY300 to AY370 and AY3 from the column predecoder CPD.
01-AY371 and AY60-AY67 are commonly supplied.

In this embodiment, the synchronous DRA
As described above, M has a block write mode in which the same data is simultaneously written to p consecutive addresses in the column direction, that is, 8 addresses, and the column decoder CD has consecutive 8 bit bits in this block write mode. Line selection signals YS00 to YS80 to YS5040 to YS
S5110 or YS01 to YS81 to YS50
41 to YS5111 are simultaneously set to an effective level, that is, a high level. Therefore, in this embodiment, q units, that is, 8 addresses are sequentially assigned to the unit column decoders UCD0 to UCD63, and q bits, that is, 8 bits are selected every p bits, that is, every 8 bits. Signals YS00, YS80 to YS560 to YS45
50, YS4630 to YS5110 or YS01,
YS81 to YS561 to YS4551 and YS463
1 to YS5111 are sequentially assigned.

The unit column decoders UCD0 to UCD63 of the column decoder CD are the unit column decoder U of FIG.
As represented by CD0, eight sets of P-channel MOSFET P1 and N-channel MOSFET N1 provided in series-parallel form between the power supply voltage of the circuit and the internal node n1 for the memory array ARY0, that is, the bank BNK0.
And 8 sets of P-channel MOSFETs P2 and N provided in series parallel between the power supply voltage of the circuit and the internal node n1 for the memory array ARY1, that is, the bank BNK1.
Two P-channel MOSFETs P3 and P4 each including a channel MOSFET N2 and provided in parallel between the power supply voltage of the circuit and the internal node n1.
And two N-channel MOSFETs N3 and N provided in series between the internal node n1 and the ground potential of the circuit.
4 is included.

Among them, corresponding predecode signals AY300 to AY are applied to the commonly connected gates of the MOSFETs P1 and N1 of each pair corresponding to the memory array ARY0.
370 are sequentially supplied, and the potentials at the commonly coupled drains thereof are inverted by the corresponding inverter VP, and then bit line selection signals YS00, YS80 to YS.
It becomes 560. Similarly, the common-coupled gates of the MOSFETs P2 and N2 of each pair corresponding to the memory array ARY1 have corresponding predecode signals AY301 to AY.
371 are sequentially supplied, and the potentials at the commonly coupled drains thereof are inverted by the corresponding inverter VQ, and then the bit line selection signals YS01, YS81 to YS.
561. On the other hand, the predecode signals YM0 to YM are applied to the commonly connected gates of the MOSFETs P3 and N3.
The corresponding bit YM0 of 7 is supplied to the MOSFET
Corresponding bits AY60 of the predecode signals AY60 to AY67 and the like are supplied to the commonly connected gates of P4 and N4.

From these points, for example, the memory array A
Bit line selection signals YS00, YS80 corresponding to RY0
To YS560 are predecode signals YM0 and AY.
When 60 is set to the high level and the corresponding predecode signals AY300 to AY370 are set to the high level, they are selectively set to the high level, and the memory array ARY
The bit line selection signals YS01, YS81 to YS561 corresponding to 1 are predecode signals YM0 and AY60.
Is set to a high level and the corresponding predecode signal AY
When 301 to AY371 are set to the high level, they are selectively set to the high level.

As described above, the synchronous DRA
When M is set to the block write mode, the predecode signals YM0 to YM7 correspond to the corresponding mask data MD0 to MD0.
MD7 is simultaneously set to the high level on condition that MD7 is not set to the low level. Therefore, the unit column decoder UCD
Common predecode signal AY60 among 0 to UCD63
~ AY67 receive high level predecode signal AY300 to AY370 or AY301
~ 8-bit bit line selection signal Y corresponding to AY371
S00 to YS80 to YS5040 to YS5110 or YS01 to YS81 to YS5041 to YS5
111 becomes high level at the same time, and the same data can be simultaneously written to a total of 64 memory cells corresponding to 8 addresses continuous in the column direction.

As described above, the synchronous DRAM of this embodiment includes the column selection circuit including the column predecoder CPD and the column decoder CD. The column predecoder CPD forming the column selection circuit includes three unit column predecoders UPD0, UPD3 and UPD6, and four predecoder latches PL0, PL3.
0, PL31 and PL6, and one YSE signal generation circuit YSEG, and the column decoder CD includes 64
The unit column decoders UCD0 to UCD63 are included.
Among them, a predetermined part of the column predecoder CPD, that is, the unit column predecoders UPD0 to UPD6, the predecoder latches PL0 and PL6, and the YSE signal generation circuit YSEG are provided in a pair of banks BNK0 and BNK.
The predecoder latches PL30 and PL31 are shared by 1 and are assigned to each bank. Further, a predetermined part of the column decoder CD, that is, the MOSFETs P3 and P4 and N3 and N4 of the unit column decoders UCD0 to UCD63 are shared by the banks BNK0 and BNK1, and the MOSFETs P1 and N1 and P2 and N2 are assigned for each bank.

The synchronous DRAM of this embodiment has a block write mode in which the same data is simultaneously written to eight consecutive addresses in the column direction. In this block write mode, the lower 3 bits of the internal address signal Y0 are written. ~ Y2 is made invalid and the mask data M
It needs to be masked for each address according to D0 to MD7. Further, the column selection operation of the synchronous DRAM needs to be selectively performed for each bank, and further, in the block write mode, consecutive 8-bit bit line selection signals need to be simultaneously set to the high level.

As is apparent from the above description, in this embodiment, the processing corresponding to the block write mode is provided corresponding to the internal address signals Y0 to Y2 of r bits, that is, 3 bits, and is a unit shared by both banks. The column predecoder UPD0 and the predecoder latch PL0 are efficiently realized, and the bank selection processing is performed independently by the predecoder latches PL30 and PL31 corresponding to the s-bit, that is, 3-bit internal address signals Y3 to Y5. It is realized by being provided.
As a result, in this embodiment, the address suitable for the block write mode can be assigned to the column decoder and the layout required area of the column decoder and the column predecoder can be reduced by the partial sharing. . As a result, the chip size of the synchronous DRAM having the block write mode can be reduced and its cost can be reduced.

The operational effects obtained from the above embodiments are as follows. That is, (1) In a synchronous DRAM or the like having a plurality of banks and having the block write mode for simultaneously writing the same data to p consecutive addresses in the column direction, a predetermined part of the column decoder and the column predecoder is In addition to being shared by a plurality of banks, unit column decoders of column decoders are provided corresponding to q-bit bit line selection signals, and q units of q are provided to each unit column decoder.
By sequentially allocating each column address, it is possible to achieve an effect that the layout required area of the column decoder and the column predecoder can be reduced while realizing the address allocation suitable for the block write mode to the column decoder.

(2) According to the above item (1), a synchronous DR having a plurality of banks and a block write mode
There is an effect that the chip size of AM or the like can be correspondingly reduced and the cost can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the memory arrays ARY0 and ARY1 of the synchronous DRAM can be divided into a plurality of memory mats including their direct peripheral circuits. Further, the block write mode of the synchronous DRAM can be masked in the IO direction, that is, for each bit of the input data, and a mask data register therefor can be provided.
The synchronous DRAM can have an arbitrary number of banks, and its storage capacity can also be set arbitrarily. Further, the synchronous DRAM can have any bit configuration such as x4 bit or x16 bit, and its block configuration, address configuration, combination of activation control signals, and the like can adopt various embodiments.

In FIG. 2, the column predecoder CPD
The block configuration and address allocation for each unit column predecoder are not restricted by this embodiment.
3 to 5, each unit column predecoder,
The specific configurations of the predecoder latch and the unit predecoder latch may be various embodiments as long as the logical conditions are maintained. In FIG. 6, various block configurations of the column decoder CD can be considered. In FIG. 7, the concrete configuration of the unit column decoders UCD0 to UCD63 is not restricted by this embodiment, and the same applies to the polarity of the power supply voltage, the conductivity type of the MOSFET, and the like. In FIG. 8, the name, effective level, and time relationship of each signal are not limited to those in this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronous DRAM which is the field of use as the background, has been described.
The invention is not limited to this, and can be applied to, for example, an image memory having a plurality of banks. The present invention can be widely applied to a semiconductor memory device having at least a plurality of banks and a system including such a semiconductor memory device.

[0062]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a synchronous DRAM or the like having a plurality of banks and having a block write mode for simultaneously writing the same data to p consecutive addresses in the column direction, a predetermined part of a column decoder and a column predecoder is provided in a plurality of banks. In addition, the unit decoders of the column decoders are provided corresponding to the q-bit bit line selection signals, and q column addresses are sequentially assigned to these unit column decoders every q p. On the other hand, the address allocation suitable for the block write mode can be realized, and the partial area sharing can reduce the layout required area of the column decoder and the column predecoder. As a result, the chip size of a synchronous DRAM or the like having a plurality of banks and having a block write mode can be reduced and the cost thereof can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

2 is a block diagram showing an embodiment of a column predecoder included in the synchronous DRAM of FIG.

FIG. 3 is a first partial circuit diagram showing an embodiment of the column predecoder of FIG.

FIG. 4 is a second partial circuit diagram showing an embodiment of the column predecoder of FIG.

5 is a third partial circuit diagram showing an embodiment of the column predecoder of FIG. 2. FIG.

6 is a block diagram showing an embodiment of a column decoder included in the synchronous DRAM of FIG.

7 is a circuit diagram showing an embodiment of a unit column decoder included in the column decoder of FIG.

8 is a signal waveform diagram showing an embodiment of the synchronous DRAM of FIG.

FIG. 9 is a block diagram showing an example of a synchronous DRAM developed by the inventors of the present application prior to the present invention.

[Explanation of symbols]

BNK0 to BNK1 ... Banks, ARY0 to ARY1 ...
... Memory array, RD0 to RD1 ... Row decoder, B
S ... Bank selection circuit, RB ... Row address buffer, SA0-SA1 ... Sense amplifier, CD00 * -C
D70 *, CD01 * to CD71 * ... Complementary common data lines, MA0 to MA1 ... main amplifier, CD ... column decoder, CPD ... column predecoder, CC ... column address counter, CB ... column address buffer, IO ... Data input / output circuit, DR ... Data register, TG ... Timing generation circuit. BS0 to BS1 ...
Bank selection signal, Y0 to Y8 ... Internal address signal, M
D0 to MD7 ... Mask data, YSEG ... YSE signal generation circuit, UPD0, UPD3, UPD6 ... Unit column predecoder, PL0, PL30 to PL31, PL
6 ... Predecoder latch, YM0 to YM7, AY30
0-AY370, AY301-AY371, AY60-
AY67 ... Predecode signal. UPL00 to UPL0
7, UPL300 to UPL370, UPL301 to UP
L371, UPL60 to UPL67 ... Unit predecoder latch UCD0 to UCD63 ... Unit column decoder, YS0
0 to YS5110, YS01 to YS5111 ... Bit line selection signals. A1-AA ... AND gate,
O1 ... OR gate, G1-GH ... NAND gate, C1-C6 ... Clocked inverter, V1-VQ ... Inverter, N1-N4 ... N-channel MOSFET, P1-P4 ... P channel M
OSFET. CD0-CD1 ... Column decoder, CP
D0-CPD1 ... Column predecoder, AY000-
AY070, AY001 to AY071, AY600 to A
Y670, AY601 to AY671 ... Predecode signal.

Claims (4)

[Claims] 1. A plurality of banks capable of independently selecting a word line are provided, and a predetermined part of a column predecoder and a column decoder for selecting a bit line is shared by the plurality of banks. And semiconductor memory device. 2. The semiconductor memory device has a block write mode in which the same data can be simultaneously written to p addresses continuous in the column direction,
2. The semiconductor memory according to claim 1, wherein the column decoder includes a plurality of unit column decoders provided corresponding to q bits of a bit line selection signal and sequentially assigned q p addresses. apparatus. 3. The write in the block write mode is performed by invalidating the Y address signal of the lower r bits, and can be selectively masked at each of the p addresses, and the column predecoder. 3. The semiconductor memory device according to claim 2, wherein the shared portion includes at least a portion corresponding to the Y address signal of the lower r bits. 4. The semiconductor memory device is a synchronous DRAM having a pair of banks, and the column predecoder has a higher s-bit Y excluding the lower r bits.
4. The semiconductor device according to claim 3, further comprising a pair of predecoder latches which are provided corresponding to the address signals and are selectively brought into an operating state when a corresponding bank selection signal is set to a valid level. Storage device.