JP3736779B2 - Dynamic RAM - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, for example, a dynamic RAM (random access memory) having a redundant word line and having a refresh function, and a technique particularly effective when used for improving the product yield.
[0002]
[Prior art]
There is a dynamic RAM including a memory array in which dynamic memory cells including an information storage capacitor and an address selection MOSFET are arranged in a lattice as a basic component. In these dynamic RAMs, the charge stored in the information storage capacitor of the memory cell in accordance with the logical value of the stored data leaks to the semiconductor substrate side with time and disappears. For this reason, a refresh operation is required in which the stored data is read and rewritten in units of word lines within the time during which the amount of charge leakage does not reach a predetermined value, that is, within the information retention time of the memory cell. The dynamic RAM has a so-called self-refresh mode and a built-in self-refresh mode that autonomously performs a refresh operation for all the word lines of the memory array while stepping a built-in address counter at a predetermined cycle as means for efficiently executing a refresh operation. A CBR (CAS before RAS) refresh mode is prepared which can be executed with the initiative of the access device side.
[0003]
On the other hand, a predetermined number of redundant word lines and redundant bit lines are provided in the memory array of the dynamic RAM, and these redundant word lines or redundant bit lines are selectively replaced with word lines or bit lines in which an abnormality is detected by product inspection. Thus, there is a so-called defect relief method that can increase the product yield of the dynamic RAM.
[0004]
[Problems to be solved by the invention]
Prior to the present invention, the inventors of the present application noticed the following problems when trying to develop a large-capacity next-generation dynamic RAM having a refresh mode and a defect relieving function. In other words, in a conventional dynamic RAM adopting the defect relief method, when a memory cell whose information retention time is outside the specified value is detected in the memory array, defect relief is performed by replacing the corresponding word line with a redundant word line. Is called. Further, in recent years, as dynamic RAM has been miniaturized and highly integrated, the information retention time of memory cells tends to be shortened by increasing the concentration of the substrate. It is becoming a relatively large target for defect relief by redundant word lines. However, when the information retention characteristic is deteriorated in the replaced redundant word line itself, the dynamic RAM becomes defective even if it is slightly deviated from the specified value. As a result, the relief efficiency of the dynamic RAM is lowered, and the product yield is lowered.
[0005]
An object of the present invention is to increase the repair efficiency by a redundant word line such as a dynamic RAM having a refresh mode and having a defect repair function by a redundant word line, and to increase the product yield of the dynamic RAM or the like.
[0006]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like having a refresh mode such as a self-refresh mode and a CBR refresh mode and having a defect relief function using redundant word lines, for example, a refresh address counter for sequentially designating word lines to be refreshed is used. A bit for a refresh switching control signal is provided as an upper bit. For example, when the refresh switching control signal is at a low level, only a refresh operation for a redundant word line is executed, and when it is at a high level, a refresh for a normal word line and a redundant word line is performed. By executing the operation, the refresh operation relating to the redundant word line is executed in a cycle of, for example, a half of the refresh operation relating to the normal word line.
[0008]
According to the above-described means, even when a certain degree of deterioration is observed in the information retention characteristics of the memory cells coupled to the redundant word line, only the redundant word line refresh operation is executed at twice the frequency to compensate for the deterioration. be able to. As a result, the repair efficiency by the redundant word line such as the dynamic RAM having the refresh mode and the defect repair function can be increased, and the product yield can be increased.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a dynamic RAM (semiconductor memory device) to which the present invention is applied. The outline of the configuration and operation of the dynamic RAM of this embodiment will be described first with reference to FIG. The circuit elements constituting each block in FIG. 1 are not particularly limited, but are known MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are collectively referred to as insulated gate field effect transistors). It is formed on the surface of a single semiconductor substrate such as single crystal silicon by an integrated circuit manufacturing technique.
[0010]
In FIG. 1, the dynamic RAM of this embodiment has a memory array MARY and a redundant memory array RARY, which are arranged so as to occupy most of the semiconductor substrate surface, as its basic components. Among these, as will be described later, the memory array MARY includes m + 1 word lines (normal word lines) arranged in parallel in the vertical direction in the figure and n + 1 sets of complementary bits arranged in parallel in the horizontal direction. Including lines. The redundant memory array RARY includes one redundant word line arranged in the vertical direction, and shares n + 1 sets of complementary bit lines with the memory array MARY. At the intersections of these word lines and redundant word lines and complementary bit lines, there are (m + 1) × (n + 1) dynamic memory cells or (n + 1) redundant memory cells each consisting of an information storage capacitor and an address selection MOSFET. The grid is arranged.
[0011]
The word lines constituting the memory array MARY are coupled to the X address decoder XD at the lower side thereof, and alternatively set to a predetermined selection level. Redundant word lines constituting the redundant memory array RARY are coupled to the redundant X address decoder RXD below the redundant word lines and are selectively set to a selection level under a predetermined condition. The X address decoder XD is supplied with i + 1-bit internal address signals X0 to Xi from the X address buffer XB, and also supplied with a redundancy enable signal RE from a refresh control circuit RFC, which will be described later, and driven from the timing generation circuit TG to the X decoder. A signal XE is supplied. The redundant X address decoder RXD is supplied with the redundant enable signal RE from the refresh control circuit RFC and the X decoder drive signal XE from the timing generation circuit TG.
[0012]
On the other hand, to the X address buffer XB, i + 1-bit X address signals AX0 to AXi are supplied from an external access device via address input terminals A0 to Ai in a time-sharing manner. Address signals R0 to Ri are supplied, and internal control signals RF and XL are supplied from the timing generation circuit TG. The internal control signal RF is set to a low level when the dynamic RAM is selected in the normal write or read mode, and selectively at a predetermined timing when the dynamic RAM is selected in the refresh mode including the self-refresh mode. High level. In addition, this self-refresh mode has a row address strobe signal RASB as an activation control signal (here, for a so-called inversion signal that is selectively set to a low level when it is enabled, B is added at the end of its name. The same applies to the following, and after the signal is set to the low level after the column address strobe signal CASB, it is selectively designated by continuing the low level over a predetermined time.
[0013]
The X address buffer XB is an X address signal supplied from an external access device via the address input terminals A0 to Ai when the dynamic RAM is selected in the normal operation mode and the internal control signal RF is at a low level. AX0 to AXi are taken in according to the internal control signal XL and held. When the dynamic RAM is selected in the refresh mode and the internal control signal RF is set to the high level, the refresh address signals R0 to Ri supplied from the refresh control circuit RFC are fetched and held according to the internal control signal XL. The X address buffer XB forms internal address signals X0 to Xi composed of non-inverted and inverted signals based on these X address signals or refresh address signals, and supplies them to the X address decoder XD and the refresh control circuit RFC. .
[0014]
The X address decoder XD is selectively activated in response to the high level of the X decoder drive signal XE, decodes the internal address signals X0 to Xi supplied from the X address buffer XB, and corresponds to the memory array MARY. A word line is alternatively set to a selection level. The redundant X address decoder RXD is selectively activated in response to the high level of the redundancy enable signal RE, and sets the redundant word line of the redundant memory array RARY to the high level selected state. Note that when the redundancy enable signal RE is set to the high level and the redundancy word line is set to the selection level, the normal word line selection operation by the X address decoder XD is prohibited.
[0015]
The refresh control circuit RFC is supplied with the internal address signals X0 to Xi from the X address buffer XB and the internal control signal SRF from the timing generation circuit TG. The output signal, that is, the refresh address signal R0 to Ri is supplied to the X address buffer XB as described above, and the redundancy enable signal RE is supplied to the redundancy X address decoder RXD and the X address decoder XD. Another output signal of the refresh control circuit RFC, that is, the internal row address strobe signal IRAS is supplied to the timing generation circuit TG. The internal control signal SRF is selectively set to a high level at a predetermined timing when the dynamic RAM is set to the self-refresh mode.
[0016]
In this embodiment, as will be described later, the refresh control circuit RFC includes a refresh oscillation circuit that receives an internal control signal SRF, a frequency divider that receives an internal clock signal that is an output signal of the refresh oscillation circuit, and an output signal of the frequency divider A refresh address counter for receiving a refresh clock signal, and a redundant address comparison circuit for receiving internal address signals X0 to Xi and refresh address signals R0 to Ri as output signals of the refresh address counter. Among these, the refresh oscillation circuit is selectively activated when the dynamic RAM is set to the self-refresh mode and the internal control signal SRF is set to the high level, and generates an internal clock signal having a predetermined cycle. The frequency divider circuit divides the internal clock signal output from the refresh oscillation circuit to generate a refresh clock signal having a predetermined period. Further, the refresh address counter is an i + 2 bit binary counter, and performs a stepping operation according to the refresh clock signal to generate refresh address signals R0 to Ri + 1. Among them, the refresh address signals R0 to Ri of lower i + 1 bits are supplied to the X address buffer XB, and the refresh address signal Ri + 1 of the most significant bit (not shown) is used to generate an internal row address strobe signal IRAS described later.
[0017]
On the other hand, the redundant address comparator circuit detects the address of the defective word line of the memory array MARY, that is, the defective address, in which an abnormality is detected in any of the n + 1 memory cells coupled to the redundant address line of the redundant memory array RARY. The defective address and the internal address signals X0 to Xi output from the X address buffer XB are compared and collated for each bit, and when both the addresses match, the redundant enable signal RE, which is the output signal, is set to a predetermined value. Select high level selectively at timing. As described above, the redundancy enable signal RE is supplied to the redundancy X address decoder RXD and the X address decoder XD.
[0018]
The refresh control circuit RFC further includes a refresh clock signal output from the frequency dividing circuit, an internal address signal Ri + 1 of the most significant bit output from the refresh address counter, and a redundancy enable signal RE output from the redundancy address comparison circuit. And a logic circuit for selectively generating internal row address strobe signal IRAS. The internal row address strobe signal IRAS is supplied to the timing generation circuit TG and is used for selectively generating various internal control signals necessary for the refresh operation. The specific configuration and operation of the refresh control circuit RFC will be described later in detail.
[0019]
Next, the complementary bit lines constituting the memory array MARY and the redundant memory array RARY are coupled to the sense amplifier SA on the left side, and through this, eight sets of complementary common data lines CD0 * to CD7 * ( Here, for example, complementary signals such as the complementary common data line CD0 * composed of the non-inverted common data line CD0T and the inverted common data line CD0B are represented by adding * to the end of the name. A non-inverted signal or the like that is selectively set to a high level when connected is sometimes connected with a T at the end of its name. The sense amplifier SA is supplied with a bit line selection signal of a predetermined bit (not shown) from the Y address decoder YD, and is supplied with an internal control signal PA and an internal control signal PC (not shown) from the timing generation circuit TG. The Y address decoder YD is supplied with i + 1-bit internal address signals Y0 to Yi from the Y address buffer YB, and is supplied with the Y decoder drive signal YE from the timing generation circuit TG. Further, the Y address buffer YB is supplied with the Y address signals AY0 to AYi from the external access device via the address input terminals A0 to Ai in a time-division manner, and the internal control signal YL is supplied from the timing generation circuit TG. Is done.
[0020]
The Y address buffer YB fetches and holds Y address signals AY0 to AYi supplied via the address input terminals A0 to Ai according to the internal control signal YL, and also uses the internal address signals Y0 to Y0 based on these Y address signals. Yi is formed and supplied to the Y address decoder YD. The Y address decoder YD is selectively activated in response to the high level of the Y decoder driving signal YE, decodes the internal address signals Y0 to Yi, and corresponds to the bit corresponding to the bit line selection signal for the sense amplifier SA. Is alternatively set to a high level selection level.
[0021]
The sense amplifier SA includes n + 1 unit circuits provided corresponding to the respective complementary bit lines of the memory array MARY and the redundant memory array RARY. Each of these unit circuits includes a pair of CMOS (complementary MOS) inverters. Each includes a unit amplifier circuit that is cross-coupled, a bit line precharge circuit in which three N-channel type precharge MOSFETs are connected in series and parallel, and a pair of N-channel type switch MOSFETs. Among these, the unit amplifier circuit of each unit circuit is selectively activated all at once when the dynamic RAM is selected and the internal control signal PA is set to the high level, and the memory array MARY or redundant memory array is selected. The minute read signals output from the n + 1 memory cells coupled to the selected word line of RARY via the corresponding complementary bit lines are respectively amplified to obtain high-level or low-level binary read signals.
[0022]
As will be described later, the binary read signal established for each complementary bit line of the memory array MARY and the redundant memory array is transferred from the complementary common data lines CD0 * to CD7 * when the dynamic RAM is set to the read mode. The data is output to an external access device through the input / output circuit IO and the data input / output terminals D0 to D7, and is rewritten to n + 1 memory cells coupled to the selected word line of the memory array MARY or the redundant memory array RARY. When the dynamic RAM is set to a refresh mode such as a self-refresh mode, only rewriting is performed without being output to an external access device.
[0023]
On the other hand, the precharge MOSFETs constituting the bit line precharge circuit of each unit circuit are selectively turned on simultaneously in response to the high level of the internal control signal PC, and correspond to the memory array MARY and the redundant memory array RARY. The non-inverted and inverted signal lines of the complementary bit lines are precharged to a predetermined intermediate potential. In addition, the switch MOSFET pairs of each unit circuit are selectively turned on in groups of eight in response to the high level of the corresponding bit of the bit line selection signal, and the eight complementary pairs of the memory array MARY and the redundant memory array RARY. The bit line and the complementary common data lines CD0 * to CD7 * are selectively connected.
[0024]
Complementary common data lines CD0 * to CD7 * are coupled to corresponding unit circuits of data input / output circuit IO. The data input / output circuit IO is supplied with internal control signals WP and OC (not shown) from the timing generation circuit TG.
[0025]
The data input / output circuit IO includes eight unit circuits provided corresponding to the complementary common data lines CD0 * to CD7 *. Each of these unit circuits includes a write amplifier, a main amplifier, a data input buffer, and a data output. Contains a buffer. Among these, the output terminal of the write amplifier and the input terminal of the main amplifier constituting each unit circuit are respectively coupled to the corresponding complementary common data lines CD0 * to CD7 *. The input terminal of the write amplifier of each unit circuit is coupled to the output terminal of the corresponding data input buffer, and the output terminal of the main amplifier of each unit circuit is coupled to the input terminal of the corresponding data output buffer. The input terminal of the data input buffer and the output terminal of the data output buffer constituting each unit circuit are commonly coupled to the corresponding data input / output terminals D0 to D7. The internal control signal WP is commonly supplied to the write amplifiers of the unit circuits, and the internal control signal OC is commonly supplied to the data output buffers of the unit circuits.
[0026]
The data input buffer of each unit circuit of the data input / output circuit IO is an 8-bit supplied from the external access device via the data input / output terminals D0 to D7 when the dynamic RAM is selected in the write mode. Write data is captured and held, and transmitted to the corresponding write amplifier. At this time, the write amplifiers of each unit circuit are selectively and simultaneously activated in response to the high level of the internal control signal WP, and write data transmitted from the corresponding data input buffer is set as a predetermined complementary write signal. After that, data is written to eight selected memory cells of the memory array MARY or the redundant memory array RARY via the complementary common data lines CD0 * to CD7 * and the sense amplifier SA.
[0027]
On the other hand, when the dynamic RAM is selected in the read mode, the main amplifier of each unit circuit of the data input / output circuit IO is a sense amplifier from the eight memory cells selected in the memory array MARY or the redundant memory array RARY. The binary read signal output via the SA and complementary common data lines CD0 * to CD7 * is further amplified and transmitted to the corresponding data output buffer. At this time, the data output buffers of the respective unit circuits are simultaneously operated in response to the high level of the internal control signal OC, and further amplify the read data transmitted from the main amplifiers, so that the data input / output terminals D0 to D7. To the external access device.
[0028]
The timing generation circuit TG includes a row address strobe signal RASB, a column address strobe signal CASB and a write enable signal WEB supplied as activation control signals from an external access device, and an internal row address strobe signal IRAS supplied from the refresh control circuit RFC. Based on the above, the various internal control signals are selectively formed and supplied to the respective units. The specific configuration of the relevant part of the timing generation circuit TG will be described later in detail.
[0029]
FIG. 2 shows refresh related circuits included in the dynamic RAM of FIG. 1, that is, memory array MARY, redundant memory array RARY, X address buffer XB, refresh control circuit RFC, X address decoder XD, redundant X address decoder RXD, sense A connection diagram of the first embodiment of the amplifier SA and the timing generation circuit TG is shown. FIG. 3 shows a signal waveform diagram of one embodiment in the self-refresh mode of the refresh related circuit of FIG. Based on these figures, the specific configuration, connection form, operation and characteristics of the refresh-related circuit included in the dynamic RAM of this embodiment will be described. In the following block diagram, specific block configurations and circuit configurations of the relevant portions of the memory array MARY, the redundant memory array RARY, the refresh control circuit RFC, and the timing generation circuit TG are shown. In the following signal waveform diagram, the redundant word line WR of the redundant memory array RARY is replaced with the word line W2 of the memory array MARY, and this is relieved.
[0030]
In FIG. 2, the memory array MARY includes 2 j powers arranged in parallel to the vertical direction in the figure, that is, 2 + 1 powers, that is, m + 1 word lines W0 to Wm (normal word lines) and a horizontal direction. N + 1 sets of complementary bit lines B0 * to Bn * arranged in parallel with each other. At the intersections of these word lines and complementary bit lines, (m + 1) × (n + 1) dynamic memory cells MC composed of information storage capacitors and address selection MOSFETs are arranged in a lattice pattern.
[0031]
On the other hand, the redundant memory array RARY includes one redundant word line WR arranged in parallel in the vertical direction, and the n + 1 sets of complementary bit lines B0 * to Bn * arranged in an extended manner are connected to the memory array MARY. Share with. At the intersection of these redundant word lines and complementary bit lines, n + 1 redundant memory cells RC, which are also composed of information storage capacitors and address selection MOSFETs, are arranged.
[0032]
Word lines W0 to Wm constituting memory array MARY are coupled to X address decoder XD below, and redundant word lines WR constituting redundant memory array RARY are coupled to redundant X address decoder RXD below. The X address decoder XD is supplied with i + 1 bits of internal address signals X0 to Xi from the X address buffer XB. The X address decoder XD and the redundant X address decoder RXD are commonly supplied with the X decoder drive signal XE from the X decoder drive signal generation circuit XEG of the timing generation circuit TG, and from the redundant address comparison circuit RADC of the refresh control circuit RFC. The redundancy enable signal RE is supplied in common. The X address buffer XB is supplied with X address signals AX0 to AXi of i + 1 bits from an external access device via address input terminals A0 to Ai. Further, refresh address signals R0 to Ri are supplied from the refresh address counter RCTR of the refresh control circuit RFC, and internal control signals RF and XL are supplied from the timing generation circuit TG.
[0033]
As described above, the X address buffer XB is supplied from an external access device via the address input terminals A0 to Ai when the dynamic RAM is in a normal operation mode and the internal control signal RF is at a low level. Address signals AX0 to AXi are fetched and held in accordance with internal control signal XL. When the dynamic RAM is set to the refresh mode and the internal control signal RF is set to the high level, the refresh address signals R0 to Ri supplied from the refresh control circuit RFC are fetched and held according to the internal control signal XL. Then, based on these X address signals or refresh address signals, internal address signals X0 to Xi are formed and supplied to the X address decoder XD.
[0034]
X address decoder XD selectively operates in response to the high level of X decoder drive signal XE, decodes internal address signals X0 to Xi, and selectively selects corresponding word lines W0 to Wm of memory array MARY. To a high level selection state. The redundant X address decoder RXD is selectively activated in response to the high level of the redundancy enable signal RE, and selectively selects the redundant word line WR of the redundant memory array RARY according to the X decoder drive signal XE. And When the redundancy enable signal RE is set to the high level, the normal word line selection operation by the X address decoder XD is prohibited.
[0035]
Next, the timing generation circuit TG includes input buffers RB and CB, a mode determination circuit MOD, an X decoder drive signal generation circuit XEG, and a switch circuit S1. Among these, the mode determination circuit MOD is supplied with an inverted signal of the row address strobe signal RASB by the input buffer RB, that is, the external row address strobe signal ERAS, and at the same time, an inverted signal of the column address strobe signal CASB by the input buffer CB, that is, the external column. An address strobe signal ECAS is supplied. The output signal of the mode determination circuit MOD, that is, the internal control signal SRF is supplied to the refresh oscillation circuit ROSC of the refresh control circuit RFC and also to the switch circuit S1 as a switch control signal.
[0036]
The mode determination circuit MOD of the timing generation circuit TG is based on the level and time relationship of the external row address strobe signal ERAS and the external column address strobe signal ECAS, that is, the row address strobe signal RASB and the column address strobe signal CASB as activation control signals. Then, the operation mode of the dynamic RAM is determined, and an internal control signal for mode control including the internal control signal SRF is selectively generated. As shown in FIG. 3, in the dynamic RAM, after the row address strobe signal RASB is set to the low level at least a predetermined time tCSR later than the column address strobe signal CASB, the dynamic RAM continues to be set to the low level further after the predetermined time tRAS. The self-refresh mode is selectively set, and in response to this, the internal control signal SRF is selectively set to the high level.
[0037]
On the other hand, the external row address strobe signal ERAS is supplied from the input buffer RB to the normally-on input terminal of the switch circuit S1 of the timing generation circuit TG, and the internal row address strobe signal from the refresh control circuit RFC is supplied to the normally-off input terminal. IRAS is supplied. The switch circuit S1 selects the external row address strobe signal ERAS, that is, the row address strobe signal RASB supplied from the input buffer RF when the dynamic RAM is in a normal operation mode and the internal control signal SRF is at a low level. This is transmitted to the X decoder drive signal generation circuit XEG. When the dynamic RAM is set to the self-refresh mode and the internal control signal SRF is set to the high level, the internal row address strobe signal IRAS supplied from the refresh control circuit RFC is selected and the X decoder drive signal generation circuit XEG is selected. introduce.
[0038]
The X decoder drive signal generation circuit XEG drives the X decoder for the X address decoder XD and the redundant X address decoder RXD based on the external row address strobe signal ERAS or the internal row address strobe signal IRAS transmitted through the switch circuit S1. A signal XE is selectively generated. Thus, as shown in FIG. 3, the X decoder drive signal XE formed in the self-refresh mode is set to the high level for a predetermined period in response to the rising edge of the internal row address strobe signal IRAS to the high level. It becomes.
[0039]
Next, the refresh control circuit RFC includes a refresh oscillation circuit ROSC that receives the internal control signal SRF from the timing generation circuit TG, a frequency divider circuit FD that receives an internal clock signal that is an output signal of the refresh oscillation circuit ROSC, and a frequency divider circuit FD. A refresh address counter RCTR that receives a refresh clock signal CR that is an output signal, a relief address memory RROM that holds an address of a defective word line in the memory array MARY, a defective address that is an output signal of the relief address memory RROM, and an X address buffer XB And redundant address comparison circuit RADC receiving internal address signals X0 to Xi as output signals.
[0040]
Among these, the refresh oscillation circuit ROSC is selectively activated in response to the high level of the internal control signal SRF when the dynamic RAM is set to the self-refresh mode, and generates an internal clock signal having a predetermined cycle. Further, the frequency dividing circuit FD divides the internal clock signal output from the refresh oscillation circuit ROSC, and the shortest information holding time of the memory cells constituting the memory array MARY, that is, the refresh cycle tREF defined as the product specification. For example, the refresh clock signal CR having a period equal to or less than 1 / (2 + 1) is generated. Thus, as shown in FIG. 3, the refresh clock signal CR is a pulse that is selectively formed in the predetermined cycle while the dynamic RAM is in the self-refresh mode and the internal control signal SRF is at the high level. Signal.
[0041]
On the other hand, the refresh address counter RCTR of the refresh control circuit RFC is a binary counter of j + k bits, that is, i + 1 + 1, that is, i + 2 bits, and advances in response to the falling edge of the refresh clock signal CR output from the frequency divider circuit FD. An operation is performed to generate refresh address signals R0 to Ri + 1. Of these, the lower j bits, i + 1 bits, of the refresh address signals R0 to Ri are supplied to the X address buffer XB, and the upper k bits, ie, the uppermost 1 bit, the refresh address signal Ri + 1 are ORed as a so-called refresh switching control signal. It is supplied to one input terminal of the gate OG1. Note that the refresh address counter RCTR retains the count value even when the self-refresh mode ends.
[0042]
Thus, the lower i + 1 bits corresponding to the refresh address signals R0 to Ri of the refresh address counter RCTR are set when the dynamic RAM is set to the self-refresh mode and the internal control signal SRF is set to the high level as shown in FIG. In response to the falling edge of the refresh clock signal CR, the modulo [2 to the power of j], that is, [m + 1] is counted up, and one bit corresponding to the most significant bit refresh address signal Ri + 1 receives the overflow of the lower i + 1 bits. Modulo [2 to the power of k], that is, counted up with [2]. Therefore, the count value of the lower i + 1 bits of the refresh address counter RCTR is first counted up so that the normal word lines W0 to Wm of the memory array MARY are specified in one cycle while the refresh address signal Ri + 1 of the most significant bit is set to the low level. At the same time, while the refresh address signal Ri + 1 is set to the high level, the normal word lines W0 to Wm of the memory array MARY are similarly counted up to designate.
[0043]
The relief address memory RROM of the refresh control circuit RFC includes a plurality of fuse circuits, and an abnormality is detected in one of the memory cells MC coupled thereto, so that the redundant word line of the redundant memory array RARY is replaced with a redundant word line of the memory array MARY. The address of the defective word line, that is, the defective address is held. The redundant address comparison circuit RADC compares the i + 1-bit defective address supplied from the relief address memory RROM with the internal address signals X0 to Xi supplied from the X address buffer XB for each normal access or refresh operation. When the two addresses match, the output signal, that is, the redundancy enable signal RE is selectively set to the high level. Therefore, in the embodiment of FIG. 3 in which, for example, the word line W2 of the memory array MARY is replaced with the redundant word line WR of the redundant memory array RARY as a defective word line, the redundant enable signal RE is the refresh address signal R0 of the lower i + 1 bits. Each time the count value of Ri becomes 2, it is selectively set to the high level.
[0044]
As described above, the redundancy enable signal RE generated by the redundancy address comparison circuit RADC of the refresh control circuit RFC is supplied to the redundancy X address decoder RXD and the X address decoder XD, and also the OR gate OG1 of the refresh control circuit RFC. It is supplied to the other input terminal. The other input terminal of the OR gate OG1 is supplied with the refresh address signal Ri + 1 of the most significant bit from the refresh address counter RCTR, and the output signal is supplied to one input terminal of the AND gate AND1. The refresh clock signal CR is supplied from the frequency divider FD to the other input terminal of the AND gate AG1, and the output signal is supplied to the switch circuit S1 of the timing generator TG as the internal row address strobe signal IRAS.
[0045]
As a result, the internal row address strobe signal IRAS, which is the output signal of the AND gate AG1 of the refresh control circuit RFC, is redundantly enabled when the output signal of the OR gate OG1 is set to the high level, in other words, as shown in FIG. When the signal RE is set to the high level or the most significant bit refresh address signal Ri + 1 is set to the high level, the signal RE is selectively set to the high level in synchronization with the refresh clock signal CR. As described above, the internal row address strobe signal IRAS is supplied to the X decoder drive signal generation circuit XEG via the switch circuit S1 of the timing generation circuit TG, and is used to generate the X decoder drive signal XE. The X address decoder XD performs an operation of selecting the word lines W0 to Wm of the memory array MARY when the redundancy enable signal RE is at a low level, but the word lines W0 to Wm are selected when the redundancy enable signal RE is at a high level. And the redundant X address decoder RXD selects the redundant word line WR of the redundant memory array RARY instead.
[0046]
For these reasons, the selection operation of the normal word lines W0 to Wm constituting the memory array MARY is performed when the upper k bits of the refresh address counter RCTR, that is, the count value of the most significant 1 bit is 1, that is, the refresh address signal Ri + 1 is at the high level. In some cases, the redundant enable signal RE is selectively performed in accordance with the lower j bits on condition that the redundant enable signal RE is at a low level. However, the redundant word line WR of the redundant memory array RARY is selected according to the count value of the most significant 1 bit. Regardless, it is selectively performed only on the condition that the redundancy enable signal RE is at a high level, and the refresh cycle thereof is an integral fraction of the refresh cycle for the normal word lines W0 to Wm of the memory array MARY, that is, 2 minutes. It becomes 1 of. Therefore, even when some deterioration in the information retention characteristic is observed in any of the n + 1 redundant memory cells RC coupled to the redundant word line WR of the redundant memory array RARY, this is compensated for and normal defect relief is realized. be able to. As a result, it is possible to increase the relief efficiency of the dynamic RAM having the self-refresh mode and the defect relief function using the redundant word line, and to increase the product yield.
[0047]
As is clear from the above description, the refresh operation related to the redundant word line WR of the redundant memory array RARY is performed when the redundant word line WR is replaced with one of the normal word lines W0 to Wm constituting the memory array MARY. If it is selectively performed and defect repair is not performed, it is not performed even if the refresh address signal Ri + 1 of the most significant bit is at a low level.
[0048]
FIG. 4 shows a connection diagram of a second embodiment of the refresh related circuit included in the dynamic RAM to which the present invention is applied. FIG. 5 shows a signal waveform diagram of one embodiment in the self-refresh mode of the refresh related circuit of FIG. Since the dynamic RAM and the refresh related circuit of this embodiment basically follow the embodiment of FIGS. 1 to 3, only the differences will be described.
[0049]
In FIG. 4, the refresh control circuit RFC of the dynamic RAM of this embodiment receives the least significant bit refresh address signal R0 at one input terminal and the most significant bit refresh address signal Ri + 1 at the other input terminal. An exclusive OR circuit EO is included. The output signal of the exclusive OR circuit EO is supplied to one input terminal of the OR gate OG1 that receives the redundancy enable signal RE at the other input terminal. The output signal of the OR gate OG1 is supplied to one input terminal of the AND gate AG1. The other input terminal of the AND gate AG1 is supplied with the refresh clock signal CR from the frequency dividing circuit FD, and the output signal is supplied to the normally-off input terminal of the switch circuit S1 of the timing generation circuit TG as the internal row address strobe signal IRAS. Supplied.
[0050]
Thereby, the internal row address strobe signal IRAS is set to a high level when the output signal of the OR gate OG1 is set to high level, that is, the redundancy enable signal RE is set to high level or the output signal of the exclusive OR circuit EO is set to high level. In other words, when the refresh address signals R0 and Ri + 1 are at different logic levels, they are selectively set to a high level in synchronization with the refresh clock signal CR. Needless to say, the refresh address signal R0 of the least significant bit is selectively set to the low level when the even-numbered word lines W0, W2 to Wm-1 of the memory array MARY are designated, and the odd-numbered word lines W1, W3 to When Wm is designated, it is at a high level.
[0051]
Therefore, the output signal of the exclusive OR circuit EO is provided on condition that the odd-numbered word lines W1, W3 to Wm of the memory array MARY are designated when the most significant bit refresh address signal Ri + 1 is set to the low level. When selectively set to the high level and the refresh address signal Ri + 1 of the most significant bit is set to the high level, it is selectively provided that the even-numbered word lines W0, W2 to Wm-1 of the memory array MARY are designated. It will be a high level. The redundancy enable signal RE is selectively set to the high level every time a normal word line replaced with the redundancy word line WR of the redundancy memory array RARY of the memory array MARY is designated as in the first embodiment. The
[0052]
Therefore, in the embodiment of FIG. 5 in which the word line W2 of the memory array MARY is replaced with the redundant word line WR, the odd number of the memory array MARY is kept while the refresh address signal Ri + 1 of the most significant bit is set to the low level. The word lines W1, W3 to Wm + 1 are sequentially selected and the redundant word line WR is selected at the timing corresponding to the defective word line W2, but the refresh address signal Ri + 1 of the most significant bit is set to the high level. During this time, the even-numbered word lines W0, W4 to Wm are sequentially selected, and the redundant word line WR is selected at a timing corresponding to the defective word line W2.
[0053]
That is, in this embodiment, as in the first embodiment, the refresh operation for the normal word lines W0 to Wm of the memory array MARY is performed once every refresh cycle tREF, and the redundant word of the redundant memory array RARY is executed. The refresh operation for the line WR is performed twice or twice, but the refresh operation for the normal word lines W0 to Wm is performed according to whether the number is an odd number or an even number, that is, each refresh address signal Ri + 1. It is performed with average dispersion for the count value. As a result, it is possible to obtain the same operational effects as the embodiments of FIGS. 1 to 3 and average the power consumption in the self-refresh mode performed by, for example, battery backup of the dynamic RAM, and the battery serving as the operation power supply It will be possible to reduce the burden.
[0054]
FIG. 6 is a connection diagram of a third embodiment of the refresh related circuit included in the dynamic RAM to which the present invention is applied. FIG. 7 shows a signal waveform diagram of one embodiment in the self-refresh mode of the dynamic RAM of FIG. 6, and FIG. 8 shows a signal waveform diagram of one embodiment in the CBR refresh mode. Yes. The dynamic RAM and the refresh related circuit of this embodiment basically follow the embodiment of FIG. 1, FIG. 2 and FIG. 3, and therefore only the differences will be described. In FIG. 7, the refresh address counter RCTR of the refresh control circuit RFC is composed of a binary counter of Modulo [5].
[0055]
In FIG. 6, the refresh control circuit RFC of the dynamic RAM of this embodiment is composed of a binary counter of j bits, i + 1 bits, that is, 3 bits, and its counter modulo is set to [2 to the (j−1) th power + 1], that is, [5] includes a refresh address counter RCTR and a k-bit or 1-bit flip-flop FF that receives an overflow signal, that is, a carry signal of the refresh address counter RCTR. The dynamic RAM memory array MARY includes m + 1, that is, 2 (j + k-1) powers, that is, eight normal word lines W0 to Wm, that is, W0 to W7. The redundant memory array RARY Similar to the embodiment, it includes one redundant word line WR.
[0056]
An output signal of the OR gate OG2 is supplied to the refresh address counter RCTR of the refresh control circuit RFC. One input terminal of the OR gate OG2 is supplied with the internal control signal CBR from the mode determination circuit MOD of the timing generation circuit TG, and the other input terminal is supplied with the refresh clock signal CR from the frequency dividing circuit FD. . The output signal of the lower i bits of the refresh address counter RCTR, that is, the refresh address signals R0 to Ri-1, is supplied to the X address buffer XB, and the most significant bit, that is, the refresh address signal Ri is supplied to one input terminal of the OR gate OG3. Is done. The other input terminal of the OR gate OG3 is supplied with the redundancy enable signal RE from the redundancy address comparison circuit RADC, and its output signal is common to the X address decoder XD and the redundancy X address decoder RXD as the final redundancy enable signal REP. To be supplied. The non-inverted output signal of the flip-flop FF is supplied to the X address buffer XB as the refresh address signal Ri + 1.
[0057]
The dynamic RAM of this embodiment has a CBR refresh mode that can be executed with the initiative of the access device side while suppressing an increase in hardware on the access device side in combination with the refresh address counter RCTR of the refresh control circuit RFC. The internal control signal CBR supplied to one input terminal of the OR gate OG2 is selectively set to a high level at a predetermined timing when the dynamic RAM is set to the CBR refresh mode.
[0058]
The refresh address counter RCTR of the refresh control circuit RFC receives the falling edge of the refresh clock signal CR supplied from the frequency dividing circuit FD when the dynamic RAM is set in the self-refresh mode, and the stepping operation of the modulo [5]. When the CBR refresh mode is set, the step of Modulo [5] is performed in response to the falling edge of the internal control signal CBR supplied from the mode determination circuit MOD of the timing generation circuit TG, and the refresh address is set. Signals R0 to Ri are sequentially generated. Further, the flip-flop FF performs a stepping operation in response to the overflow signal of the refresh address counter RCTR, and generates a refresh address signal Ri + 1.
[0059]
Thereby, refresh address signals R0 to Ri, that is, R0 to R2, which are output signals of the refresh address counter RCTR, correspond to modulo [5] as shown in FIG. 7 when the dynamic RAM is set to the self-refresh mode. The refresh address signal Ri + 1, that is, R3, which is the output signal of the flip-flop FF, is alternately set to the low level or the high level every time the refresh address counter RCTR overflows to selectively designate five count values. Will be.
[0060]
On the other hand, when the dynamic RAM is in the refresh mode and the internal control signal RF is set to the high level, the X address buffer XB selects the refresh address signals R0 to Ri-1 supplied from the refresh address counter RCTR and selects the internal address. The signals X0 to Xi-1 are selected, and the refresh address signal Ri + 1 supplied from the flip-flop FF is selected as the internal address signal Xi of the most significant bit. At this time, the redundant address comparison circuit RADC uses the defective address supplied from the relief address memory RROM and the refresh address signals R0 to Ri-1 and Ri + 1 supplied as the internal address signals X0 to Xi from the X address buffer XB for each bit. The redundancy enable signal RE is selectively set to the high level by comparing with each other, and the OR gate OG3 outputs the redundancy enable signal as its output signal on condition that either the refresh address signal Ri or the redundancy enable signal RE is set to the high level. REP is selectively set to a high level.
[0061]
Therefore, in the embodiment of FIG. 7 in which, for example, the word line W2 of the memory array MARY is a defective word line, the redundancy enable signal REP has the refresh address signals R0 to Ri-1 and Ri + 1, that is, the count values of R0 to R1 and R3. It becomes 2 that designates a defective word line, or the refresh address signal Ri, that is, R2, is set to a high level, so that the redundant word line WR is selectively set to a high level. The In another cycle in which the redundancy enable signal REP is set to the low level, normal word lines W0, W1 and W3 to W7 of the memory array MARY are sequentially selected according to the count values of the refresh address signals R0 to R1 and R3. Is selected.
[0062]
In other words, in this embodiment, the redundant word line WR has a refresh clock signal CR of 2 (j−1) +1, in addition to the cycle in which the word line targeted for defect relief of the memory array MARY is designated. The refresh operation is performed every five cycles, and the refresh operation for the normal word line of the memory array MARY is performed once while the refresh operation is performed three times. As a result, it is possible to obtain the same operational effects as in the above-described embodiment, thereby increasing the relief efficiency of the dynamic RAM and increasing the product yield.
[0063]
In this embodiment, as described above, the output signal of the OR gate OG2 serving as the stepping clock of the refresh address counter RCTR is also generated by the internal control signal CBR. Therefore, in the dynamic RAM, as shown in FIG. 8, the same refresh operation is performed even in the CBR refresh mode, and the same effect as the self refresh mode can be obtained.
[0064]
FIG. 9 is a connection diagram of a fourth embodiment of the refresh related circuit included in the dynamic RAM to which the present invention is applied. FIG. 10 shows a signal waveform diagram of one embodiment in the self-refresh mode of the refresh related circuit of FIG. Since the dynamic RAM and the refresh related circuit of this embodiment basically follow the embodiment of FIGS. 6 to 8, only the differences will be described. In FIGS. 9 and 10, portions related to the relief address memory RROM and the redundant address comparison circuit RADC of the refresh control circuit RFC are omitted.
[0065]
In FIG. 9, the dynamic RAM of this embodiment includes a plurality of or two memory arrays MARY0 and MARY1, redundant memory arrays RARY0 and RARY1, and an X address decoder XD0 provided corresponding to these memory arrays and redundant memory arrays. And XD1 and redundant X address decoders RXD0 and RXD1. Among these, the memory array MARY0 includes (m + 1) / 2 word lines W0, W2 to .about.Wm−1 assigned with even numbers, and the memory array MARY1 is similarly (m + 1) / Two word lines W1, W3 to .about.Wm are included. The redundant memory array RARY0 is not particularly limited, but includes one redundant word line WR0, and the redundant memory array RARY1 similarly includes one redundant word line WR1.
[0066]
The X address decoders XD0 and XD1 are commonly supplied with the internal address signals X0 to Xi from the X address buffer XB and are commonly supplied with the X decoder drive signal XE from the timing generation circuit TG. The redundant X address decoders RXD0 and RXD1 are supplied with the X decoder driving signal XE in common, and the redundant X address decoder RXD0 is supplied with the internal address signal X0 of the least significant bit from the X address buffer XB. The inverted signal from the inverter V1 is supplied to the redundant X address decoder RXD.
[0067]
Thus, for example, in the dynamic RAM memory array MARY0 in the self-refresh mode, as shown in FIG. 10, when the count value of the refresh address signals R0 to Ri is an even number, that is, when the refresh address signal R0 is at the low level, When refresh operations relating to normal word lines W0, W2 to Wm-1 are sequentially performed and the count value of refresh address signals R0 to Ri is an odd number, that is, refresh address signal R0 is at a high level, redundant word line of redundant memory array RARY0 A refresh operation relating to WR0 is performed. On the contrary, in the memory array MARY1, when the count value of the refresh address signals R0 to Ri is an odd number, that is, when the refresh address signal R0 is at the high level, the refresh operation for the normal word lines W1, W3 to Wm is performed. When the count values of the signals R0 to Ri are an even number, that is, the refresh address signal R0 is at the low level, the refresh operation for the redundant word line WR1 of the redundant memory array RARY1 is performed.
[0068]
Needless to say, the refresh operation related to the redundant word lines WR0 and WR1 of the redundant memory arrays RARY0 and RARY1 is performed when a defective word line replaced with each redundant word line of the memory array MARY0 or MARY1 is designated by the refresh address signals R0 to Ri. Is done in the same way. Therefore, the frequency of the refresh operation relating to the redundant word lines WR0 and WR1 is (m + 1) / 2 times that of the normal word lines constituting the memory arrays MARY0 and MARY1, and the information retention characteristics of the memory cells MC coupled to the defective word lines are Even if it is considerably deteriorated, this can be compensated and defect relief can be realized.
[0069]
The effects obtained from the above embodiments are as follows. That is,
(1) Refresh for sequentially designating word lines to be refreshed in a semiconductor memory device such as a dynamic RAM having a refresh mode such as a self-refresh mode and a CBR refresh mode and having a defect relief function using redundant word lines For example, a refresh switching control signal bit is provided as the most significant bit of the address counter.For example, when the refresh switching control signal is at a low level, only a refresh operation relating to a redundant word line is executed, and when the refresh switching control signal is at a high level, A memory cell coupled to the redundant word line by executing a refresh operation related to the redundant word line and executing a refresh operation related to the redundant word line in a cycle of, for example, one half of the refresh operation related to the normal word line. Even when a degree of deterioration in the information holding property can be seen, running at a frequency refresh operation only, for example twice the redundant word line, there is an advantage that it is possible to compensate for the deterioration of data holding characteristics of the redundant memory cell.
(2) According to the above item (1), it is possible to obtain an effect that the repair efficiency by a redundant word line such as a dynamic RAM having a refresh mode and a defect repair function can be improved and the product yield can be increased.
[0070]
(3) In the above items (1) and (2), the refresh operation relating to the normal word line is carried out by averaging the respective count values of the refresh switching control signal, so that, for example, by a battery backup such as a dynamic RAM It is possible to average the power consumption in the self-refresh mode to be performed and to reduce the burden on the battery serving as the operation power supply.
(4) In the above items (1) and (2), when the dynamic RAM or the like includes a plurality of memory arrays, when a refresh operation relating to a normal word line is performed in a certain memory array, a redundant word is generated in another memory array. By simultaneously performing the refresh operation for the lines, the frequency of the refresh operation for the redundant word lines can be increased, the relief efficiency of the dynamic RAM and the like can be further increased, and the product yield can be further increased.
[0071]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the memory array MARY and the redundant memory array RARY can be integrated as one functional block, or can be divided into an arbitrary number of memory mats including its direct peripheral circuit. The dynamic RAM can take an arbitrary bit configuration such as x4 bits or x16 bits, and does not require address multiplexing. Furthermore, the dynamic RAM can take an arbitrary block configuration, and various embodiments can be adopted in terms of the combination of the start control signal, the address signal, the internal control signal, etc., the polarity of the power supply voltage, and the like.
[0072]
2, 4, 6, and 9, redundant memory array RARY can include an arbitrary number of redundant word lines, and can also include redundant bit lines for relieving defective bit lines. When the redundant memory array RARY includes, for example, two redundant word lines, the refresh operation for each redundant word line is executed in the same manner every time a corresponding defective word line is designated in the embodiments of FIGS. Can do. In the embodiment shown in FIG. 6, the counter modulo of the refresh address counter RCTR can be easily dealt with by setting [2 (j−1) th power + 2]. In the embodiment shown in FIG. A 1-bit binary counter for sequentially designating a plurality of redundant word lines provided in the arrays RARY0 or RARY1 may be prepared in common for both redundant memory arrays. The bit of the refresh address signal used as the refresh switching control signal is not limited to the most significant bit and can be arbitrarily selected. The relief address memory RROM, the redundant address comparison circuit RADC, and the like can be separated as functional blocks separate from the refresh control circuit RFC. Further, the block configuration of the timing generation circuit TG and the refresh control circuit RFC and the specific configuration of the logic circuit related to each signal can take various embodiments as long as the basic logic conditions are not changed.
[0073]
2 and 4, the dynamic RAM can have a CBR refresh mode. In this case, as in the embodiments of FIGS. 6 and 9, an OR gate OG2 for receiving the internal control signal CBR is additionally provided at one input terminal, and the output signal is incremented with respect to the refresh address counter RCTR of the refresh control circuit RFC. What is necessary is just to supply as a clock.
[0074]
3, 5, 7 to 8, and 10, the absolute level of each signal, the time relationship, the effective level, and the like do not limit the present invention.
[0075]
In the above description, the case where the invention made mainly by the present inventor is applied to the dynamic RAM, which is the field of use behind it, has been described. However, the present invention is not limited to this. The present invention can also be applied to various types of memory integrated circuit devices such as a synchronous DRAM configured as above, and logic integrated circuit devices including such memory integrated circuit devices. The present invention can be widely applied to a semiconductor memory device having at least a refresh mode and having a defect relief function using a redundant word line, and a device or system including the same.
[0076]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like having a refresh mode such as a self-refresh mode and a CBR refresh mode and having a defect relief function using redundant word lines, for example, a refresh address counter for sequentially designating word lines to be refreshed is used. A bit for a refresh switching control signal is provided as an upper bit. For example, when the refresh switching control signal is at a low level, only a refresh operation for a redundant word line is executed, and when it is at a high level, a refresh for a normal word line and a redundant word line is performed. By executing the operation and performing the refresh operation for the redundant word line at a cycle of, for example, one half of the refresh operation for the normal word line, the information holding characteristics of the memory cells coupled to the redundant word line are performed. Some even if the deterioration is observed, and run at a frequency refresh operation only, for example twice the redundant word line, it is possible to compensate for the deterioration of data holding characteristics. As a result, the repair efficiency by the redundant word line such as the dynamic RAM having the refresh mode and the defect repair function can be increased, and the product yield can be increased.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.
FIG. 2 is a connection diagram showing a first embodiment of a refresh related circuit included in the dynamic RAM of FIG. 1;
FIG. 3 is a signal waveform diagram showing one embodiment in a self-refresh mode of the refresh related circuit of FIG. 2;
FIG. 4 is a connection diagram showing a second embodiment of a refresh related circuit included in a dynamic RAM to which the present invention is applied;
5 is a signal waveform diagram showing an example of the refresh-related circuit in FIG. 4 in a self-refresh mode. FIG.
FIG. 6 is a connection diagram showing a third embodiment of a refresh related circuit included in a dynamic RAM to which the present invention is applied;
7 is a signal waveform diagram showing an example of the refresh-related circuit in FIG. 6 in the self-refresh mode. FIG.
8 is a signal waveform diagram showing an example of the refresh-related circuit in FIG. 6 in the CBR refresh mode.
FIG. 9 is a connection diagram showing a fourth embodiment of a refresh related circuit included in a dynamic RAM to which the present invention is applied;
10 is a signal waveform diagram showing an example of the refresh-related circuit in FIG. 9 in the self-refresh mode. FIG.
[Explanation of symbols]
MARY, MARY0 to MARY1 ... Memory array, RARY, RARY0 to RARY1 ... Redundant memory array, XD, XD0 to XD1 ... X address decoder, RXD, RXD0 to RXD1 ... Redundant X address decoder, XB ... X address buffer , RFC ... refresh control circuit, SA ... sense amplifier, YD ... Y address decoder, YB ... Y address buffer, IO ... data input / output circuit, TG ... timing generation circuit.
D0 to D7: Input or output data or input / output terminal thereof, RASB: Row address strobe signal or input terminal thereof, CASB: Column address strobe signal or input terminal thereof, WEB: Write enable signal or input terminal thereof, A0 to Ai: Address signal or its input terminal.
W0 to Wm: Normal word line, WR, WR0 to WR1: Redundant word line, B0 * to Bn *: Complementary bit line, MC: Memory cell, RC: Redundant memory cell, RB: Row address strobe Signal input buffer, CB: Column address strobe signal input buffer, MOD: Mode determination circuit, S1: Switch circuit, XEG: X decoder drive signal generation circuit, ROSC: Refresh oscillation circuit, FD: Minute Peripheral circuit, RCTR: Refresh address counter, RROM: Relief address memory, RADC: Redundant address comparison circuit.
SRF: Internal control signal (self-refresh mode signal), CR: Refresh clock signal, R0 to Ri + 1 ... Refresh address signal, RE, REP ... Redundancy enable signal, ERAS ... External row address strobe signal, ECAS ... External column address strobe signal, IRAS... Internal row address strobe signal, XE... X decoder drive signal.
V1: inverter, OG1 to OG3: OR gate, AG1: AND gate, EO: exclusive OR circuit.

Claims (2)

A memory array formed in a first block and including a plurality of normal word lines and a redundant word line selected in place of the normal word line in which an abnormality is detected among the normal word lines;
A memory array formed in a second block and including a plurality of normal word lines and a redundant word line selected in place of the normal word line in which abnormality is detected among the normal word lines;
With refresh control circuit,
The refresh control circuit
At the same time as the refresh operation of the memory array of the first block, the refresh operation of the redundant word line of the second block is simultaneously executed,
A dynamic RAM comprising a refresh operation of the redundant word lines of the first block simultaneously with a refresh operation of the memory array of the second block. In claim 1,
A dynamic RAM, wherein each of the first and second blocks has a plurality of the memory arrays.

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