JPS61294689A - Dynamic ram - Google Patents

Abstract

PURPOSE:To reduce the current consumption in refreshing operation by incorporating a defective address storage circuit which inhibits a column system from operating in refreshing operation mode if there if a defective address and a redundancy circuit which switches a memory array to a stand-by memory array in a RAM. CONSTITUTION:Stand-by memory array YR-ARY elements 1 and 2 are provided to remedy faults of memory array M-ARY elements 1 and 2 and a defective address signal is compared by an address comparator AC with address signals a0-an supplied from an address buffer C-ADB. Then if there is a defective bit array, the memory array elements are switched to the memory array element 1 or 2 for redundancy, and the operation of a storage circuit included in the comparator AC is stopped so as to reduce the power consumption of the address storage circuit. This storage circuit is provided with a fuse means made of polycrystal Si and the means F2 is blown by an MOSFET for writing or by being irradiated with a laser light beam.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a dynamic RAM (random access memory), and relates to a technique that is effective when used in a dynamic RAM with a built-in spare memory array, for example. It is.

[Background technology]

In dynamic RAM, a defective bit relief method is known in order to improve the product yield. In order to employ the defective bit relief scheme, appropriate storage means for storing defective addresses in the memory array and their address comparison circuits, as well as additional circuits such as redundant circuits (spare memory arrays) are provided.

As the storage means, it has been proposed to use a fuse made of polysilicon, for example, and to melt it electrically or cut it with a laser beam. Such storage means causes a steady direct current to flow through the fuse means that is not blown during the read operation, which is a factor that increases current consumption.

By the way, in dynamic memory cells formed on semiconductor substrates, stored information is held in the form of charges, and the amount of held charges decreases over time due to leakage current, etc. ,
In order to always store accurate information in a memory cell, it is necessary to read out the information stored in the memory cell before it is lost, amplify it, and write it back into the same memory cell. It is necessary to perform a refresh operation. In such a refresh operation, row-related atranging (word line selection operation and sense amplifier amplification operation) is performed, and column-related addressing is not performed.

Focusing on the refresh operation, the inventor of the present application has proposed that when a column-based spare memory array is provided as the redundant circuit, the read operation of the column-based address storage circuit is prohibited during the refresh operation, resulting in wasted current. The idea was to prevent the consumption of

As an example of a dynamic RAM with a redundant circuit, for example, see Nikkei Electronics J, July 21, 1980 issue, pages 189 to 20i, published by Nikkei McGraw-Hill.
Examples of automatic refresh methods include ``Electronic Technology 1 Magazine Vol. 123, Arashi 3 pp. 30-33''.

[Purpose of the invention]

An object of the present invention is to provide a dynamic RAM that reduces power consumption during refresh operations.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

(Summary of the Invention) A brief overview of typical inventions disclosed in this application is as follows.

That is, in the refresh operation mode, by inhibiting the operation of the column-based defective address storage circuit, generation of reactive current flowing through the fuse means that is selectively blown in accordance with the defective address is prohibited.

〔Example〕

FIG. 1 shows a dynamic RA according to an embodiment of the present invention.
A block diagram of M is shown. The dynamic RAM shown in the figure is a dynamic RAM that is accessed in 8-bit units, although it is not particularly limited, and is formed on a semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

In this embodiment, the memory array is arranged in two parts, M-ARYI and M-ARY2, although this is not particularly limited. Each memory array M-ARYI, M-
In ARY2, eight complementary data line pairs are formed as one set, and are formed to extend in the vertical direction in the figure.

In other words, rather than configuring the memory array by dividing it into 8 blocks (mats), one address is assigned to each 8-bit data line and 8 complementary data line pairs adjacent to each other in the same memory array. The memory arrays M-ARYI and M-ARY2 are arranged in matrix in the memory arrays M-ARYI and M-ARY2. The memory cell is a 1MO consisting of a capacitor for information storage and a MOSFET for address selection.
A type 3 dynamic memory cell is used. The gate of the MOSFET for address selection of this memory cell is
It is coupled to the word line and its drain (source) is coupled to the data line.

Row-related address selection lines (word lines) are formed so as to extend horizontally in common to each of the memory arrays M-ARYI and M-ARY2, and are sequentially arranged vertically in the figure.

The above complementary data line pair includes column switches C-8Wl, C
-8 common complementary data line pairs CDI, C via 3W2
Selectively connected to D2. In the figure, the common complementary data line pair runs in the horizontal direction. This common complementary data line pair CD1. CD2 is main amplifier MAI, MA2
are connected to the respective input terminals.

The sense amplifiers SAI and SA2 receive a minute read voltage on the complementary data line pair of the memory array, are activated by the timing signal φpa, and amplify the complementary data line pair to a high level/low level according to the read voltage. .

The row address buffer R-ADB receives m from an external terminal.
It receives the +1 bit address signal RAD, forms internal complementary address signals aO-am, 70-am, and sends them to the row address decoder R-DCH. In the following description and drawings, a pair of internal complementary address signals, for example 802-0, will be expressed as internal complementary address signal 0.

Therefore, the internal complementary address signal aO~am, 1
0 to τm are expressed as internal complementary address signals 10 to 1m.

Row address decoder R-DCR selects one word line in accordance with address signal aQ-xam in synchronization with word line selection timing signal φX.

Column address decoder C-ADB receives an n+1-bit address signal CAD from an external terminal, forms internal complementary address signals aO-an, aQ-Tn, and sends them to column address decoder C-DCR. In addition, in accordance with the representation of the internal complementary address signals, in the drawings and the following description, the internal complementary address signals aQman, aQ
~an is expressed as an internal complementary address signal 10~satn.

Column address decoder C-DCR forms a selection signal synchronized with data line selection timing signal φy for eight complementary data line pairs in accordance with the address signals i0 to an.

Column switches C-3WI and C-5W2 receive the selection signal and connect the eight pairs of complementary data lines to the corresponding eight pairs of common complementary data lines. In addition, in the figure, the complementary data line pair and the common complementary data line pair shown as an example are represented by one line.

The input/output circuit I10 is composed of a main amplifier and a data output buffer sofa for reading, and a data input buffer for writing. During reading, the input/output circuit I10 amplifies one of the main amplifiers MAL or MA2, which is activated, and outputs an external signal. Send to terminal DA. Also, during a write operation, the write output is sent to the common complementary data line pair CDI, CD2.
supply to. In the figure, this write signal path is omitted.

The internal control signal generation circuit TG generates two external control signals C8.
(chip select signal), WE (write enable signal), and, although not particularly limited, the above address signal a.
Address signal change detection signal φ formed by address signal change detection circuit ATD receiving O~am and aO~an
In response to this, various timing signals necessary for memory operations are formed and sent out. The RAM is operated in an internally synchronous manner by forming a series of timings for internal operations based on the detection signal φ generated by the address signal change detection circuit ATD as described above. As a result, even though a dynamic memory cell as described above is used, it can be accessed from the outside in the same way as a static RAM (configuring a so-called pseudo-static RAM). For such operations, the above address buffers R-ADB, C-ADB
and address decoders R-DCR, C-DCRI.

Peripheral circuits such as C-DCR2 are 0MO5 as described later.
(Complementary type MO3) It is constituted by a static type circuit.

The above memory array M-ARYI, memory array M-AR
In order to relieve the defect in Y2, these memory arrays M-ARY 1. Spare memory arrays YR-ARYI and YR-ARY2 are provided for MARY2, respectively. These spare memory arrays YR-ARY1 and Y
In order to switch to R-A, RY 2, an address storage means for storing a defective address signal and a defective bit address, and an address signal 0 to an supplied from the defective address signal and the address buffer C-ADH are used. An address conveyor AC is provided, which includes a column address comparison circuit that compares the stored defective addresses and detects that a stored defective address has been input. This address conveyor AC detects access to a defective address, and detects access to the redundant memory array YR-ARYI (or YR-ARY
2) A selection operation is performed in which the data line is connected to the common complementary data line instead of the defective bit array. The operation of the defective address storage circuit included in the address conveyor AC is stopped in the refresh operation mode, as will be described later, in order to reduce power consumption.

Note that a similar redundant memory array may be provided for the word line as well.

The automatic refresh circuit REFC includes a refresher address counter, a timer, etc., and is activated by being supplied from an external terminal or by setting the refresher signal REF to a low level. That is, when the refresh signal REF is set to a low level while the chip selection signal C3 is at a high level, the automatic refresher circuit REFC switches the multiplexer provided at the output part of the row address buffer R-ADB using a control signal (not shown), and The refresh address signal formed by the refresh address counter is transmitted to the row decoder R-DCR to perform a refresh operation (auto-refresh) by selecting one word line and amplifying the sense amplifier SA. If it is kept at a low level, a timer is activated, and the refresh address counter is incremented at regular intervals, and a continuous refresh operation (self-refresh) is performed during this period.

FIG. 2 shows a circuit diagram of an embodiment of the main part of the address conveyor AC.

The above-mentioned set of address conveyors is composed of a number of defective address storage circuits and address comparison circuits corresponding to the number of bits (n+1) of the address signal, and one enable circuit.

The 1-bit storage circuit for the defective address is constructed by a write MOSFET (not shown) or fuse means F2 made of a polysilicon layer that is cut by laser beam irradiation. In order to obtain an electric signal depending on whether or not the fuse means is disconnected, one end of the fuse means F2 is
A MOSFET Q2. A series circuit of Q3 and resistor R2 is provided. The MO3FET Q2 has its gate supplied with the output signal of the AND gate circuit G2. An internal chip selection signal c3 and a refresh control signal REF are supplied to the input of the ant gate circuit G2. The gate of the MO3FET Q3 is supplied with an output signal from an enable circuit, which will be described next.

A high level or low level electric signal is formed from the connection point between the fuse means F2 and the MOSFET Q2, depending on whether or not the fuse means F2 is disconnected, and is transmitted to the input of the inverter circuit N2.

Although not particularly limited, a type of latch circuit is constructed by providing a MOSFET Q4 that receives the output signal of the inverter circuit N2 between the input terminal of the inverter circuit 111N20 and the ground potential point of the circuit.

The defective address signal obtained from the inverter circuit N2 is supplied to one input of an exclusive OR circuit EXI as a coincidence detection circuit. A corresponding address signal aO is supplied to the other input of this exclusive OR circuit EXI. Thereby, a comparison between the defective address signal and the address signal aO supplied by memory access is performed to detect a match.

Other defective address storage circuits, readout circuits, and coincidence detection circuits shown as examples also include fuse means F3, AND gate circuit G3, and MO5FETQ5 similar to those described above.
~Q7, a resistor R3, an inverter circuit N3, and an exclusive OR circuit EX2. However, the most significant bit address signal an is supplied to the exclusive OR circuit EX2. The fuse means F3 is selectively disconnected in accordance with the defective address corresponding to this bit.

Coincidence detection outputs formed through a total of n+1 circuits similar to the above are supplied to a NOR gate circuit G4, although this is not particularly limited. This NOR gate circuit G4 is also supplied with an output signal φr from an enable circuit, which will be described next.

By not cutting its fuse means F1, the enable circuit enables the memory arrays M-ARY1, M-ARY
This is to prevent address switching as described above from occurring when there is no defect in the address. The fuse means F
1, one end of the fuse means F1 is coupled to the power supply voltage Vcc, and a similar chip selection signal c3 as described above is connected between the other end and the ground potential point of the circuit. MOSFET Ql controlled by the output of AND gate circuit G1 receiving refresh signal REF
and a current limiting resistor R1 are provided in series. The signal φr at the connection point between the fuse means F1 and the MOSFET Ql is connected to the inverter circuit N1 and the feedback MO3FET similar to the above.
MOSFETQ3.Q2 constitutes the storage circuit for the defective address through a launch circuit consisting of MOSFETQ2. This will be communicated to the Q6 gate. Further, the signal φr is the gate circuit G4.
is transmitted as a control signal. Alternatively, the output signal of the inverter circuit N1 may be inverted by an inverter circuit and supplied to the gate circuit G4.

As a result, for example, when the fuse means F1 is not cut, the signal φr is set to a high level. In response, the output signal through the inverter circuit N1 is set to low level, so that the MOSFET Q3. Q4
etc. are turned off. Furthermore, due to the high level of the signal φr, the output signal ac of the NOR gate circuit G4 is fixed at a low level, thereby prohibiting switching to the spare memory array.

When repairing a defective bit, the fuse means F1 is cut off. As a result, contrary to the above case, the read operation of the storage circuit of the defective address and the exclusive OR circuit EX1. When a match output is obtained in which the outputs of EX2 and the like are set to a low level, a signal ac instructing switching to the spare memory array is generated from the NOR gate circuit G4.

In this embodiment, in the refresh operation mode in which the refresh signal REF is set to a low level, the output signals of the AND gate circuits 01 to G3 are forcibly set to a low level. This allows MOSFETs Ql, Q2 and Q
5 etc. are turned off, the fuse means F1 to F3
No current flows through. As a result, in the refresh operation mode in which column-related selection operations are not performed,
Since no current flows through the fuse means, power consumption can be reduced.

Note that in the normal write/read operation mode, both the internal chip selection signal c3 and the refresh signal REF are set to high level, so the AND gate circuit G
The outputs of I to G3 are set to high level. Accordingly M
OSFETs Ql, Q2 and Q5 etc. are put into the secondary on state,
If the output signal from the enable circuit is at a high level, it will be read.

〔effect〕

In the refresh operation mode, the control signal interrupts the read current path of the fuse means for storing defective addresses in the column system, thereby preventing the flow of invalid current unrelated to the refresh operation. This provides the effect of reducing power consumption during refresh operations.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. For example, in the case of a RAM, numerous embodiments can be adopted, such as one in which writing or reading is performed in units of 4 bits or 1 bit.

Further, the specific circuit configuration of each circuit block of the dynamic RAM can take various embodiments.For example, the address signal supplied from the external terminal is
The row address signal and the column address signal may be supplied from a common external terminal in synchronization with the strobe signals RAS and CAS in a time-division manner. In this case, the refresh activation signal may be generated by setting the column address strobe signal CAS to a low level prior to the row address strobe signal RAS. In this case, the read current path of the fuse means for storing the column-system defective address may be cut off in accordance with the activation signal.

[Application field]

Although the invention made by the present inventor is applied to a dynamic RAM (*biased vertical RAM), which is the foreground field of application, the invention is not limited to this; for example, as described above. It can be widely used in static RAM that employs a defect relief method.

[Brief explanation of the drawing]

FIG. 1 is an internal configuration block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the main part of the address conveyor. M-ARYI, M-ARY2...Memory array, SAI
, SA2... sense amplifier, R-ADB... row address buffer, c-swi, c-sw2... column switch, C-ADB... column address buffer, R-DC
R...Row address decoder, C-DCRI, C-DC
R2...Column address decoder, MAI, MA2...
Main amplifier, TG...internal control signal generation circuit, ATD
・・Address signal change detection circuit, Ilo・・Input/output circuit, AC・・Address conveyor, REFC・・Auto refresh circuit Fig. 1 C^0 00~O7 Fig. 2

Claims (1)

[Claims] 1. A defective address storage circuit that includes fuse means that is selectively cut in accordance with a column-system defective address signal and whose reading is prohibited in a refresh operation mode, and a device that detects access to this defective address. A dynamic RAM characterized by having a built-in redundant circuit that switches to a spare memory array. 2. The defective address storage circuit is a MOS that is unconditionally turned off in the refresh operation mode by an output signal of a logic gate circuit that receives a refresh control signal and a substantial chip selection signal supplied from an external terminal.
2. The dynamic RAM according to claim 1, wherein the FET is inserted in series with the fuse means.