JPH07240469A - Bipolar logic - Google Patents

Abstract

PURPOSE:To suppress potential rise clue to the wiring resistance by dividing the injector electrode supply source for an IIL element thereby decreasing the number of elements per current source. CONSTITUTION:The resistances of wiring 15 for an injector 5, produced through a feeder pad 14 and a resistor 16, are connected in parallel and an IIL element is interposed between respective wiring resistances thus arranging the injectors 5. The resistance is generally designed at a low value R and a current is fed while patterning 16 the wiring to have a resistance of 2R or above. Consequently, a plurality of power supplies are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar logic, and more particularly, it is suitable for improving a bipolar logic using an IIL (Integrated Injection Logic) element.

[0002]

2. Description of the Related Art A bipolar logic device using a bipolar element, especially IIL will be described with reference to the plan view of FIG. 6 and its equivalent circuit diagram of FIG.

For example, in order to monolithically build a logic circuit in a silicon semiconductor substrate by IIL, resistors 51 and II are connected to a pad 50 electrically connected to an external electronic device.
A method is employed in which the L injectors 52 are electrically connected in this order by wires 53.

The resistor 51 determines the voltage of the injector 52, and is constructed by providing a diffusion region in the silicon semiconductor substrate or after coating a predetermined place of an oxide covering the surface of the silicon semiconductor substrate with polycrystalline silicon. A method is adopted in which most of the side surface and the polycrystalline silicon surface are covered with an insulator and the wiring is fixed to the exposed portion.

An IIL forming a logic circuit is composed of an injector and a gate region, and an IIL element having 20 or more gates is used to form an integrated circuit. The x mark in the figure is a contact region.

As shown in FIG. 7, a common injector 52
The gate region 53 is electrically connected to the resistor 51 and each injector 52 with the contact 5 interposed therebetween.
4 is installed to form a logic circuit.

A circuit diagram of the logic circuit of FIG. 6 is shown in FIG. 7. In the figure, a wiring resistance r is generated in the wiring 53 between the injectors 52.

That is, the current capacity of the wiring 53 functioning as a current supply source for the injector 52 is determined by its cross-sectional area, and the potential of the wiring 53 for the multistage injector 52 rises. As a countermeasure for the logic having a large number of IIL elements, it is common to increase the thickness of the wiring or limit the number of IIL elements per wiring 53.

[0009]

In the bipolar logic having a large number of IIL elements, the current supply amount due to the wiring cross-sectional area may cause malfunction because the injector current is not supplied to all the injectors 52 due to wiring resistance or the like. Increasing the width of the wiring, which is one of the measures as described above, results in increasing the size of the semiconductor chip, and it is completely opposite in the bipolar logic because compactness is desired.

The present invention has been made in view of the above circumstances, and in particular, by dividing the injector current supply source of the IIL, the number of elements per current source is reduced and the potential rise due to the wiring resistance is suppressed.

[0011]

A pad that can be connected to the outside, a wiring that forms a closed loop branched from this pad, and a plurality of injectors of resistors and IIL elements that are electrically connected to the branched wiring. The bipolar logic of the present invention is characterized in that each of the injectors is provided with a gate region which is continuous and integrated, and the wiring resistance connected to the injector at the final stage is made smaller than the resistance that determines the voltage of the injector. is there.

[0012]

In order to parallelize the wiring resistance of the power supply pad and the injector generated by passing through the resistance, the wiring is branched from the pad to form a closed loop. Moreover, a resistor and an injector of an IIL element are electrically connected to the branched wirings, respectively, and since the designed value R of the resistance is generally low, a resistor of 2R or more is arranged in the branched wiring.

Since the resistance of the wiring connecting the plurality of injectors of the IIL element electrically connected to the wiring thus parallelized is also suppressed by being parallelized, an unnecessary potential rise is suppressed. The operation of the bipolar logic having a plurality of IIL elements is stable.

[0014]

Embodiments of the present invention will be described with reference to FIGS. 1 is a sectional view of the IIL element, FIG. 2 is an equivalent circuit diagram of FIG. 1, FIGS. 3 to 5 are plan views of a bipolar logic using the IIL, and FIG. 5 is a circuit diagram of FIG.

That is, as is apparent from FIG. 1, in the IIL element, an n ⁺ region (later embedded region) is formed from the surface portion of the p-type silicon semiconductor substrate 1 toward the inside by an impurity diffusion process using a photolithography method. Functioning as a) 2 is formed, an n-type epitaxial layer 3 is deposited. Then n
An npn vertical transistor and a pnp injector 5 are formed in the island region obtained by the p type isolation region 4 formed in the epitaxial layer 3 of the type to form an IIL element.

The so-called deep n ⁺ region 6 formed from the surface of the n-type epitaxial layer 3 toward the inside is electrically connected to the buried region 2 by diffusion, and the electrode 7 placed there is for an npn-type vertical transistor. It functions as a collector electrode.

From the other surface portion of the n-type epitaxial layer 3, B or the like is introduced and diffused inward so that the surface concentration is 10
A base region 8 of ^{1 7} 10 ¹⁸ atoms / cm ³ is formed, and phosphorus or arsenic is introduced and diffused therein to have a surface concentration of 10 ²⁰
Npn-type vertical transient scan is obtained by forming an n ⁺ emitter region 9 10 ^{2 1} atoms / cm ^3.

The p-type injector 5 is usually formed at the same time as the formation of the p base region 8, and the surface concentration thereof is almost the same. Prior to forming each region, the thermal oxide film pattern 10 covering the surface of the n-type epitaxial layer 3 is formed.
Is patterned by using the lithography method. Further, Al or Al alloy (Al—Si Al—Si—Cu) is formed in each region in a stacked manner and used as the emitter electrode 11, the base electrode 12, the collector electrode 7 and the injector electrode 13.

In the bipolar logic using the IIL element having such a structure, the npn vertical transistor functions as a gate, the collector electrode 11 thereof functions as an output terminal, the base electrode 12 functions as an input terminal, and the emitter electrode 7 functions as a ground terminal. To do. This npn-type vertical transistor is hereinafter referred to as a gate region.

Further, as shown in the equivalent circuit diagram of FIG. 2, an npn type vertical transistor which functions as a gate region, and a p type injector 5 in the n type epitaxial layer 3 portion.
A pnp-type lateral transistor is provided, a p-base region 8 functioning as a collector region of the pnp-type lateral transistor is grounded from the buried region 2 through the deep n ⁺ region 6, and the p-type injector 5 is a pnp-type lateral transistor Work as an emitter.

The bipolar logic of the present invention using such an IIL element has the structure shown in FIGS. That is, for example, a wiring 14 electrically connected to a so-called pad 14 provided on the P-type silicon semiconductor substrate 1 and made of the same material as each electrode of the IIL element is branched in parallel and has a closed loop structure. A resistor 16 having a doubled resistance value 2R, for example, is formed on each of the wirings 15 branched in parallel. This utilizes polycrystalline silicon or diffused impurity regions. Further, as is apparent from FIG. 3, the wiring 15 is electrically connected to the injector electrode 13 of the injector 5 of the IIL element.

The p-base region 8, the emitter region 9, the emitter electrode 11 and the base electrode 12 of the npn vertical transistor forming the gate region of the IIL element indispensable to the bipolar logic circuit are partially shown in the plan view of FIG. However, it is omitted in FIG.

Since the current amplification factor β is not large in the IIL element shown in FIG. 1, the current injected into the injector 5 is
It is inevitably consumed by the npn transistor which is the gate portion, and operates like a wiring resistance. For this reason, in the conventional technique, the phenomenon in which the necessary current cannot be injected into the plurality of injectors 5 has occurred as described above. Therefore, this phenomenon becomes more severe as the number of injectors 5 increases. It is additionally noted that the wiring resistance in the present invention includes the resistance due to the parasitic capacitance inside the injector 5.

In the bipolar logic circuit shown in FIG.
This is an example in which four injectors 5 are electrically connected to the branched wiring 15, and the connection terminal A at the final stage and the other wiring 1
The connecting end B of 5'is electrically connected to the wiring 15 "to form a closed loop, and the circuit diagram is shown in Fig. 5. As is apparent from this equivalent circuit diagram, the resistor 16 having a double resistance value 2R is used. The resistance generated by the wiring 15 and the wiring 15 'connecting the respective injectors 5, which follows, is about half that of r, which is smaller.

4 shows an example in which a closed loop structure is composed of three branched wires 15, 15 ', 15 "and 15 ⁿ . In this example, the number of gates of the IIL is increased, but the resistance value is three times as large. The wiring resistance at the final stage of the injector 5, which is provided with the resistor 17 having 3R and is electrically connected subsequently, is about 1/3 r. A predetermined voltage is applied to the injector 5 in FIGS. Output from the pad Fig. 5 clarifies the equivalent circuit diagram of the bipolar logic circuit of Fig. 3.

As described above, the plurality of injectors 5 in the bipolar logic according to the present invention are arranged in parallel and are electrically connected by the closed loop wiring 15 and also electrically connected to the pad.

For this reason, the wiring resistance of the plurality of injectors 5 is at the lowest position in almost half of the wiring corresponding to the number, so that the required current value is also supplied to the injector 5 at the final stage. This is the same in FIGS. 3 and 4, of course, and it should be noted that the number of wirings branched to the outside is four and the resistance can be an integral multiple, such as 4R having a resistance value four times larger. In addition, in the figure, a cross indicates a contact region.

[0028]

The bipolar logic according to the present invention stabilizes the bipolar logic by suppressing the wiring resistance of the injector and reducing unnecessary voltage drop (potential increase) without increasing the semiconductor chip area. Works. or,
Since the width of the wiring for the injector can be made narrower than in the conventional case, the area of the semiconductor chip (substrate) can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an IIL element used in the present invention.

FIG. 2 is an equivalent circuit diagram of FIG.

FIG. 3 is a plan view of an IIL element used in the present invention.

FIG. 4 is a plan view of another IIL element used in the present invention.

5 is an equivalent circuit diagram of the IIL element of FIG.

FIG. 6 is a plan view of a conventional IIL element.

FIG. 7 is an equivalent circuit diagram of FIG.

[Explanation of symbols]

50, 14: Pad, 51, 16: Resistance, 52, 5: Injector, 53, 15, 15 ', 15 ": Wiring, 1: Semiconductor substrate, 2: n ⁺ buried region, 3: Epitaxial layer, 4: Separation region, 6: Deep n ⁺ region, 7: Collector electrode, 8: Base region, 9: Emitter region, 10: Thermal oxide film, 11: Base electrode, 12: Emitter electrode, 13: Injector electrode.

Claims (1)

[Claims] 1. A pad that can be connected to the outside, a wiring that forms a closed loop branched from this pad, a plurality of injectors of resistors and IIL elements that are electrically connected to this branched wiring, and each of these. A bipolar logic having an injector and a continuous gate region, and making a wiring resistance connected to the injector at the final stage smaller than the resistance for determining the voltage of the injector.