KR100188106B1 - Integrated injection logic - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated implantation logic, comprising an N-type buried layer formed on a P-type semiconductor substrate, an N-type epitaxial layer formed thereon, a P region formed thereon, and an N ⁺ region formed therein The N ⁺ sink region surrounding the P region is in contact with the buried layer. This eliminates the additional process of forming the bottom layer while forming with a high voltage analog fixture. And, by improving the up-beta, it is possible to overcome the limitation of the number of output terminals.

Description

Direct injection logic

1 (a) is a cross-sectional view of an integrated implantation logic cell according to the prior art,

FIG. 1B is an equivalent circuit diagram of the integrated injection logic of FIG.

2 (a) and (b) are a layout view and a cross-sectional view of a conventional integrated injection logic,

3 (a) and (b) are cross-sectional views and other equivalent circuit diagrams of another integrated injection logic cell according to the prior art,

4 is a cross-sectional view of an integrated implantation logic cell according to the prior art,

5 is a cross-sectional view and an equivalent circuit diagram of an integrated logic circuit according to an embodiment of the present invention.

6 is a graph illustrating up-beta characteristics of an integrated logic circuit according to an exemplary embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1 substrate 2 epi layer

3, 4: P area 5, 6, 7, 8: N ⁺ area

10: sink area 11: substrate

10; Sink Zone 20: Isolation Zone

30: investment layer 40: bottom layer

The present invention relates to intergrated injection logic (I ² L).

Integrated injection logic or merged transistor logic (MTL) is one of the bipolar device structures used in digital logic and is used in applications where power consumption should be small.

Then, the conventional integrated injection logic will be described in detail with reference to the accompanying drawings.

1 (a) and (b) show a conventional integrated implantation logic cell, where (a) is a sectional view and (b) is an equivalent circuit diagram thereof.

The structure of the integrated injection logic cell shown in FIG. 1 (a) is as follows.

An N-type epitaxial layer 2 is formed on the high concentration N-type substrate 1, and the first P region 3 and the second P region 4 are formed in the epitaxial layer 2, and the second P region 4 is formed. ), An N ⁺ region 5 is formed. Here, the second P region 4 is connected to the input terminal IN, the N ⁺ region 5 is connected to the output terminal OUT, and the current I is supplied to the first P region 3. .

This structure can be viewed as a combination of a horizontal PNP transistor and a vertical NPN transistor. The horizontal PNP transistor has an emitter of the second P region 5, an N-type EPE layer 2 as a base, and a first P region ( 3) is used as a collector, and the vertical NPN transistor uses an N-type Epee layer 2 as an emitter, a first P region 3 as a base, and an N ⁺ region 4 as a collector. Here, the vertical NPN transistor is an inverted structure in which the emitter is underneath the base, and the emitter is not only common with the base of the horizontal PNP transistor, but also the collector of the horizontal PNP transistor is equal to the base of the vertical NPN transistor. same. Thus, these two transistors are said to be integrated into an integrated circuit, also referred to as merge transistor logic.

Therefore, the equivalent circuit of this structure is as shown in FIG.

In FIG. 1B, the collector of the PNP transistor Q1 is connected to the base and the input terminal IN of the NPN transistor Q2, and the base of the PNP transistor Q1 and the emitter of the NPN transistor Q2 are grounded. It is. The collector of the NPN transistor Q2 is connected to the output terminal OUT and the current is supplied to the emitter of the PNP transistor Q1.

On the other hand, since the logic array is made up of these cells, the input terminal IN of this cell is connected to the output terminal of the preceding cell, and the output becomes the input of another cell. The PNP transistor Q1 becomes a current source for supplying the base current of the NPN transistor Q2, and the input terminal IN can be used to short this current to ground.

In this integrated injection logic, when the input is open, NPN transistor Q2 is saturated by the current source, and the output voltage at this time is within 100mV as a small saturation voltage across NPN transistor Q2. In contrast, when the input terminal is blocked, the NPN transistor Q2 is turned off.

These integrated injection logic cells are gathered together to form a logic array, in which multiple collectors are formed on the NPN transistors of one cell to reduce the area occupied by the device.

This will be described in detail with reference to FIGS. 2A and 2B.

2 (a) and (b) show a structure in which integrated injection logic with multiple collectors is integrated, (a) is a layout view, and (b) is a cross-sectional view of (a).

One first P region 3 is linearly formed in the N-type epitaxial layer 2, and the second P region 4 has three N ⁺ regions 6, 7, 8 formed on both sides thereof. There are many formation doors, and the code | symbol 9 has shown the low demand. Therefore, it can be seen that the PNP transistor is connected to a plurality of NPN transistors having multiple collectors.

Here, the first P region 3, which is the emitter of the PNP transistor as the current source, is used to drive a plurality of NPN transistors. When the first P region 3, which is a current source, is divided in this way, the degree of integration may be increased and the current may be uniformly distributed to various places.

This structure uses a current source transistor, which eliminates the need for many biasing resistors, resulting in significant space savings, resulting in an entire cell about the size of one integrated transistor and very small power consumption.

Another advantage of integrated implantation logic is that different types of bipolar elements can be mounted on the same chip.

On the other hand, Isoplanar or isolation techniques can be introduced to reduce parasitic transistor behavior in integrated implantation logic. This will be described in detail with reference to FIGS. 3 (a) and (b).

FIG. 3A is a cross-sectional view of the integrated injection logic that forms the isolation region, and FIG. 3B is an equivalent circuit diagram thereof.

As can be seen in FIG. 3 (a), sink regions 10 are formed on both sides of the conventional integrated injection logic cell having multiple N ⁺ regions 6, 7, 8. The isolation region 10 is in contact with the substrate 1 as an N ⁺ type diffusion region.

Meanwhile, three N ⁺ regions 6, 7 and 8, which are collectors of the NPN transistor, are connected to the output terminals OUT1, OUT2, and OUT3, respectively, and a resistor R is connected in series to the first P region 3. It is.

However, in order to form the integrated logic circuit as described above in a high voltage analog process using a P type substrate, an additional process of separately forming a buried layer and a bottom layer is required. This will be described in detail with reference to FIG. 4.

Buried layer 30 of N ⁺ type on the P-type substrate 11 is formed and there is a bottom layer 40 of N ⁺ type is formed thereon. Next to the buried layer 30 and the bottom layer 40, a P ⁺ type isolation region 20 in contact with the substrate 11 is formed. The structure on the bottom layer 40 is the same as the structure on the substrate 1 in FIG. However, in the structure of FIG. 3 (a), the collector current of the NPN transistor is flowed through the grounded substrate 1, but in this structure, the sink region 10 and the isolation region 30 are grounded to thereby ground the NPN transistor. Flow the current collector.

However, in the integrated injection logic of such a structure, the depth of the epi layer 2 must be deep, and the effective epi layer depth is also deep in order to secure the breakdown voltage of the NPN or PNP transistor.

In addition, since the integrated injection logic is constructed by applying the inverted structure of the transistor, the effective epitaxial depth determines the magnitude of the current gain, which has a structure directly connected to the number of output terminals of the logic.

However, in this structure, since the up-beta is limited to βu of βu ≦ 5, the number of output terminals is limited to five or less in the same region separated by the isolation region 20.

The present invention has been made to solve this problem, by using an additional process to form the bottom layer in the high-voltage analog process is formed to be independent of the effective epi layer depth to improve the up-beta and thus to increase the number of output terminals The purpose is to.

Integrated injection logic according to the present invention for achieving this object is,

A first conductive semiconductor substrate,

A second conductive buried layer formed on the substrate,

A second conductive epitaxial layer formed on the buried layer,

A first conductivity type region in which the epi layer is formed,

A second conductive region formed in the second conductive region,

A second conductive sink region surrounding the first conductive region and in contact with the buried layer

It includes.

Here, the second conductive region may be three or more, and the sink region is preferably grounded.

On the other hand, it may further include an isolation region of the second conductivity type surrounding the sink region, wherein the isolation region is preferably in contact with the substrate, it is preferable that the sink region and the isolation region is grounded.

The buried layer, the second conductivity type region and the sink region are preferably higher in concentration than the epi layer.

In addition, an inverter, a latch, and various flip-flops may be implemented using this structure.

In the intellectual implantation logic according to the present invention thus formed, an additional step of forming a bottom layer while forming by a high pressure analog process is unnecessary. And, by improving the up-beta, it is possible to overcome the limitation of the number of output terminals.

Next, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

FIG. 5A is a cross-sectional view of an integrated injection logic according to an embodiment of the present invention, FIG. 5B is an equivalent time, and FIG. 6 is an upstream view of an integrated injection logic circuit manufactured according to this embodiment. A graph showing the beta characteristics.

As shown in FIG. 5A, in the integrated injection logic according to the embodiment of the present invention, the bottom layer does not exist, and the epi layer 2 is formed directly on the N ⁺ buried layer 30. The first P region, which is an emitter of the balanced PNP transistor, is omitted.

This is explained in more detail.

An N ⁺ -type buried layer 30 is formed on the P-type substrate 11, and a P ⁺ -type isolation region 20 in contact with the substrate 11 is formed next to the buried layer 30. An N-type epitaxial layer 2 is formed on the buried layer 30, and one P region 4 is formed in the epitaxial layer 2, and the N ⁺ region 5 is formed in the P region 4. Is formed. The end of the buried layer 30 is in contact with the N ⁺ type sink region 10 surrounding the P region 4. Here, the P region 4 is connected to the base terminal B, the N ⁺ region 5 is connected to the collector terminal C, and is isolated from the sink region 10 corresponding to the emitter of the NPN transistor. Region 20 is grounded. Here, the connection layer 10 ′ connecting the sink region 10 to the ground may be formed on the sink region 10.

An equivalent circuit diagram of the integrated injection logic according to the present embodiment is shown in FIG. 5 (b), where the current supplied to the P region 4, that is, the base of the NPN transistor, is supplied to the PNP transistor current source I _INJ . R _{B corresponds} to the NPN transistor Q2 base resistance.

In the present embodiment, a structure in which only one collector of the N ⁺ region, that is, the NPN transistor is formed, is provided. However, several N ⁺ type regions may be formed.

The up-beta characteristic of the integrated injection logic according to the present invention is shown in FIG.

This graph is for the integrated injection logic with three collectors, the horizontal axis represents the collector current (IC), and the vertical axis represents the up-beta (). The up-beta value is greater than 25 depending on the collector current. It can be seen that the up-beta value can be improved and obtained with sufficient magnitude.

In the direct injection logic according to the present invention thus formed, there is no need for an additional step of forming the bottom layer while forming in a high pressure analog process. And, by improving the up-beta, it is possible to overcome the limitation of the number of output terminals. Using such a structure, an inverter, a latch, and various flip-flops can be implemented.

Claims (10)

A first conductive semiconductor substrate, a second conductive buried layer formed on the substrate, a second conductive epitaxial layer formed directly on the buried layer, a first conductive type first region formed on the epitaxial layer, And a second conductive type second area formed in the first area, and a second conductive type sink area surrounding the first area and in contact with the buried layer. 2. The direct injection logic of claim 1, wherein the second region is at least three. 2. The direct injection logic of claim 1 wherein the sink region is grounded. The logic of claim 1, further comprising an isolation region of a second conductivity type surrounding the sink region. The logic of claim 4, wherein the isolation region is in contact with the substrate. 5. The integrated implantation logic of claim 4, wherein the sink region and the isolation region are grounded. The logic of claim 1, wherein the buried layer is higher in concentration than the epi layer. The logic of claim 1, wherein the second region is denser than the epi layer. The logic of claim 1, wherein the sink region is of higher performance than the epi layer. The logic of claim 1, further comprising a second conductive connection layer connecting the sink region and the outside.