RU2094910C1 - Complementary bipolar nand circuit (options) - Google Patents

Abstract

FIELD: microelectronics; manufacture of combined logic superlarge-scale CMOS integrated circuits of superlow power requirement. SUBSTANCE: complementary bipolar NAND gate which is functional integrated circuit compatible with CMOS technology has newly introduced first and second p-n-p loading transistors whose bases are combined and connected to circuit output with the result that p-n-p loading transistors function at cut-off barrier and do not consume current from power supply when at least one of circuit inputs is placed at logical 0 voltage. Proposed circuit uses functional integration of semiconductor regions of all circuit transistors and standard CMOS technology for its manufacture. Low-resistance n+ substrate is introduced to reduce current gain of parasitic p-n-p transistor and parasitic resistance Rx of n substrate. Circuit is set up on insulating substrate which eliminates P+ regions around it causing parasitic current leakage and stray capacitances as well as volumetric and surface regions wherein charge carrier generation caused by radiation may develop. EFFECT: reduced power requirement, facilitated manufacture and reduced cost, reduced parasitic effect of "latching", improved speed and radiation resistance. 3 cl, 4 dwg

Description

 The invention relates to microelectronics and can be used to create structures of logical combined Bi-CMOS ultra-large integrated circuits (VLSI) with ultra-low power consumption.

 There is a known transistor-transistor logic circuit with injection power and an NAND element containing a multi-emitter npn transistor, a switching circuit and an injection pnp transistor, the emitter of which is connected to a power source, and the collector and base, respectively, with the base and collector of the multi-emitter transistor (ed. St. USSR N 1128387, CL H 03 K 19/088, 1984).

 The disadvantage of this scheme is the high power consumption.

 The closest technical solution to the proposed circuit is a transistor-transistor logic circuit with injection power (ed. St. USSR N 1744738А 1, class N 01 L 27/04, 1990), containing multi-emitter and switching npn transistors and a metallized connection between the collector of a multi-emitter and base switching npn transistors.

 The disadvantage of this scheme is the relatively large power consumption.

The closest constructive solution to the complementary I-NOT bipolar scheme is an I-NOT injection element (ed. St. USSR N 1744738А 1, class H 01 L 27/04, 1990) containing a p ⁺ substrate to which a metallized electrode is connected nutrition. The emitters injecting the first and additional pnp transistors are combined in the substrate. In the first n _ep1 epitaxial region, the collector of a multi-emitter npn transistor and the base of the first injecting pnp transistor are combined. In the second n _ep2 epitaxial region, the base of the second injecting pnp transistor and the emitter of the switching npn transistor are combined; an electrode of a common bus is connected to the same region through a deep diffusion podkontaktnoy n ⁺ -region. Above the region n _{ep1, there} is a third p _ep1 epitaxial region of the first type of conductivity, in which the base of the multi-emitter npn transistor and the collector of the first injecting pnp transistor are combined. Region p _ep1 contains diffusion regions n ₁ and n ₂ , which are emitters of a multi-emitter transistor to which input electrodes are connected. Above the region of n _ep2 is the fourth p _ep2 epitaxial of the first type of conductivity. In the region p _{ep2, the} base of the switching npn transistor and the collector of the additional second injecting pnp transistor are combined. The region p _ep2 contains n the region to which the output electrode is connected, and the diffusion contact region p $\genfrac{}{}{0ex}{}{\text{+}}{\text{2}}$ . To region p $\genfrac{}{}{0ex}{}{\text{+}}{\text{2}}$ connected metallized conductor connecting the base of the switching npn transistor and the collector of a multi-emitter npn transistor.

 The disadvantage of this design solution is the complexity of manufacturing, requiring the creation of two epitaxial layers.

 The present invention is based on the task of developing a complementary bipolar circuit of an AND-NOT functionally integrated circuit with lower power consumption and the task of simplifying manufacturing technology to a standard CMOS process.

 The tasks are solved as follows.

1. A complementary bipolar NAND circuit containing a substrate, n- and p-regions formed in the substrate, input and output metal electrodes, a metal power electrode and a common bus electrode, contains a substrate made of n-type silicon material, formed therein the n ⁺ region connected to the output metal electrode, a closed insulating p ⁺ region connected to the common bus electrode, and the first, second, third p-regions, the first p-region being an injector located between the second and third p- areas of and connected to a metal power electrode, one collector n ⁺ region and at least two emitter n ⁺ regions, to which input metal electrodes are connected, are formed in the second p-region, a p ⁺ region connected by a metal electrode is formed in the third p-region with a collector n ⁺ region located in the second p-region and an n ⁺ region that is connected to the common bus electrode, the technical result is achieved by simplifying the manufacturing technology to the standard CMOS technology and its variants.

2. A complementary bipolar NAND circuit containing a substrate, n- and p-regions formed in the substrate, input and output metal electrodes, a metal supply electrode and a common bus electrode, contains a substrate made of a low resistance n ⁺ type material on which a high-resistance n-type epitaxial region is located in which an n ⁺ region is formed, connected to the output metal electrode, a closed insulating p ⁺ region, connected to the common bus electrode, and the first, second, third p-regions, the first p-region b, which is an injector, located between the second and third p-regions and connected to a metal power electrode, in the second p-region one collector n ⁺ region and at least two emitter n ⁺ regions, to which the input metal electrodes are connected, are formed in the third p-region, a p ⁺ region is formed, connected by a metal electrode to a collector n ⁺ region located in the second p-region, and an n ⁺ region, which is connected to the common bus electrode, which weakens the parasitic “snap” effect.

3. A complementary bipolar NAND circuit containing a substrate, n- and p-regions formed in the substrate, input and output metal electrodes, a metal supply electrode and a common bus electrode, contains a substrate made of an insulating material on which a single-crystal high-resistance layer is located n-type, wherein the formed n ⁺ -region coupled to the output electrode metal and the first, second, third p-region, wherein the first p-region, which injector is arranged between the second and third p-regions and Keys to supply metallic electrode, a second p-region formed by a n ⁺ -region collector and emitter of at least two n ⁺ type regions, which are connected to metal input electrodes of the third p-region formed by p ⁺ -region coupled to the metal electrode a collector n ⁺ region located in the second p-region and an n ⁺ region that is connected to the common bus electrode, the following technical effect is achieved: the parasitic “snapping” effect and leakage currents are eliminated, and the parasitic ones are reduced bones, increase speed, noise immunity and radiation resistance.

 The I-NOT complementary bipolar circuit, which is a functionally integrated circuit compatible with CMOS technology, has a lower power consumption compared to the prototype, which is ensured by the following essential features: the first and second load pnp transistors are introduced, their bases are combined and connected to the circuit output As a result, load pnp transistors operate at the locking boundary and do not consume current from the power source when a logic zero voltage is applied to at least one of the circuit inputs.

 Simplification and cheaper technology is achieved through the use of functional integration of the semiconductor regions of all transistors of the circuit and the standard CMOS process for manufacturing the proposed circuit.

The parasitic “snapping” effect is weakened by introducing a low-resistance n ⁺ substrate into the circuit design, as a result, the current gain of the parasitic pnp transistor decreases and the parasitic resistance of the n-substrate R _x decreases [1]
Elimination of spurious effects of “snapping-in” and leakage currents, reduction of spurious capacitances, increased speed and radiation resistance are achieved by placing the circuit design on an insulating substrate, as a result, insulating deep bordering p ⁺ -region circuits having parasitic leakage currents and capacities, as well as bulk and surface regions where carrier generation can develop due to radiation.

 The technical result that can be obtained by carrying out the invention is that the proposed design has less power consumption and more simplified and cheapened manufacturing technology.

 In FIG. 1 shows the design of a complementary bipolar I-NOT circuit, a functionally integrated circuit compatible with standard CMOS technology; in FIG. 2 design of a complementary bipolar circuit of an AND-NOT functionally integrated circuit compatible with modified CMOS technology; in FIG. 3 design of a complementary bipolar circuit of an AND-NOT functionally integrated circuit compatible with the silicon-on-insulator CMOS technology; in FIG. 4 schematic diagram of a complementary bipolar circuit AND NOT.

, к подложке 1 подключен через n⁺-область 3 выходной металлизированный электрод 4. В подложке 1 совмещены базы нагрузочных p-n-p транзисторов 24, 25 и коллектор переключательного n-p-n n-транзистора 23, а замкнутая изолирующая область 2, базовая область 5 многоэмиттерного горизонтального n-p-n транзистора, базовая область 6 переключательного n-p-n транзистора и p-область 7 совмещенных эмиттеров нагрузочных горизонтальных p-n-p транзисторов выполняются одновременно в ходе технологического процесса и имеют концентрацию примеси (1-5) • 10¹⁶см^-3. К области 7 совмещенных эмиттеров нагрузочных p-n-p транзисторов подключен металлизированный электрод питания 8. В базовой области 5 многоэмиттерного транзистора содержатся эмиттерные n⁺-области 9, 10 и коллекторная n⁺-область 11 с концентрацией 1 • 10²⁰см^-3, совмещены база многоэмиттерного n-p-n и коллектор первого нагрузочного p-n-p транзисторов. К эмиттерным n⁺-областям 9, 10 подключены металлизированные входные электроды 12, 13. В базовой p-области 6 переключательного n-p-n транзистора содержатся эмиттерная n⁺-область 14 с концентрацией доноров 1 • 10²⁰см^-3, совмещены база переключательного n-p-n и коллектор второго нагрузочного p-n-p транзисторов, подконтактная p⁺-область 15 с концентрацией акцепторов 1 • 10²⁰см^-3 соединена металлизированным проводником 16 с n⁺-коллекторной областью многоэмиттерного транзистора. К эмиттерной n⁺-области 14 подключен металлизированный электрод общей шины 17. В p-области 7 совмещены эмиттеры первого и второго нагрузочных p-n-p транзисторов 24, 25.A complementary bipolar circuit AND NOT functional integrated circuit compatible with standard CMOS technology (figure 1), contains a ring insulating p-region 2, which is formed on an n-substrate 1 with a concentration of 1 • 10 ¹⁴ 2 • 10 ¹⁵

, the output metallized electrode 4 is connected to the substrate 1 through the n ⁺ region 3; the bases of the load pnp transistors 24, 25 and the collector of the switching npn n-transistor 23 are combined in the substrate 1, and the closed isolation region 2, the base region 5 of the multi-emitter horizontal npn transistor, the base region 6 of the switching npn transistor and the p-region 7 of the combined emitters of the load horizontal pnp transistors are performed simultaneously during the process and have an impurity concentration of (1-5) • 10 ¹⁶ cm ^-3 . A metallized power electrode 8 is connected to region 7 of the combined emitters of load pnp transistors 8. The base region 5 of the multi-emitter transistor contains emitter n ⁺ regions 9, 10 and collector n ⁺ region 11 with a concentration of 1 • 10 ²⁰ cm ^-3 , and the base of the multi-emitter npn is combined and the collector of the first load pnp transistors. Metallized input electrodes 12, 13 are connected to emitter n ⁺ regions 9, 10. The base p-region 6 of the npn switching transistor contains the emitter n ⁺ region 14 with a donor concentration of 1 • 10 ²⁰ cm ^-3 , the switching npn base and the collector are combined of the second load pnp transistor, the contact p ⁺ region 15 with an acceptor concentration of 1 • 10 ²⁰ cm ^{-3 is} connected by a metallized conductor 16 to the n ⁺ collector region of a multi-emitter transistor. A metallized electrode of the common bus 17 is connected to the emitter n ^{+ region} 14. In the p-region 7, the emitters of the first and second pnp load transistors 24, 25 are combined.

область 19 с концентрацией (1-5) • 10¹⁴см^-3.The complementary bipolar scheme AND NOT a functionally integrated circuit compatible with the modified CMOS technology (Fig. 2), which reduces the “latch” effect, contains an n ⁺ substrate 18 with a concentration of 1 • 10 ¹⁹ cm ^-3 , on which the epitaxial

area 19 with a concentration of (1-5) • 10 ¹⁴ cm ^-3 .

 The complementary bipolar circuit is an AND-NOT functionally integrated circuit compatible with the silicon-on-insulator CMOS technology (Fig. 3 contains an insulating substrate 20 on which a region of single-crystal silicon 21 is either grown epitaxially or formed by the SIMOX method. In such structures, formation of parasitic pnpn devices and the “latch” effect are eliminated, and parasitic capacitances and leakage currents are greatly reduced, which leads to an improvement in the speed, noise immunity, and radiation resistance of the circuit.

 On the circuit diagram of a complementary bipolar circuit of an AND-NOT functionally integrated circuit compatible with CMOS technology (Fig. 4) a multi-emitter horizontal npn transistor 22, a vertical npn switching transistor with a normal structure 23, the first horizontal load pnp transistor 24, the second horizontal load pnp transistor 25.

 A complementary bipolar I-NOT scheme works as follows.

To ensure operation, a voltage is applied to p-region 7
E> (1.5-1.7) B
E> u _be23 + u _bk22 + u _ken24 ,
where u _be23 voltage at the open junction 6 14 base emitter switching npn transistor 23;
u _bk22 voltage at the open junction 5 11 base collector of a multi-emitter npn transistor 22;
u _ken24 voltage 5 7 collector emitter saturation of the first load pnp transistor 24.

Mode 1. When at least one input electrode 12 or 13 is supplied with a logic zero voltage of a low voltage level, all transistors are in a half-closed state. At the output of the circuit, the voltage of the logical unit is a high voltage level, determined by the formula
E u _be25 ,
where u _be25 voltage at the half-closed junction base emitter 1 - 7 of the second load pnp transistor.

 Mode 2. When a logic unit voltage is applied to all inputs of the circuit, the multi-emitter n-p-n transistor 22 is open and operates in inverse mode, its transition 5 11, the collector base is biased in the forward direction. The first pnp load transistor 24 is saturated. Carriers are injected from the p-region 7 into the base region 5 of the multi-emitter n-p-n transistor 22. The current from the n collector region 11 is fed through the metallized conductor 16 to the p-base region 6 of the switch n-p-n transistor 23. The second load p-n-p transistor 25 is operating in normal active mode. At the output of a complementary bipolar circuit AND NOT a low voltage level, a logic zero voltage determined by a voltage of 1 14 collector emitter of an open switching n-p-n transistor 23 operating at the saturation boundary.

 From the operating modes it follows that this complementary bipolar circuit and the corresponding structures perform a logical AND-NOT function.

 The design change compared with the prototype is associated with the replacement of the vertical structure of the multi-emitter npn transistor 22 by a horizontal structure, the inverted structure of the switching npn transistor 23 with a normal one, the vertical structure of the load pnp transistors 24 and 25 with a horizontal one, and the base areas of the load pnp transistors 24 and 25 are combined with the collector area switching npn transistor 23.

 Thus, in relation to the prototype, the combination of the base areas of the load pnp transistors 24 and 25 with the collector of the switching npn transistor 23 reduces the power consumed by the circuit, and replacing the vertical structures of the multi-emitter npn transistor 22 and horizontal pnp transistors 24 and 25 with horizontal ones greatly simplifies the manufacturing technology, making compatible with the most common varieties of the CMOS process.

 Complementary bipolar circuits AND NOT functional integrated circuits compatible with CMOS technology, providing lower power consumption and manufactured using a simpler technology, allow you to create combined Bi-CMOS circuits on a single chip, which leads to improved microcircuit parameters and lower microelectronic cost devices.

Literature
1. Muller G. Keymins T. Elements of integrated circuits./ Transl. from English M. Mir, 1989, 630 p.

Claims (3)

1. A complementary bipolar circuit AND NOT containing a substrate, n- and p-regions formed in the substrate, input and output metal electrodes, a metal supply electrode and a common bus electrode, characterized in that the substrate is made of n-type silicon material, in which formed n ⁺ region connected to the output metal electrode, a closed insulating p ⁺ region connected to the common bus electrode, and the first, second and third p-regions, the first p-region being an injector located between the second and third p -regions and is connected to a metal power electrode; in the second p-region, one collector n ⁺ region and at least two emitter n ⁺ regions are formed to which input metal electrodes are connected; in the third p-region, a p ⁺ region connected a metal electrode with a collector n ⁺ region located in the second p-region and an n ⁺ region that is connected to the common bus electrode. 2. A complementary bipolar circuit AND NOT containing a substrate, n- and p-regions formed in the substrate, input and output metal electrodes, a metal power electrode and a common bus electrode, characterized in that the substrate is made of low-resistance n ⁺ -type material, which contains a high-resistance n-type epitaxial region in which an n ⁺ region is formed connected to the output metal electrode, a closed insulating region connected to the common bus electrode, and the first, second and third p-regions, the first The p-region, which is an injector, is located between the second and third p-regions and is connected to a metal power electrode; in the second p-region, one collector n ⁺ region and at least two emitter n ⁺ regions are formed, to which input metal electrodes are connected , in the third p-region, a p ⁺ region is formed, connected by a metal electrode to a collector n ⁺ region located in the second p-region, and an n ⁺ region, which is connected to the common bus electrode. 3. A complementary bipolar circuit AND NOT containing a substrate, n- and p-regions formed in the substrate, input and output metal electrodes, a metal supply electrode and a common bus electrode, characterized in that the substrate is made of an insulating material on which a single-crystal high-resistance n-type layer, wherein the formed n ⁺ -region coupled to the output electrode metal and the first, second and third p-region, wherein the first p-region, which injector is arranged between the second and third p-region styami and connected to the metal electrode of the power in the second p-region formed by a n ⁺ -region collector and emitter of at least two n ⁺ type regions, which are connected to metal input electrodes of the third p-region formed by p ⁺ -region coupled metal an electrode with a collector n ⁺ region located in the second p-region, and an n ⁺ region that is connected to the common bus electrode.

Images