JPH0723939B2 - Smectic electro-optical display - Google Patents

Description

TECHNICAL FIELD The present invention relates to a liquid crystal electro-optical device using a chiral smectic C liquid crystal.

(Prior Art) In recent years, a liquid crystal display panel using a chiral smectic C phase (hereinafter referred to as SmC ^* ) has attracted attention as a display device having high-speed response and memory retention.

As a liquid crystal having this chiral smectic C phase, for example, 2-methylbutyl P-[(Pn-decyloxybenzylidene) amino] is widely known. As shown in FIG. 8, the liquid crystal is arranged in a twisted spiral structure in each of the layers L ₁ , L ₂ , L ₃ ... With a constant azimuth angle.

By the way, this SmC ^* has a spiral pitch (usually several μ
Two substrates with a gap of about 1 μm smaller than m)
When injected between B and B (FIG. 9), the liquid crystal molecules are arranged in a state in which the helical structure disappears and the molecular axis is parallel to the substrate and is inclined by ± θ from the normal direction of the layer.

That is, the liquid crystal injected into the cell has a state in which domains tilted clockwise by an angle θ from the normal to the layer and domains tilted counterclockwise by θ, ie, −θ, coexist as shown in FIG.

By the way, SmC ^* liquid crystal molecules generally have an electric dipole in a direction perpendicular to the molecular axis. When one domain has an electric dipole upward with respect to the cell substrate, the other domain has a downward electric dipole. You will have a child. Therefore, when an electric field is applied between the substrates B and B, the liquid crystal molecules in the substrate are aligned all at a position inclined by + θ or −θ from the normal direction of the layer, and when an electric field in the opposite direction is applied, they are inverted. −
Arrange them in a state where they are all aligned at a tilted position of θ or + θ.

Needless to say, since liquid crystal molecules have deflection characteristics, if the substrate is made of a transparent material and polarizing plates are arranged on both sides, an optical bright state and a dark state occur depending on the arrangement direction of the liquid crystal molecules, so-called liquid crystal display. It can have the function of a panel.

In this way, the liquid crystal panel using SmC ^* liquid crystal has a very fast response speed on the order of microseconds and the great advantage that the display state can be maintained for a long period even if the electric field is removed from the pattern display, but it is not selected. The upper limit of the electric field, the so-called liquid crystal threshold voltage Vth, is 0.5
Since it is very low as V (Fig. 11) and the margin in the non-selected state is small, there is a problem that it is practically impossible to perform the dynamic drive by applying the 1 / N bias method.

(Objective) In view of such problems, an object of the present invention is to provide an SmC ^* liquid crystal display device to which the 1 / N bias method can be practically applied.

That is, the feature of the present invention is that the line-sequential scanning signal is largely divided into two, different states are written in the first half and the latter half, and an alternating voltage equal to or lower than the liquid crystal operating voltage is applied when non-electrodes are selected. is there.

(Structure) Therefore, details of the present invention will be described below based on illustrated embodiments.

FIG. 1 is a liquid crystal display panel according to the present invention using SmC ^* , in which reference numeral 1 is one of the substrates constituting a cell of the liquid crystal panel, a common electrode on the surface of an electrically insulating transparent plate such as glass. .. are provided, a polyimide thin film is formed on the surface by printing or dipping, and a uniaxial alignment film 1b obtained by rubbing in one direction is provided.

Reference numeral 2 is the other substrate constituting the cell, which is formed by providing segment electrodes 2a, 2a ... On the surface of an electrically insulating transparent plate and forming the uniaxial alignment film 2b similar to that described above on the surface. .

Two substrates 1 and 2 which have been subjected to the alignment treatment in this way
Is made to face the orientation faces, SmC ^* are arranged in parallel with a smaller distance d than the helical pitch of the liquid crystal, the gap formed by the two substrates SmC ^* liquid crystal is injected. A liquid crystal panel is constructed by disposing polarizing plates 3 and 4 on the upper and lower substrates with their polarization axes orthogonal to each other and displaying the rotation of liquid crystal molecules in a bright and dark state.

FIG. 2 shows one embodiment of a smectic liquid crystal display device using the above-mentioned liquid crystal panel. In the figure, reference numeral 6 is the above-mentioned liquid crystal display panel, in which the common electrodes and the segment electrodes are driven by common electrodes. Grayscale display can be performed by utilizing the transient response characteristics (FIG. 9) of the liquid crystal molecules formed by connecting the circuit 7 and the segment electrode drive circuit 8.

Next, these drive circuits will be described.

FIG. 3 shows an embodiment of the common electrode drive circuit. In the figure, reference numeral 9 is a shift register for sequentially shifting the frame scanning switching signal by a clock signal synchronized with the common electrode scanning speed. . A latch circuit 10 latches a signal from the shift register 9 in synchronization with a clock signal, and a drive voltage from a drive voltage generation circuit 11 described later via an output gate circuit 12 to common electrodes CM ₁ , CM _2, ...
・ ・ ・ Supply to CMn.

Reference numeral 11 denotes the above-mentioned drive voltage generation circuit, which supplies liquid crystal drive voltages Vap, 2 / 3Vap, 1 / 3Vap and 0 voltage from a power source (not shown) to analog switches such as a transmission gate 11 respectively.
supplied via a, 11b, 11c, 11d, and the liquid crystal drive voltage Vap
And analog switches 11a and 11b which are supplied with 0 voltage
, And the output of the analog switch 11c11d receiving the supply of 2 / 3Vap and 1 / 3Vap as a pair is output to the output gate 12 described later. Reference numeral 13 denotes a drive signal scanning switching signal frequency divider composed of a JK flip-flop, which divides the drive signal into 1/2 and outputs it. Reference numeral 14 denotes an exclusive OR gate, which inputs a drive signal and a 1/2 frequency signal of this signal and outputs a 1/2 frequency signal synchronized with the drive signal. The signal from the exclusive-OR gate 14 is the direct and inverter 15
Is input to the control terminals of the analog switches 11a, 11b and 11c, 11d forming a pair of the drive voltage generation circuit 11, and the drive voltage generation circuit 11 outputs 0 voltage and 2 / 3Vap or Vap and 1 / 3Vap. An output gate 12 is a pair of two analog switches 12a and 12b, each of which receives a voltage supply from the drive voltage generating circuit 11, and one analog switch 12a receives the output signal from the latch circuit 10 directly and the other. The analog switch 12b receives the output signal from the latch circuit 10 after being inverted by the inverters 16, 16.

FIG. 4 shows an embodiment of the segment electrode drive circuit described above, in which reference numeral 17 is a shift register,
The data signal and the segment electrode scanning timing, that is, the sub-scanning clock CK ₂ is input, and the data signal is shifted by the clock CK ₂ . A latch circuit 18 latches the signal from the shift register 17 in synchronization with the clock signal CK ₁ .

Numerals 19, 19, 19 ... Are exclusive OR gates to which the signal from the JK flip-flop 22 for dividing the drive signal and the data signal from the latch circuit 18 are input, and the output thereof is an output gate which will be described later. Input to circuit 21. Reference numeral 20 denotes the above-mentioned drive voltage generation circuit, which is a liquid crystal drive voltage Vap, 2
Analog switches 20a and 20b, which are supplied with / 3Vap, 1 / 3Vap and 0 voltage respectively via analog switches 20a, 20b, 20c and 20d such as transmission gates, and are supplied with liquid crystal drive voltage Vap and 0 voltage, and 2 / 3Vap, 1 / 3Vap
The outputs of the analog switches 20c and 20d supplied with are output to the output gate 21 described later as a pair. 22 is J-
A drive signal scanning switching signal frequency divider composed of a K flip-flop divides the drive signal by half and outputs it. 2
3 is an exclusive OR gate, which is a drive signal and 1/2 of this signal
A frequency signal is input and a 1/2 frequency signal synchronized with the drive signal is output. A signal from the exclusive OR gate 23 is directly and via the inverter 24 a pair of analog switches 20a, 20b and 20c, 20d of the drive voltage generating circuit 20.
Input to the control terminal of and drive voltage generation circuit 20
Output 2 / 3Vap or Vap and 1 / 3Vap. Reference numeral 21 is an output gate formed of a pair of two analog switches 21a and 21b, each of which is supplied with a voltage from the drive voltage generation circuit 20, and one of the analog switches 21a has an exclusive OR gate 1
The output signal from 9 is directly connected to the other analog switch 21b.
The output signal from the exclusive OR gate 19 is the inverter 2
Inputting is reversed with 5, 25.

Next, the operation of the apparatus configured as described above will be described based on the waveform charts shown in FIGS. 3, 5, and 6.

When the frame scan switching signal is output, the shift register 9
The first common electrode CM ₁ is selected by being latched by the latch circuit 10 via the other common electrode CM _{2 ,.}
... CMn is in a non-selected state, and scanning of the scan electrodes is started.

On the other hand, the drive signal is converted by the exclusive OR gate 13 into a signal of double frequency synchronized with the common electrode selection clock and input to the exclusive OR gate 14. As a result, the phase of the drive signal input to the exclusive OR gate 14 is inverted and then input to the drive voltage generation circuit 11.

During the scan period of the common electrode, Vap and 0 voltage from the drive voltage generation circuit 11 are defined at the timing according to the output signal of the exclusive OR gate 14 in FIG. 5, and according to the output signal from the latch circuit 10. , And are selected by the analog switches 12a and 12b and output to the common electrode. Common electrode CM ₁
On the other hand, Vap is supplied in the 1/4 cycle of the scanning period, 0 voltage is supplied in the 2/4 cycle, 0 voltage is supplied in the 3/4 cycle, and Vap is supplied in the 4/4 cycle. 2 / 3Vap and 1 / 3Vap from the drive voltage generating circuit 11 are selected by the analog switches 12a and 12b and supplied to the common electrode CM ₁ thereafter. Common electrode
The above waveforms are sequentially applied to CM ₂ , CM _3, ... CMn.

On the other hand, in the segment electrode drive circuit (Fig. 4),
The data signal is input to the shift register 17, and the latch circuit
Latched at 18 and input to the exclusive OR gates 19, 19, .... The phase of the data signal is inverted by the input of a signal having a double frequency of the drive signal input from the other terminal, and the data signal is input to the output gate 21.

For the segment electrodes in the scan period of the common electrode, when the display data is bright inversion data, 0, Vap voltage from the drive voltage generation circuit 20 in the first half of the scan period, 1/3 Vap in the latter half, 2/3 Vap is an analog switch
It is selected and supplied by 21a and 21b. More specifically, 0 voltage is supplied in the 1/4 cycle of the scanning period, and Vap, 3 is supplied in the 2/4 cycle.
1/3 Vap is supplied in the / 4 cycle and 2/3 Vap is supplied in the 4/4 cycle.
On the other hand, when the display data is bright inversion data, the output from the exclusive OR gate 19 is changed, and 2 / 3Vap at the 1/4 cycle of the scanning period, 1 / 3Vap at the 2/4 cycle, and 3 / Vap It becomes Vap in the 4th cycle and 0 voltage in the 4/4 cycle. When the display data is non-inverted, 1 / 3Vap and 2 / 3Vap from the drive voltage generation circuit 20 are selected by the analog switches 21a and 21b and supplied to the segment electrodes.

FIG. 12 is a diagram specifically showing a combined voltage pulse applied to a pixel when the scan signal of the common electrode and the data signal of the segment electrode are combined.

FIG. 6 shows more specifically the waveform of the composite voltage pulse applied to the pixel.

FIG. 6B shows the waveform of the bright inversion combined voltage pulse applied to the pixels in synchronization with the line-sequential scanning signal, which is composed of the data signal of the segment electrode and the scanning signal of the common electrode. is there. FIG. 6C shows the waveform of the dark inversion combined voltage pulse applied to the pixel, which is composed from the dark inverted data signal and the scan signal of the common electrode.

That is, in FIG. 6 (2), a pixel on the common electrode, which should be in the bright state, has an electric field in the opposite direction to the required electric field, in this example, a negative electric field in the 1/4 cycle of the line-sequential scanning signal. In the 2/4 cycle of the line-sequential scanning signal, an electric field in the target direction, which is a positive electric field in this example, is applied to write a bright state. After the 3 / 4th cycle, the voltage of ± 1 / 3Vap is applied and the pixel is not inverted.

Further, in FIG. 6 (3), the pixel on the common electrode which should be in the dark state is an electric field in the opposite direction to the required electric field in the 3 / 4th cycle of the line-sequential scanning signal, that is, a positive electric field in this example. Is applied, and in the 4/4 cycle of the line-sequential scanning signal, an electric field in the target direction, in this example, a negative electric field is applied to write the dark state. After that, a voltage of ± 1/3 Vap is applied, and the pixel does not invert.

Due to this process, electric fields in both the positive and negative directions of the liquid crystal operating voltage Vap are applied to the pixels, so that the liquid crystals forming the pixels do not accumulate charges. Further, after the writing is completed in this way, the fate of the 1 / n bias method is inevitably 1 / n of the liquid crystal drive voltage, which is 1/3 in this embodiment.
A voltage called Vap that does not exceed the threshold voltage Vth of the smectic liquid crystal is applied to the pixel,
As shown in FIG. 7, this electric field acts so as to dynamically hold the liquid crystal molecules around the position of b which is slightly displaced from the domain a of the selected liquid crystal. When the scanning of all the common electrodes is completed in this way, the process moves to the scanning of the second frame and the writing of the next information is started.

Although the smectic liquid crystal panel is driven by the 1/3 averaging method in the above-mentioned embodiment, it goes without saying that the invention is not limited to this.

(Effect) As described above, according to the present invention, smectic liquid crystal compounds are injected with two substrates having the scanning electrodes and the alignment film on the surfaces so that the alignment films face each other, and the gap between the substrates is smectic. In addition to configuring the smectic liquid crystal panel by limiting it to the helical pitch of liquid crystal molecules or less, and dividing the line-sequential scanning signal into two, and writing different states in the first half and the second half, not only partial writing is possible, All the information can be written in one frame scan, and the display speed can be improved. Also,
At the time of non-selection, the writing state is held at the same time by applying an alternating current below the liquid crystal operating voltage.
The threshold voltage can be set high, the 1 / N averaging bias method can be applied, and multi-division dynamic display can be performed. Further, the liquid crystal of the pixel portion is applied with the pulses having the opposite polarities and the same absolute values during the selection period and the non-selection period, so that the direct current component is zero, no charge is accumulated, and the life of the liquid crystal is prolonged. Is achieved.

[Brief description of drawings]

FIG. 1 is a perspective sectional view of a device showing an embodiment of a smectic liquid crystal panel used in the present invention, and FIG. 2 is a schematic view showing the configuration of a liquid crystal electro-optical device of the present invention, FIGS.
The figure shows the common electrode drive circuit in the same device,
And a block diagram showing an embodiment of a segment electrode drive circuit, FIGS. 5 and 6 are waveform diagrams showing the operation of the same device.
FIG. 7 is a schematic diagram showing the movement form of liquid crystal molecules in the same device, FIG. 8 is a schematic diagram showing the molecular arrangement of chiral smectic liquid crystals, and FIGS. 9 (a) and 9 (b) show cell gaps, respectively. Schematic diagram showing the arrangement of molecules when the pitch is below the helical pitch of the liquid crystal molecule, FIG. 10 is an explanatory diagram showing the relationship between the domain of the smectic liquid crystal and polarization, and FIG. 11 is the electric field and optical effect acting on the smectic liquid crystal. FIG. 12 is a characteristic diagram showing the relationship of density, and FIG. 12 shows a composite voltage pulse applied to a pixel by a combination of a scan signal of the common electrode and a data signal of the segment electrode. 1a …… common electrode 1b …… uniaxial alignment film 2a …… segment electrode 2b …… random horizontal alignment film 6 …… liquid crystal panel 7 …… common electrode drive circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Koji Iwasa 6-31-1, Kameido, Koto-ku, Tokyo Seiko Electronics Co., Ltd. (56) Reference JP-A-56-107216 (JP, A) JP JP-A-58-179890 (JP, A) JP-A-60-235121 (JP, A) JP-A-60-172029 (JP, A)

Claims (1)

[Claims] 1. A substrate having a plurality of common electrodes on its surface and another substrate having a plurality of segment electrodes on its surface are arranged with a gap so that the electrode surfaces face each other. The smectic liquid crystal compound is sealed in the space and the gap is limited to a spiral pitch of the smectic liquid crystal compound or less, and a pixel is formed at each intersection of the common electrode and the segment electrode, and the common electrode is line-sequentially selected. Two smectic liquid crystal molecules in the pixel portion are scanned in response to a composite pulse of the potential difference between the scanning signal supplied to the common electrode and the data signal supplied to the segment electrode in synchronization with the scanning signal. In the smectic liquid crystal electro-optical device that is written in a stable array state, the combined voltage pulse applied to the pixel unit is largely 2 during the common electrode selection period. According to the display data of the data signal, it is divided into a first half of the combined voltage pulse in which one stable state is written and a second half of the combined voltage pulse in which the other stable state is written. When a state is written, the first half of the composite voltage pulse includes a voltage pulse of the other polarity, each of which is greater than or equal to the operating voltage of the smectic liquid crystal, and a voltage pulse of the one polarity that follows, the composite voltage pulse. The second half of the above includes voltage pulses having polarities different from each other at the operating voltage of the smectic liquid crystal, and when the other stable state is written, the first half of the composite voltage pulse has polarities different from each other. The second half of the combined voltage pulse includes a voltage pulse of one polarity and a voltage pulse of one polarity each of which is higher than the operating voltage of the smectic liquid crystal. In the non-selection period of the common electrode, an alternating voltage pulse composed of voltage pulses each of which is equal to or lower than the operating voltage of the smectic liquid crystal is applied to the pixel portion to write the voltage. A smectic liquid crystal electro-optical device characterized by maintaining a stable state.