JP2790137B2 - Matrix type liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention relates to a liquid crystal display device.
In particular, matrix type using ferroelectric liquid crystal
The present invention relates to a liquid crystal display device. [0002] 2. Description of the Related Art Conventionally, this type of matrix type liquid crystal display
In the device, the ferroelectric liquid crystal is not in the nematic liquid crystal
Efficient use of high-speed response and memory characteristics, one display screen
Of ON display pixels and OFF display pixels
There is one that drives a matrix to display a matrix.
You. The above-described ON display pixel corresponds to the ON display pixel.
A display area that contains a ferroelectric liquid crystal
Display area. On the other hand, the OFF display pixel described above
Is the display area containing the corresponding ferroelectric liquid crystal
A display area that does not allow light to pass through. [0003] By the way, such a problem is solved.
In the configuration, the ferroelectric liquid
In the threshold characteristics, which are important characteristics of crystals, ferroelectricity
Liquid crystal molecules (hereinafter referred to as liquid crystal molecules) are spontaneously polarized and applied
Clear thresholds intervene to work in direct interaction with the electric field
A phenomenon of not being observed is observed. When there is no such a clear threshold,
Is applied during the non-selection period in matrix driving
The liquid crystal responds at the holding voltage, and the contrast decreases.
There is a problem of doing. In contrast, dynamic
To secure the threshold required for driving, drive pulse
Width control, voltage dependence of response speed of ferroelectric liquid crystal, negative
Switching anomaly in ferroelectric liquid crystal with dielectric anisotropy
By devising the pulse waveform of the drive pulse using
In addition, during the time until the next line sequential scanning, high-frequency superposition
Stabilizing effect prevents high-speed response of liquid crystal when not selected
In some cases, the display is stopped and a matrix display is performed. Further, Japanese Patent Application Laid-Open No. Sho 62-173436 discloses
Means that the liquid crystal responds due to the holding voltage applied during the non-selection period.
So that the scanning signal and data signal are 4 pulses
A four-pulse driving method for driving has been proposed. But
In any of the driving methods described above, the ferroelectric liquid crystal
Because there is no clear threshold characteristic, the drive circuit can be complicated.
There is a problem that must be done. Accordingly, the present inventors have conducted intensive studies,
By devising the alignment treatment of ferroelectric liquid crystal,
It has been found that a clear threshold appears in the ferroelectric liquid crystal.
This point will be described in detail in an embodiment described later.
You. Therefore, the present invention provides a clear threshold characteristic of a ferroelectric liquid crystal.
To display a high-contrast matrix using
The purpose is to: Further, it is suitable for the clear threshold characteristic of ferroelectric liquid crystal.
It is another object of the present invention to use a driving circuit. [0008] Means for Solving the Problems To achieve the above object,
Therefore, in the present invention, n row electrodes and m column electrodes
Are arranged side by side so as to face each other in a grid pattern.
The ferroelectric liquid crystal between the electrode substrates (11, 12)
a liquid crystal cell (10) forming mn display pixels;
A scanning signal composed of a selection signal and a non-selection signal is applied to n row electrodes.
Row driving circuit (40) for sequentially applying signals, and the m rows
A column drive circuit (50) for applying a data signal to the electrodes;
The synthesized signal of the scanning signal and the data signal is
applied to the mn display pixels, and applied to the mn display pixels.
Matrix type for more matrix display
In a liquid crystal display device, the liquid crystal molecules of the ferroelectric liquid crystal
With respect to opposing surfaces of the first and second electrode substrates
A pretilt angle is provided and applied to the first electrode substrate.
Given the pretilt angle and the second electrode substrate
And the pretilt angle has a relationship of reverse inclination,
The liquid crystal cell is adapted to apply a voltage between the first and second electrode substrates.
On the other hand, on one polarity side and the other
An applied voltage having a threshold value at which the light transmittance starts to change above the voltage
Having a pressure-light transmittance characteristic, the selection signal and the data
The combined signal with the data signal is erased to erase the display pixel.
Signal (E₁, E_Two) And the display image following the erase signal.
The write signal (W₁, W_Two)
And a composite signal of the non-selection signal and the data signal is
The light transmission state of the display pixel determined by the write signal is
A holding signal (H) to be maintained, wherein the data signal is
With AC pulse voltage (D2, D3) based on quasi-voltage
The reference voltage is interposed between successive AC pulse voltages.
And the AC pulse voltage is
A pulse width (2) longer than the application time (to) of the reference voltage
to) to determine the light transmission state of the display pixel.
Characterized in that it contains
You. In the above structure, the liquid crystal component of the ferroelectric liquid crystal is
To the opposing surfaces of the first and second electrode substrates.
The tilt angle is given to the pre-tilt applied to the first electrode substrate.
Tilt angle and pretilt given to the second electrode substrate
Since the angle has an inversely inclined relationship, the ferroelectric liquid
A clear threshold characteristic appears in the crystal. As a result, the liquid crystal cell
One polarity side and the other polarity side with respect to the applied voltage between the electrode substrates
When the absolute value exceeds a predetermined voltage, the light transmittance starts to change.
Having an applied voltage-light transmittance characteristic having a threshold value
become. Utilizing such an applied voltage-light transmittance characteristic
Then, erase, write, and hold signals are applied to the display pixels.
The matrix display can be performed by adding
it can. In this case, the ferroelectric liquid crystal has a clear threshold characteristic.
Is determined by the write signal when the hold signal is applied.
It is easy to maintain the light transmission state of the specified display pixel.
And high-contrast display can be performed. [0011] Further, the data signal is defined with reference to a reference voltage.
Continuous AC pulse voltage (D2, D3)
So that the reference voltage is interposed between the current pulse voltages
At the same time, the AC pulse voltage is changed to the application time (t
o) Light transmission state of display pixel with longer pulse width (2 to)
To include the pulse voltage for determining the state
doing. This kind of matrix type liquid crystal display device
And aiming for a large screen, the number of row electrodes will increase.
The scanning period must be shortened.
Also determines the light transmission state of the display pixel as described above
The pulse width of the pulse voltage from the reference voltage application time
By increasing the length, the writing time to the display pixels can be reduced.
Minutes can be secured. [0013] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Will be described. Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
More specifically, FIG. 1 shows a matrix according to the present invention.
1 shows an overall configuration of a liquid crystal display device. This liquid crystal display
The device includes a matrix type liquid crystal cell 10.
As shown in FIGS. 1 and 2, the liquid crystal cell 10 of FIG.
The electrode substrates 11 and 12 are, for example, 1 to 4 (μm) gaps.
Are disposed in parallel with each other via a
Phenylpyrimidine-based ferroelectric liquid crystal 13
Sealed and the polarization axes of the electrode substrates 11 and 12 are orthogonal to each other
Attach each of the polarizing plates 14 and 15 formed from outside
It is configured. The electrode substrate 11 is as shown in FIGS.
In addition, a transparent glass plate 11a is oxidized along its inner surface.
Transparent conductive film 11b made of indium or tin oxide
And an n-shaped line current is formed on the inner surface of the conductive film 11b.
The poles X1, X2,..., Xn are
The left and right sides of the same figure
It is configured to protrude from the row. On the other hand, the electrode substrate 12 is shown in FIGS.
Along the inner surface of the transparent glass plate 12a
Transparent conductive film made of indium oxide or tin oxide
12b and an m-shaped film is formed on the inner surface of the conductive film 12b.
Column electrodes Y1, Y2 ‥‥, Ym shown in FIG.
To each other and each row electrode X1, X2 ‥
‥, and Xn are formed so as to project perpendicularly to each other.
I have. The inner surface of the conductive film 11b has
The deposited film 16 made of silicon is used as the conductive films 11b and 12b.
And the deposition angle θa (= 80)
(Degree) to 85 (degree)).
Is being worn. On the other hand, the inner surface of the conductive film 12b has
The vapor deposition film 17 made of silicon nitride has a normal line P and a vapor deposition angle θb.
Is deposited by oblique deposition. to this
Thus, each liquid crystal molecule 13a of the ferroelectric liquid crystal 13
So that the tilt angle θp = 5 (degrees) to 35 (degrees) can be given.
The ferroelectric liquid crystal 13 is subjected to an alignment treatment. In such a case, ferroelectricity in the liquid crystal cell 10
In sealing the liquid crystal 13, first, the two deposited films 16, 1
7 (that is, each deposition angle θa, θb)
Conducting through the center of the interval between the inner surfaces of the electrofilms 11b and 12b
Being parallel to the electrolytic films 11b and 12b (that is, perpendicular to the normal line P)
Electrode substrates 11 and 1 so as to be symmetrical with respect to the center line.
Combine 2 in parallel. After that, the ferroelectric liquid crystal 13 is added.
Heat to an isotropic liquid phase, and use the capillary phenomenon to make both electrodes
The liquid crystal cell 10 is injected between the substrates 11 and 12, and
The ferroelectric liquid crystal 1 is gradually cooled by about one minute (degree).
3 is smectic C^*Cool down to phase. As a result of such cooling, the smectic layer and
The liquid crystal molecules 13a of the changed ferroelectric liquid crystal 13 are both vapor-deposited.
The center line along each deposition direction and unevenness of the films 16 and 17
It will be oriented so as to be line symmetric. In such cases,
The pretilt angle θp of each liquid crystal molecule 13a is equal to the center line
From the center line as approaching each of the deposited films 16 and 17
It is designed to increase in line symmetry. In other words, strong
The smectic layer of the dielectric liquid crystal 13 is as shown in FIG.
In addition, each of the deposited films 16, 17 is symmetrical with respect to the center line.
Thereby, bending deformation can be given to the cross-sectional curved shape. The liquid crystal cell 1 constructed as described above
0, the voltage applied between both electrode substrates 11 and 12 is
When the voltage is low, the liquid crystal molecules do not rotate, but a predetermined high voltage is applied.
When applied, the ferroelectric liquid crystal 13 is positioned on one side of the center line.
Liquid crystal molecules 13a to be placed (hereinafter, referred to as one-sided liquid crystal molecules)
Is the center of the ferroelectric liquid crystal 13
Each liquid crystal molecule 13a located on the other side of the line (hereinafter referred to as the other side liquid crystal component)
The direction of rotation of the child). For this reason, the one side liquid crystal molecules are aligned with the center line.
In the vicinity of the upper side, it will collide with the other liquid crystal molecules.
As a result, the energy loss of the ferroelectric liquid crystal 13 becomes
The one side liquid crystal molecules rotate in the same manner as the other side liquid crystal molecules
Compared to the case, it is greatly increased. In other words, ferroelectric liquid
Each liquid crystal molecule 13a of the crystal 13 is placed between the two electrode substrates 11 and 12.
When the applied voltage to the
It only starts rotating with pressure. this thing
Means that ferroelectric liquid crystal 13 has reached a definite threshold
Means Incidentally, the ferroelectric material subjected to the orientation treatment as described above
Experiments on the relationship between applied voltage and light transmittance in crystalline liquid crystal 13
As a result, as shown in FIG.
Obtained. In addition, the applied voltage is a response of the ferroelectric liquid crystal 13.
The applied voltage for a sufficient time longer than the response time
Light transmittance is a relative light transmittance. Also, as mentioned above
Force by conventional alignment method without such alignment processing
Experiment on the relationship between applied voltage and light transmittance in electro-optical liquid crystal
As a further confirmation, as shown in FIG.
Was done. By comparing these curves X and Y, it is easy to understand.
As can be seen, according to curve X, the ferroelectric liquid crystal 13
Light transmittance maintains zero (%) when applied voltage is 10 (V) or less
And rapidly increases at an applied voltage of 10 (V) to 20 (V), and
Maintain 100 (%) at an applied voltage of about 20 (V) or more
On the other hand, according to the curve Y, the light transmittance of the ferroelectric liquid crystal is
From applied voltage (V) to about 7 (V), 40 (%) to 1
00 (%), and 10 (V)
Maintain 0 (%). As a result, the characteristic by the curve X
The conventional ferroelectric liquid crystal 13 has a characteristic represented by a curve Y.
Very clear threshold characteristics compared to ferroelectric liquid crystal
I can recognize that. The characteristics of the applied voltage and light transmittance shown in FIG.
The characteristic is when the positive side of the applied voltage is equal to or higher than a predetermined voltage.
It shows that the light transmittance starts to increase, but the ferroelectric
Since the liquid crystal 13 has a memory property, the voltage mark on the positive polarity side
When a voltage higher than a predetermined voltage is applied to the negative polarity side
The light transmittance will begin to decrease. In addition, each row electrode X
1 to Xn and the intersections of the column electrodes Y1 to Ym
With each ferroelectric liquid crystal part present at each intersection
Each display pixel (1, 1), ‥‥, (1, m), (2, 1)
‥‥, (n, m) (see FIG. 1). Row electrodes and columns
When a proper unipolar voltage is applied between the electrodes
The display pixels transmit light in the molecular alignment state that the conductive liquid crystal can take.
State (that is, the ON display state).
Appropriate voltage of opposite polarity was applied between electrode and column electrode
Display pixel in the state of molecular alignment that ferroelectric liquid crystal can take
Becomes a state in which no light is transmitted (that is, an OFF display state).
So that the polarization axes of the polarizing plates 14 and 15 are ferroelectric liquid crystal.
Is determined in relation to the molecular orientation axis. In addition, the polarizing plate
Behind the light source 14, a light source for projecting light to the polarizing plate 14 is arranged.
Have been. Also, the ferroelectric liquid crystal is released from its voltage application.
The previous state is maintained after the cancellation. Further, the liquid crystal display device is as shown in FIG.
And the line-sequential scanning circuit 20
The connected reference signal generation circuit 30 and the line-sequential scanning circuit 20
A row driving circuit 40 connected to the reference signal generating circuit 30;
And a column driving circuit 50.
Is a ROM 21 and a controller connected to the ROM 21.
, And is constituted by a roller 22. The ROM 21 has a liquid crystal cell.
Display data representing predetermined display contents to be displayed on the
Data is stored in advance, and this display data is stored in the liquid crystal cell.
Row electrode display data input to any of the 10 row electrodes
And column electrode display data input to each column electrode of the liquid crystal cell 10.
And the The controller 22 receives a reference clock pulse a
(See FIG. 7) are sequentially generated, and a synchronization pulse b (see FIG. 7)
Are sequentially generated, and shift clock pulses q are sequentially generated,
The row electrode display data from the ROM 21 is converted into a data pulse Px
And the column electrode display data from the ROM 21
Are sequentially generated as data pulses Py. Reference signal
As shown in FIG. 1 and FIG.
And the inverter 3 connected to the
1, the controller 32,
Equipped with a binary counter 33 connected to the inverter 32
Inverter 31 is connected to each
Inversion pulse b is sequentially inverted and generated as an inversion pulse
You. The inverter 32 is provided with each inverted pulse from the inverter 31.
Inversion pulse (ie, synchronization pulse b)
Occurs as The binary counter 33 is an inverter
Is repeatedly reset by each sync pulse b from
After each reset, each reference clock from the controller 22
Counting while inverting the clock pulse a, and counting each result
As a binary pulse e from the output terminal Q2 (see FIG. 7),
What happens next. Further, the reference signal generating circuit 30
OR gate connected to the counter 32 and the binary counter 33
And an inverter 35 connected to the binary counter 33
And the OR gate 34 is connected to the inverter 32
At the high level in response to the rise of the synchronization pulse b.
After generating the auto pulse C1 (see FIG. 7),
Each binary pulse e from the counter 33 and the inverter 32
In response to each of the synchronizing pulses b.
Gate pulse C2 (see FIG. 7) goes high every time
Occurs at Each gate path from the OR gate 34
Lus C1 and C2 are the synchronous pulses b from inverter 32.
Goes low in response to the falling edge of. Inverter 35
Sequentially outputs each binary pulse e from the binary counter 33.
It is inverted and generated as an inverted pulse e (bar). The row drive circuit 40 is connected to the controller 22.
Shift register 40A and reference signal generation circuit 30
And each logic circuit 40B connected to the shift register 40A
1, 40B2,..., 40Bn.
The register 40A receives each synchronization pulse from the controller 22.
b are sequentially received as shift pulses, and each of these shift pulses
Data pulses from the controller 22 in synchronization with the
Px is discussed in any of the logic circuits 40B1 to 40Bn.
The shift is sequentially performed from the logical circuit 40B1 to the logical circuit 40Bn.
To give a data pulse h (see FIG. 7). The logic circuit 40B1 is shown in FIGS.
As shown in FIG. 5, the inverter 3 of the reference signal generation circuit 30
2 and AND gate 4 connected to shift register 40A
1, the inverter 35 of the reference signal circuit 30 and the shift register.
Having a NAND gate 42 connected to the transistor 40A.
The AND gate 41 receives the signal from the shift register 40A.
During the high level of the data pulse h, the
Gate pulse j at high level in response to sync pulse b
(See FIG. 7). Also, from the AND gate 41
Is the synchronization pulse b from the inverter 32
Goes low in response to the falling edge of. NAND gate
42 is the data pulse h from the shift register 40A.
In response to the inversion pulse e (bar) from the inverter 35
And both the data pulse h and the inverted pulse e (bar) are high.
Gate pulse i at low level at level (see FIG. 7)
And the gate pulse i is inverted into an inversion pulse e (bar).
-) Or high level when data pulse h is low level
To The logic circuit 40B1 includes an AND gate
NOR gate 4 connected to a NAND gate 41 and a NAND gate 42
3 and the NOR gate 43 is provided with an AND gate 4
1 and each gate pulse j, i from the NAND gate 42
Gate pulse k at high level only at low level of
(See FIG. 7). Transmission gate 4
4 is a high level gate pulse from the AND gate 41.
In response to the pulse j, the gate pulse j is supplied to the constant voltage circuit 4
Based on the negative voltage (-2Vo) from 4a, (-2Vo)
Each signal as a scanning signal S1 having a level of
Output terminal common to transmission gates 45 and 46
47, which is generated from 47 and applied to the row voltage X1 of the liquid crystal cell 10.
Each transmission gate 44, 45, 46
For example, Toshiba Corporation's TC4066 type integrated circuit
Adopted. The transmission gate 46 is
In response to the gate pulse k from the NOR gate 43,
Of the gate pulse k after falling of the gate pulse j.
Under the high level of the tap pulse h, the
Shift to the positive constant voltage (+ Vo)
Emitted from output terminal +47 as scanning signal S2 (see FIG. 8)
It is applied to the row electrode X1. In such a case, both scanning signals S
1, S2 is a selection signal for selecting the row electrode X1 (FIG. 8).
(See T) for T / n. However, the symbol T is one stroke
This represents the surface display time (see FIG. 9). The transmission gate 45
High level gate pulse i from NAND gate 42
At the zero level (immediately after the falling of the data pulse h).
To the ground level), and the result of this shift is
The signal generated from the output terminal 47 as signal S3 (see FIG. 8)
Applied to pole X1. In such a case, the scanning signal S3 is
A non-selection signal (see FIG. 8) for deselecting the pole X1;
And functions during T / n. The remaining logic circuits 40B2 to 40Bn share
And the logic circuit 40B1.
Each of the logic circuits 40B2 to 40Bn includes a shift register 40
A from each data pulse h from A and reference signal circuit 30
In response to the synchronization pulse b and the gate pulse e of
Similarly to the path 40B1, each scanning signal S1, S2 and S3 is
Each occurs. Thus, both signals from the logic circuit 40B2
The scanning signals S1, S2 and the scanning signal S3 are a selection signal and
A non-selection signal is applied to the row electrode X2 of the liquid crystal cell 10, respectively.
And both scanning signals S1 and S2 from the logic circuit 40B3.
2 and the scanning signal S3 are used as a selection signal and a non-selection signal.
Each is applied to the row electrode X3 of the liquid crystal cell 10, and
Further, both scanning signals S1, S2 from the logic circuit 40Bn and
The scanning signal S3 is a selection signal and a non-selection signal, respectively.
And applied to the row electrodes of the liquid crystal cell 10. The column drive circuit 50 is connected to the controller 22.
The shift register 50A and the latch 50B connected to each other and the reference
Each logic circuit connected to the signal generation circuit 30 and the latch 50B
Roads 50C1, 50C2, ‥‥, 50Cm,
The shift register 50A stores each data from the controller 22.
Data pulse Py from the controller 22
It is sequentially input in response to the lock pulse q,
Repeatedly convert to m data pulses and apply to latch 50B
I do. The latch 50B is connected to each of the shift registers 50A.
m data pulses from each controller
And successively latches the data pulse d
Each of the logic circuits 50C1, 50C2,.
５０, 50 Cm. The logic circuit 50C1 is shown in FIGS.
As shown in the figure, the inverter 51 connected to the latch 50B
OR gate of the latch 50B and the reference signal generation circuit 30
And an AND gate 52 connected to the
And connected to the inverter 35 of the reference signal generation circuit 30.
Connected to AND gate 53 and both AND gates 52 and 53
The inverter 51 includes a NOR gate 54
The latch data pulse from the latch 50B is inverted to
Inverts the data pulse. AND gate 52 has a latch
O during the high level of the latch data pulse d from 50B.
In response to each of the gate pulses c1 and c2 from the R gate 34,
In response, each gate pulse is generated at high level, and
When the switch data pulse d is low,
Generate a pulse. The AND gate 53 receives the signal from the inverter 51
Low level when the inverted data pulse of
Generate a high-speed pulse, and a high level of the inverted data pulse.
Each inverted pulse e (bar) from the inverter 35 during the bell
Generates each gate pulse at high level in response to
You. The NOR gate 54 is connected to both AND gates 52 and 53.
In response to each of these gate pulses, the latch data pulse d
Of each gate pulse f1 (see FIG. 7) during the high level of
During the low level of the latch data pulse d.
A heat pulse f2 (see FIG. 7) is sequentially generated. NORGE
Port 55 is supplied from reference signal generating circuit 30 and inverter 32.
Each synchronization pulse b and each gate pulse from the NOR gate 54
Each gate pulse at high level in response to
G1 and g2 (see FIG. 7) are sequentially generated. The transmission gate 56 is an invar
Each synchronous pulse b in response to each synchronous pulse b from the
To the zero level (that is, the ground level)
Is output terminal 59 common to transmission gates 57 and 58
Liquid crystal cell 1 generated as each data signal D1 (see FIG. 8).
0 is applied to the column electrode Y1. Also transmission
The gate 57 receives the gate pulse f1 from the NOR gate 54.
And the transmission gate 58
When the gate pulse g1 is received from the OR gate 55,
The transmission gate 57 supplies the gate pulse f1 with a constant voltage.
Up to the level of the negative constant voltage (-V1) from the circuit 57a.
Transmission gate 58
The gate pulse g1 is a positive constant voltage from the constant voltage circuit 58a.
Shift to level (+ V1). For this reason, such transmissions
The shift results of the gates 57 and 58 are combined and output.
59, each AC data signal D2 (see FIG. 8) is at zero level.
And is applied to the column electrode Y1. Take
In this case, each data signal D1, D2 is applied to the column electrode Y1.
Each ON data signal functions for T / n.
(See FIG. 8). Each transmission gate 5
For example, TC4 manufactured by Toshiba Corp.
A 066 type integrated circuit is employed. When the transmission gate 57 is N
Upon receiving each gate pulse f2 from the OR gate 54
The transmission gate 58 is the NOR gate 55
When each gate pulse g2 is received from the
The gate 57 outputs each gate pulse f2 to the constant voltage circuit 57a.
Shift to the negative constant voltage level (-V1) from
In both cases, the transmission gate 58 is
G2 is the level of the positive constant voltage from the constant voltage circuit 58a.
(+ V1). For this reason, such transmissions
The shift results of the gates 57 and 58 are combined and output.
59, each AC data signal D3 (see FIG. 8) is at zero level.
And is applied to the column electrode Y1. Take
In this case, both data signals D1 and D3 are applied to the column electrode Y1.
Function as each OFF data signal during T / n
(See FIG. 8). The remaining logic circuits 50C2 to 50Cm share
And the logic circuit 50C1.
Each of the logic circuits 50C2 to 50Cm receives a signal from the latch 50B.
Each latch data pulse d and the reference signal generation circuit 30
Pulse b and gate pulses c1, c2, e
(Bar), as in the logic circuit 50C1, each data
Data signals D1, D2 and D3. Thus, both data from the logic circuit 50C2 are
Data signals D1, D2 and both data signals D1, D3 are ON.
The liquid crystal cell is used as the data signal and the OFF data signal, respectively.
Applied to the column electrode Y2 of the logic circuit 10 and from the logic circuit 50C3.
Data signals D1, D2 and both data signals D1, D3
Are the ON data signal and the OFF data signal, respectively.
Is applied to the column electrode Y3 of the liquid crystal cell 10;
Both data signals D1, D2 from the logic circuit 50Cm and both
Data signals D1 and D3 are an ON data signal and an OFF data signal.
Data signal to the column electrode plate Ym of the liquid crystal cell 10 respectively.
Granted. Here, each constant voltage circuit 44a outputs
Constant voltage (-2 Vo), constant voltage from constant voltage circuit 46a
(+ Vo), the constant voltage (−V) from the constant voltage circuit 57a.
1) and the constant voltage (+ V1) from the constant voltage circuit 58a.
The determination method will be described. Display in OFF display state
A voltage is applied to the pixel (n, m) to change to the ON display state.
The light transmittance of the display pixel (n, m) is 9
The time to reach 0% is defined as the response time of the ferroelectric liquid crystal 13,
Before corresponding to the signal width of the data signal D1 or the scanning signal S1
The response time is set as the response time to and the data signal D2 or
Represents the response time corresponding to the signal width of the scanning signal S2 by 4t.
Let o be V in relation to curve X (see FIG. 3)._O
= 15 (V) and V1 = 7.5 (V),
V_O+ V1 = 22.5 (v), V_O−V1 = 7.5
(V) and V_O+ V1
The excess rate becomes 100% and V_OWhen a voltage of -V1 is applied
The light transmittance becomes 0% when the threshold voltage of the ferroelectric liquid crystal is reduced.
The pressure can be clarified. However, the set response time t_oIs V_O+
The response when a voltage of V1 = 22.5 (V) is applied.
Time. In the present embodiment configured as described above,
The line-sequential scanning circuit 20 outputs the reference clock pulse a,
Period pulse b, shift clock pulse q, data pulse P
x and data pulse Py are sequentially generated, respectively,
The raw circuit 30 generates each reference clock pulse a and each synchronization pulse.
b, each synchronization pulse b, each gate pulse c
1, c2, and e (bar) are the timings shown in FIG.
, The row drive circuit 40 causes the line-sequential scanning
Sequence of each synchronization pulse b and data pulse Px from the path 20
, The synchronization pulse b from the reference generation signal circuit 30 and each gate
In response to the pulse e (bar), a selection signal (both scanning signals S
1, S2) or a non-selection signal (scanning signal S3).
Row electrode X1 or row electrode X1
From the row electrode Xn to the row electrode Xn while shifting by T / n
On the other hand, the column driving circuit 50
Each synchronization pulse b, each shift clock pulse q and each data
Data pulse Py and the same signal from the reference signal generation circuit 30.
Period pulse b, each gate pulse c1, c2, e (bar)
In response, each ON data signal (data signal D1, D2)
Alternatively, each OFF data signal (data signal D1, D3)
Repeatedly applied to each column electrode Y1 to Ym of the liquid crystal cell 10, respectively.
(See FIG. 9). In such a state, the liquid crystal cell 10
The row driving circuit 40 and the column driving circuit 50
Each display pixel (1,
This will be described by taking 1) and (1, 2) as examples. For example, the line
The drive circuit 40 supplies a selection signal (both scanning signals S1) to the row electrode X1.
And S2), and the column driving circuit 50
An ON data signal (both data signals D1 and D2) is applied to Y1.
When given, the display pixel (1, 1) turns on the display pixel (FIG. 1).
0). In such a case, the row electrode X1 and the column
The scanning signal S1 and the data signal D1
Of the erase signal E1 (see FIG. 11A) by combining
And the scanning signal S2 and the data signal D
2 is combined with the write signal W1 (see FIG. 11A).
It will be granted for 4 to. However, the erase signal E1
Has a level of (-2 Vo), while write signal W1
Changes the level of (Vo + V1) and the level of (-V1)
Signal. Thus, the display pixel (1, 1) outputs the erase signal
Supports E1 level (-2Vo) and set response time to
OFF display state based on the signal width
A diagram according to a response of the ferroelectric liquid crystal 13 to the write signal W1.
ON display by increasing light transmittance as shown in 11 (B)
State. After T / n, non-selection from the row drive circuit 40 is performed.
Select signal and the ON data signal from the column drive circuit 50 (or
Is an AC holding signal H obtained by synthesizing an OFF data signal.
(See FIG. 11A) is applied to the display pixel (1, 1).
To maintain the ON display state. In such a case, the holding signal H
Due to the level change and signal width of ± V1, the ferroelectric liquid crystal 1
3 is almost unresponsive and the display state of the display pixel (1, 1) is ON.
Secured. The row drive circuit 40 selects the row electrode X1.
Signals (both scanning signals S1 and S2) and columns
The drive circuit 50 supplies an OFF data signal (both data) to the column electrode Y2.
Data signals D1 and D3), the display pixels (1,
2) is the OFF display pixel (see the hatched portion in FIG. 10)
Function as In such a case, the row electrode X1 and the column electrode Y2
Between the scanning signal S1 and the data signal D1.
Signal E2 (see FIG. 11 (C)) is interleaved with to
Of the scanning signal S2 and the data signal D3.
The write signal W2 (see FIG. 11C) resulting from the combination is 4 to
Will be granted. However, the erase signal E2 is (−
2Vo) while the write signal W2 is at (V1
−Vo) and (+ V1). Thus, the display pixels (1, 2) receive the erase signal.
Signal width corresponding to level (-2Vo) and to of signal E2
Is turned off once based on the write signal W
Under the non-operation of the ferroelectric liquid crystal 13 with respect to the step change of 2
As a result, the light transmittance is maintained at almost zero as shown in FIG.
Then, an OFF display state is realized. In addition, OFF table after that
The holding of the indicated state is performed by the holding signal H as described above.
You. (See FIGS. 1A and 1C). Also, other display pixels
The liquid crystal cell 10 is driven in a similar manner,
Drive. As described above, the ferroelectric liquid crystal 13
It has a light transmittance-voltage characteristic specified by a curve X in FIG.
Thus, the inner surfaces of both conductive films 11b and 12b are
By performing the alignment treatment by forming 6, 17
ON display state and OFF display state of each display pixel of cell 10
When driving dynamically to clarify the state,
Scanning signals to be applied to the electrodes X1 to Xn, and each column electrode Y
1 to Yn, the light signal
It only requires a simple waveform change in relation to the pressure characteristics.
No. Therefore, the clear threshold characteristic of the ferroelectric liquid crystal 13 is
Of the column drive circuit and the drive circuit of the display device.
Improved display contrast while greatly simplifying circuit configuration
Can be achieved. In addition, the voltage applied to the liquid crystal cell 10 is one screen.
In the display time T, all are canceled and become zero, so that the ferroelectric
Deterioration of the liquid crystal due to DC components can also be prevented. In addition,
In practicing the present invention, both conductive films 11b and 12b
The deposition films 16 and 17 were formed, respectively.
Instead, evaporation is performed only on one of the conductive films 11b and 12b.
It may be performed so that the film 16 or 17 is formed.
No. In the practice of the present invention, a ferroelectric liquid
The arrangement necessary to give bending deformation to the smectic layer of crystal 13
The direction treatment method is not limited to the oblique deposition method.
For high pretilt used for alignment of SBE liquid crystal
Polyimide alignment film LQ-1800 (Hitachi Chemical Co., Ltd.)
Is applied to each of the conductive films 11b and 12b, and then each deposited film 1
Rubbing by aligning the rubbing direction with the deposition direction of 6, 17
It may be carried out as follows. In practicing the present invention, the liquid crystal cell
The reflector 10 may be of a reflection type without being limited to the transmission type.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall configuration diagram showing one embodiment of the present invention. FIG. 2 is an enlarged schematic sectional view of the liquid crystal cell in FIG. FIG. 3 is a graph showing a relationship between a light transmittance of a ferroelectric liquid crystal and an applied voltage. FIG. 4 is a detailed circuit diagram of a reference signal generation circuit in FIG. 1; FIG. 5 is a detailed circuit diagram of a logic circuit of the row drive circuit in FIG. FIG. 6 is a detailed circuit diagram of a logic circuit of the column drive circuit in FIG. FIG. 7 is an output waveform diagram of main circuit elements in FIGS. 1 and 4 to 6; FIG. 8 is a diagram showing waveforms of a data signal and a scanning signal. 9 is an explanatory diagram of signals applied to the liquid crystal cell in FIG. FIG. 10 is a partially enlarged view of a row electrode and a column electrode. FIG. 11 is an explanatory diagram of an applied signal to a liquid crystal cell. [Description of References] 10: liquid crystal cell, 20: line sequential scanning circuit, 30: reference signal generation circuit, 40: row drive circuit, 50: column drive circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G02F 1/133 G09G 3/36

Claims (1)

(57) [Claims] (1) First and second electrode substrates (1) in which n row electrodes and m row electrodes are arranged side by side so as to face each other in a grid pattern.
A liquid crystal cell (10) for forming mn display pixels by enclosing a ferroelectric liquid crystal between (1) and (12), and a scanning signal comprising a selection signal and a non-selection signal is sequentially applied to the n row electrodes. And a column drive circuit (50) for applying a data signal to the m column electrodes, and a combined signal of the scan signal and the data signal is applied to the mn display pixels. Apply the above mn
In a matrix type liquid crystal display device in which a matrix display is performed by a plurality of display pixels, a liquid crystal molecule of the ferroelectric liquid crystal has a pretilt angle with respect to an opposing surface of the first and second electrode substrates. And a pretilt angle given to the first electrode substrate and a pretilt angle given to the second electrode substrate have a relationship of reverse inclination, and the liquid crystal cell has the first and second liquid crystal cells. On the one polarity side, the other polarity side with respect to the applied voltage between the two electrode substrates, has an applied voltage-light transmittance characteristic having a threshold value at which the light transmittance starts to change at an absolute value of a predetermined voltage or more, The combined signal of the selection signal and the data signal includes an erasing signal (E ₁ , E ₂ ) for erasing the display pixel and a write signal (W) for determining the light transmission state of the display pixel following the erasing signal. _1, W ₂₎ Yu A composite signal of the non-selection signal and the data signal is a holding signal (H) for maintaining a light transmission state of a display pixel determined by the write signal, and the data signal is based on a reference voltage. The AC pulse voltage (D2, D3) is configured such that the reference voltage is interposed between each successive AC pulse voltage, and the AC pulse voltage is applied to the reference voltage for an application time (to).
A matrix-type liquid crystal display device comprising a pulse voltage for determining a light transmission state of the display pixel with a longer pulse width (2 to). (2) The matrix type liquid crystal display device according to claim 1, wherein the application time (4 to) of the AC pulse voltage is four times as long as the application time of the reference voltage. (3) The matrix according to claim 1 or 2, wherein the pulse width of the pulse voltage is twice as long as the application time of the reference voltage (2 to). Liquid crystal display device.