JPH0473846B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a liquid crystal electro-optical device using chiral smect C liquid crystal.

(Prior Art) In recent years, liquid crystal display panels using chiral smectate C phase (hereinafter referred to as SmC ^* ) have attracted attention as display devices with high-speed response and memory retention.

For example, 2-methylbutyl P-[(P-n-decyloxybenzylidene)amino] is widely known as a liquid crystal having this chiral smectic C phase. This liquid crystal has layers L ₁ , L ₂ , L ₃ with a certain azimuth angle as shown in FIG.
...They are arranged in a twisted spiral structure.

By the way, when this SmC ^* is injected between two substrates B, which have a gap of about 1 μm, which is smaller than the helical pitch (usually several μm),
(Figure), liquid crystal molecules lose their helical structure and are aligned with their molecular axes parallel to the substrate and tilted by ±θ from the normal direction of the layers.

In other words, the liquid crystal injected into the cell has a mixed state in which domains are tilted at an angle θ clockwise from the layer normal and domains tilted counterclockwise by θ, that is, −θ. have

By the way, SmC ^* liquid crystal molecules generally have an electric dipole in the direction perpendicular to the molecular axis, and if one domain has an electric dipole pointing upwards with respect to the cell substrate, the other domain has an electric dipole pointing downwards. will have a child. Therefore, when an electric field is applied between substrates B and B, the liquid crystal molecules in the substrates are aligned at a position tilted by +θ or -θ from the normal direction of the layers, and when an electric field is applied in the opposite direction, they are reversed. Do-
Arrange them all at an angle of θ or +θ.

Needless to say, liquid crystal molecules have polarization characteristics, so if the substrate is made of a transparent material and polarization plates are provided on both sides, an optical bright state and dark state will occur depending on the alignment direction of the liquid crystal molecules, resulting in a so-called liquid crystal. It can have the function of a display panel.

In this way, liquid crystal panels using SmC ^* liquid crystals have extremely fast response speeds on the order of microseconds.
Although pattern display has the great advantage of being able to maintain the display state for a long period of time even after the electric field is removed, the upper limit of the non-selective electric field, the so-called liquid crystal threshold voltage Vth, is extremely low at 0.5V. (FIG. 13), since the margin for the non-selected state is small, dynamic driving is performed by applying the 1/N bias method, but there is a problem in that it is practically impossible.

(Objective) In view of such problems, an object of the present invention is to provide an SmC ^* liquid crystal electro-optical device to which the 1/N bias method can be practically applied.

That is, the feature of the present invention is that in the first half of electrode selection, the liquid crystal operating voltage in the opposite direction is
The main feature is that the liquid crystal operating voltage in the forward direction is applied to the liquid crystal panel in the second half when the electrode is selected, and the alternating voltage that is lower than the liquid crystal operating voltage is applied to the liquid crystal panel when the electrode is not selected.

(Structure) Therefore, details of the present invention will be described below based on illustrated embodiments.

Figure 1 shows a liquid crystal display panel according to the present invention using SmC ^* , and reference numeral 1 in the figure is one substrate constituting a cell of the liquid crystal electro-optical panel, which is attached to the surface of an electrically insulating transparent plate such as glass. Common electrodes 1a, 1a
..., a polyimide thin film is formed on the surface by printing or dipping, and a uniaxial alignment film 1b is provided by rubbing in one direction.

2 is the other substrate constituting the cell, and segment electrodes 2a, 2a... are formed on the surface of the electrically insulating transparent plate.
A uniaxial alignment film 2 similar to that described above is provided on the surface.
b.

Two substrates 1 subjected to alignment treatment in this way
and 2 are arranged parallel to each other with their orientation surfaces facing each other with a distance d smaller than the helical pitch of the SmC ^* liquid crystal, and in the gap formed by the two substrates.
SmC liquid crystal is injected. Polarizing plates 3 and 4 are disposed on the upper and lower substrates formed in this way, respectively, with their polarization axes perpendicular to each other, and a display panel is constructed so that the rotation of liquid crystal molecules is displayed as a bright and dark state. .

FIG. 2 shows an embodiment of a smectic liquid crystal display device using the above-mentioned liquid crystal panel. In the figure, reference numeral 6 denotes the above-mentioned liquid crystal electro-optic panel, and common electrodes and segment electrodes are respectively connected to the common electrode and the segment electrode. It is constructed by connecting a drive circuit 7 and a segment electrode drive circuit 8.

Next, these drive circuits will be explained.

FIG. 3 shows an embodiment of the common electrode drive circuit, in which reference numeral 9 is a shift register that sequentially shifts the frame scan switching signal using a clock signal synchronized with the common electrode scan speed. . A latch circuit 10 latches the signal from the shift register 9 in synchronization with a clock signal, and outputs a drive voltage from an operating voltage generation circuit 11 (described later) to a common electrode via a gate circuit 12.
CM ₁ , CM ₂ ... are supplied to CM _o .

Reference numeral 11 denotes the aforementioned drive voltage generation circuit, which generates liquid crystal drive voltages Vap, 2/3Vap, 1/3 from a power supply (not shown).
Vap and zero voltage are connected to analog switches 11a, 11b, 11 such as transmission gates, respectively.
c, 11d, and the liquid crystal drive voltage Vap
and an analog switch 11 supplied with zero voltage.
A and 11b, and the outputs of analog switches 11c and 11d, which are supplied with 2/3 Vap and 1/3 Vap, are output as a pair to an output gate 12, which will be described later.

Reference numeral 13 denotes a frame scan switching signal frequency divider consisting of a JK flip-flop, which divides the frame scan switching signal using a clock signal synchronized with the common electrode scanning speed and outputs the divided signal. 14 is an exclusive OR gate, and frame switching signal frequency divider 13
The analog switches 11a, 11b and 11c, which invert the phase of the drive signal when the scanning signal is input, form a pair of drive voltage generation circuits 11 directly and via an inverter 15.
Drive voltage generation circuit 1 by inputting it to the control terminal of 11d.
It is configured to output 1 to 0 voltage and 2/3Vap or Vap and 1/3Vap. Reference numeral 12 denotes an output gate consisting of a pair of two analog switches 12a and 12b, each of which receives a voltage supply from the drive voltage generation circuit 11, and one analog switch 12a receives the output signal from the latch circuit 10 directly. The other analog switch 12b inputs the signal from the latch circuit 10 to the inverters 16, 16...
... is inverted and input.

FIG. 4 shows an embodiment of the segment electrode drive circuit described above, and reference numeral 17 in the figure is an exclusive OR gate to which a frame switching signal and a data signal are input, and the point at which the frame switching signal is input. This inverts the data. 18 is a shift register into which the data signal from the exclusive sum gate 17 and the segment electrode scanning timing, that is, the sub-scanning clock CK ₂ are input, and the data signal is clocked.
It is configured to be shifted by CK ₂ . 1
Numeral 9 is a latch circuit that latches in synchronization with the signal clock signal CK ₁ from the shift register 18 and outputs a drive voltage from a drive voltage generation circuit 20 (described later) to the segment electrodes SG ₁ and SG ₂ via a gate circuit 21.
...is supplied to SG _n . Reference numeral 20 denotes the aforementioned drive voltage generation circuit, which generates liquid crystal drive voltages Vap, 2/3Vap, 1/3Vap, and zero voltage from a power supply (not shown) through analog switches 20a, 20b, 20c, and 20d such as transmission gates, respectively. The outputs of analog switches 20a and 20b, which are supplied with the liquid crystal drive voltage Vap and zero voltage, and outputs of analog switches 20c and 20d, which are supplied with 2/3 Vap and 1/3 Vap, are connected as a pair to an output gate 21, which will be described later. It is outputting. Reference numeral 22 denotes a frame signal frequency divider consisting of a JK flip-flop, which divides and outputs a frame signal in synchronization with a frame switching signal clock. 23 is an exclusive OR gate into which the signal from the frame switching signal frequency divider 2 and the drive signal are input, inverts the phase when the drive signal is input, and directly and via the inverter 24 outputs the drive voltage generation circuit 20. The drive voltage generation circuit 20 is configured to output zero voltage and 2/3 Vap or Vap and 1/3 Vap by inputting them to the control terminals of analog switches 20a, 20b, 20c, and 20d forming a pair. Reference numeral 21 denotes an output gate made up of a pair of two analog switches 21a and 21b, each of which receives voltage from the drive voltage generation circuit 20.One analog switch 21a receives the output signal from the latch circuit 19 directly. Inverters 25, 25 are connected to the other analog switch 21b.
... is inverted and input.

Next, the operation of the apparatus configured as described above will be explained based on the waveform diagrams shown in FIGS. 3 to 6 and FIG. 14.

When the frame scan switching signal is output (fifth
), the first common electrode CM ₁ latched by the latch circuit 10 via the shift register 9 (FIG. 3) becomes selected, and the common electrode CM ₂ . . .
...CM _o becomes unselected.

This frame scan switching signal is converted into a signal synchronized with the common electrode selection clock _CK1 by the frame signal frequency dividing circuit 13, and is converted into a signal synchronized with the common electrode selection clock CK1.
As a result, the drive signal is inputted to the drive voltage generation circuit 11 with its phase inverted.

Due to this reversal, for common electrode CM ₁ ,
The Vap and O voltages from the drive voltage generation circuit 11 are selected by analog switches 12a and 12b, and the Vap and O voltages are output in the first half and the second half of the selection period, respectively. 1/3 Vap in the first half of the non-selection period after common electrode CM ₁ , 2/3 in the second half
Vap voltage is output continuously. On the other hand, for the above-mentioned CM ₁ selection period of the common electrodes CM ₂ , CM ₃ . . . , 2/3 Vap, 1/3
Vap voltage is the analog switch 12a, 12b
Selected by Next, the common electrode CM ₂ is selected, the Vap voltage is applied in the first half of the selection period, and the O voltage is applied in the second half.
CM ₂ , CM ₃ , etc. are selectively scanned.

On the other hand, in the segment electrode drive circuit (FIG. 4), the data signal is passed through the exclusive OR gate 17.
The phase of the signal is inverted and input to the shift register 18. The data signal input to the exclusive OR gate by this line sequential scanning signal is input to the output gate 21 with its phase inverted. As a result of this inversion, the Vap and O voltages from the drive voltage generation circuit 20 are selected by analog switches 21a and 21b as bright inverted data signals to the segment electrodes, and the O voltage is output in the latter half and the Vap is output in the latter half. On the other hand, for the non-inverted data signal, 1/3Vap and 2/3Vap from the drive voltage generation circuit 20 are selected by analog switches 21a and 21b in synchronization with the intra-frame alternating clock signal, and in the first half of the selection period, 2/3Vap, 2/3Vap, 1/Vap is applied in the second half.

Fig. 14a shows the first frame scan, and Fig. 14b shows the second frame scan.
FIG. 10 shows a combined voltage pulse applied to a pixel combined from a scanning signal and a data signal applied to a common electrode and a segment electrode during frame scanning. In the first frame scan, a composite voltage pulse of -Vap in the first half of the selection period and Vap in the second half is applied to the pixel by the inverted data signal of the segment electrode to write a bright state, and in the second frame scan, a bright state is written. , in the first half of the selection period by the inverted data signals of the segment electrodes.
In the second half of Vap, a composite voltage pulse of -Vap is applied to the pixel to write a dark state. During the non-selection period of other scanning electrodes or the period when a non-inverted data signal of the data signal is output, an AC voltage pulse of ±1/3Vap is applied to each pixel as a composite voltage pulse.

FIG. 6 shows the waveform of the combined voltage pulse applied to the pixels combined as described above, and 1 indicates the first
Write waveform in bright state in frame scanning, 2
1 and 2 respectively show write waveforms in the dark state in the second frame scan, and the first frame scan and the second frame scan are performed alternately.

That is, in the first frame of scanning, the pixels on the first common electrode that are to be in a bright and dark state are applied with an electric field in the opposite direction to the required electric field, in this example a negative electric field, in the first half of the line sequential scanning signal. In the latter half of the line-sequential scanning signal, an electric field in the target direction, in this example a positive electric field, is applied to write a bright state. Due to this process, electric fields in both the positive and negative directions of the liquid crystal operating voltage Vap are applied to the pixels, so
The liquid crystals forming the pixels do not accumulate charge. In addition, after writing is completed in this way, as a fate of the 1/N bias method, the liquid crystal drive voltage is inevitably 1/N, in this example, 1/3Vap.
A voltage that does not exceed the threshold voltage Vth of the smectic liquid crystal is applied to the pixel, but this alternating electric field is, as shown in Figure 7,
Once the liquid crystal molecule is selected, it acts to dynamically hold the liquid crystal molecules around position b, which is slightly displaced from the selected liquid crystal molecule position a. When scanning of all the common electrodes is completed in this way, the scanning moves to the second frame and writing in the dark state is started.

That is, in the first half of the line sequential scanning signal, an electric field in the opposite direction to the required electric field, in this example, a positive electric field, is applied to the pixel on the first common electrode that is to be in a dark state, and in the second half of the line sequential scanning signal, the pixel is in a dark state. An electric field in the target direction, that is, a negative electric field, is applied to write a dark state. Needless to say, the magnitude of the positive electric field and negative electric field applied at the time of these selections, and their duration are set to values that allow sufficient movement of the liquid crystal molecules.

As described above, since a positive electric field and a negative electric field act on the pixel during this process as well, the pixel does not accumulate charge. When writing is completed in this manner, an alternating voltage of about 1/3 of the liquid crystal drive voltage Vap is applied to the pixel to dynamically maintain the selected dark state.

In addition, in the above-mentioned embodiment, the smectic liquid crystal panel was driven by the 1/3 averaging method.
Needless to say, it is not limited to this.

FIG. 8 shows another embodiment of the present invention,
The pulse width Tm of the write signal is modulated by the data signal in accordance with the display density, and according to this embodiment, the transient response characteristics of liquid crystal molecules (Figure 9) are used to display gradations. It can be carried out.

(Effects) As explained above, according to the present invention, two substrates each having a scanning electrode and an alignment film on their surfaces are made to face each other with the alignment films, and a smectic liquid crystal compound is injected into the substrates, and the spacing between the substrates is adjusted so that the smectic liquid crystal compound A smectic liquid crystal panel is constructed by limiting the pitch to the helical pitch of the molecules, and a reverse liquid crystal operating voltage is applied once during the first half of electrode selection, and a forward liquid crystal voltage is applied during the second half of electrode selection. Therefore, it is possible to prevent the generation of residual charges in the liquid crystal panel during writing, thereby improving the life of the liquid crystal and the electro-optical performance. In addition, since the write state is dynamically maintained by applying an alternating voltage lower than the liquid crystal operating voltage when not selected, the write state is maintained when not selected, regardless of the low threshold voltage of the smectic liquid crystal molecules. There is no risk of unnecessary fluctuations, the 1/N averaging bias method can be applied, and multi-division dynamic display can be performed.

[Brief explanation of the drawing]

FIG. 1 is a perspective sectional view of a device showing one embodiment of a smectate liquid crystal panel used in the present invention, FIG. 2 is a schematic diagram showing the configuration of a liquid crystal electro-optical device of the present invention, and FIGS. 3 and 4 5 and 6 are block diagrams showing an example of the common electrode drive circuit and the segment electrode drive circuit in the same device, respectively.
The figure is a waveform diagram showing the operation of the same device, and FIG.
FIG. 8 is a waveform diagram showing another embodiment of the present invention; FIG. 9 is an explanatory diagram showing transient response characteristics of liquid crystal molecules in a smectic liquid crystal panel; 10th
The figure is a schematic diagram showing the molecular arrangement of a chiral smect liquid crystal. Figures 11A and 11B are schematic diagrams showing the molecular arrangement when the cell gap is made smaller than the helical pitch of the liquid crystal molecules. , an explanatory diagram showing the relationship between the domains of a smectic liquid crystal and polarization, FIG. 13 is a characteristic diagram showing the relationship between the electric field acting on the smectic liquid crystal and optical density, and FIG. The resulting composite voltage pulse is shown. 1a... Common electrode, 1b... Uniaxial alignment film, 2
a...Segment electrode, 2b...Random horizontal alignment film, 6...Liquid crystal panel, 7...Common electrode drive circuit, 8...Segment electrode drive circuit.

Claims (1)

[Claims] 1. One substrate provided with a plurality of common electrodes on its surface and another substrate provided with a plurality of segment electrodes on its surface are arranged with a gap so that the electrodes face each other, and A chiral smect liquid crystal is sealed in the gap, and the gap is limited to a helical pitch of the chiral smect liquid crystal or less, a pixel portion is formed at each intersection of the common electrode and the segment electrode, and the common electrode is A scan signal is selected line-sequentially and supplied, and a composite voltage pulse is applied to the pixel portion based on the potential difference between the scan signal supplied to the common electrode and the data signal supplied to the segment electrodes in synchronization with the scan signal. In a chiral smect liquid crystal electro-optical device that writes bright and dark information by applying voltage, the composite voltage pulse applied to the pixel portion is divided into two parts, the first half and the second half, during the selection period of the common electrode, and bright information in the data signal is written. When writing, a composite voltage pulse having a voltage higher than the operating voltage of the chiral smect liquid crystal for writing dark information is applied to the pixel portion in the first half, and a composite voltage pulse of opposite polarity to that for writing bright information in the second half. When writing dark information in a data signal by applying a composite voltage pulse of substantially the same voltage to the pixel section, a composite voltage of a voltage higher than the operating voltage of the chiral smect liquid crystal in which bright information is written in the first half is applied. A pulse is applied to the pixel portion, and a composite voltage pulse having an opposite polarity and substantially the same voltage as the composite voltage pulse for writing dark information in the latter half is applied to the pixel portion, and the writing of the bright information and the writing of the dark information are performed. The operation voltage is lower than the operating voltage of the chiral smect liquid crystal during the non-selection period of the common electrode, and two voltages of substantially the same voltage with different polarities are applied during one scanning period. A chiral smect liquid crystal electro-optical device characterized in that a composite voltage pulse consisting of two voltage pulses is applied to a pixel portion.