JP2680392B2 - Matrix type ferroelectric liquid crystal display device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a ferroelectric liquid crystal electro-optical device, and more particularly to a matrix type ferroelectric liquid crystal display device for displaying information such as characters, figures and TV images. .

[Conventional technology]

Currently, the liquid crystal display device is TN (Twisted Nematic)
The type display method is most widely used. However, compared to other display devices (for example, a fluorescent display tube, a plasma display, etc.), it is inferior in response speed, and no significant improvement has been seen so far.

Recently, a display method using a ferroelectric liquid crystal was announced (Japanese Patent Laid-Open No. 56-107216), and in addition to its fast response speed,
It has attracted a great deal of attention because of its properties that are effective for high matrix properties such as high contrast and display memory effect.

Ferroelectric liquid crystal refers to liquid crystal exhibiting ferroelectricity. From the theory of crystal symmetry, a ferroelectric liquid crystal was first synthesized by Meyer et al. In 1975. So far, as the ferroelectric liquid crystal phase, a chiral smectic C phase, a chiral smectic I phase, a chiral smectic G phase, etc. have been discovered. ing. Here, the properties will be described using a chiral smectic C phase, which is generally most widely studied. Ferroelectric liquid crystal is a liquid crystal having a layer structure called a smectic layer, and liquid crystal molecules are inclined by an angle θ with respect to the layer normal direction. In addition, the liquid crystal molecules have a permanent dipole moment that causes spontaneous polarization in the direction perpendicular to the asymmetric atom and the molecular long axis, and the entire ferroelectric liquid crystal system has a non-racemic optically active configuration. Since the ferroelectric liquid crystal molecules have asymmetric atoms, they usually have a helical structure.
As described in JP-A-56-107216, when a cell is formed by sandwiching it between substrates having a pitch of three times or less of the spiral pitch, the spiral structure is unraveled by the effect of the wall surface of the substrate, and spontaneous polarization occurs. The two states in which are uniformly arrayed in the direction perpendicular to the substrate become stable. This is called the so-called memory effect. In these two states, the directions of spontaneous polarization are opposite to each other, and if one of the molecular long axes is inclined by θ with respect to the layer normal direction, the other is inclined by −θ. It corresponds to each. At this time, if a cell is placed between the crossed Nicols and the polarizer is made parallel to the one molecular long axis, the linearly polarized light transmitted through the polarized light passes through the liquid crystal layer as it is,
It is blocked by the analyzer and goes dark. In this state, on the other hand, the linearly polarized light transmitted through the polarizer passes through the analyzer due to the birefringence effect of the liquid crystal molecules, and a bright state is obtained. Here, when a direct current electric field is applied to the substrate in the vertical direction, the long axes of the molecules are uniformly inclined with respect to the layer normal direction by θ (or −θ) according to the property that the spontaneous polarization is oriented in the electric field direction. When a DC electric field in the opposite direction is applied, the molecules are uniformly arranged in -θ (or θ). As described above, the light / dark state can be switched according to the direction of the electric field.

When the matrix type ferroelectric liquid crystal display device utilizing the above switching principle is matrix-driven, the row electrode groups X ₁ ... X _n are normally sequentially selected and scanned in the horizontal direction shown in FIG. Then, a line sequential scanning method is used in which the "bright" or "dark" signal voltages are simultaneously applied in parallel to the vertical column electrode groups Y ₁ ... Y _m . As a specific example using this method, there is a method called a “two-field method” in which the optical response time of the ferroelectric liquid crystal is driven by voltage modulation by utilizing the strong dependence on the applied voltage.

This method will be explained in a little more detail. When a character, a figure, or the like is displayed by a combination of "bright" and "dark" of a pixel, which is an intersection of the row electrode and the column electrode, the ferroelectric liquid crystal has the special characteristic of responding to the polarity of the applied voltage as described above. The display is completed by performing two scans, one for driving the "bright" display pixels and the other for driving the "dark" display pixels. The drive voltage signal in each scan is composed of a pair of rectangular pulses, and a pulse of voltage ± V is applied to the selected pixel and a pulse of ± V / 4 is applied to the non-selected image. Here, the selected pixel is a pixel on the selected row electrode, and is a "bright" display pixel in the scan for driving the "bright" display pixel and a "dark" display pixel in the scan for driving the "dark" display pixel. Is pointing in this case. The non-selected pixels are all pixels on the row electrodes that are not selected.

[Problems to be solved by the invention]

When the matrix type ferroelectric liquid crystal display device is matrix-driven, a voltage of ± V / 4 is applied to the non-selected pixels as described above. Therefore, in order for the matrix type ferroelectric liquid crystal display device to maintain good display quality, at least ±
It is necessary that the brightness does not change even when a voltage of V / 4 is applied. That is, in the case of the two-field method, ± V / 4
Therefore, it is necessary that the light quantity does not change and becomes ± V. After all, in order to perform matrix driving, a characteristic that the light amount does not change up to a certain voltage (hereinafter referred to as threshold characteristic) is required.

In the conventional matrix type ferroelectric liquid crystal display device, no one having excellent threshold characteristics has been found, and there is a problem that the display quality is not good.

Therefore, an object of the present invention is to provide a display device of a matrix type ferroelectric liquid crystal having a good display contrast.

[Means for solving the problem]

In order to solve the above problems, in the invention according to claim 1, a ferroelectric liquid crystal is provided between both electrode substrates arranged in parallel so that n row electrodes and m row column electrodes face each other in a grid pattern. A liquid crystal cell (10) forming nm display pixels with (13) interposed, and a scanning signal is sequentially given to the n row electrodes, and a bright or dark data signal is supplied to the m column electrodes. In a matrix type ferroelectric liquid crystal display device provided with a drive control means (20 to 50) configured to perform a line-sequential scanning method of applying, the ferroelectric liquid crystal is within a certain polarity predetermined voltage range of an applied voltage. In the liquid crystal cell, the first stable state changes to the second stable state (or the second stable state to the first stable state) in response to an increase (or decrease) in the absolute value of the applied voltage, and the liquid crystal cell accordingly. -Voltage-Voltage characteristics that increase (or decrease) the amount of transmitted light Hysteresis is generated, and the first stable state to the third stable state (or the third stable state) in accordance with the increase (or decrease) of the absolute value of the applied voltage within a predetermined voltage range of the reverse polarity of the applied voltage. From the first stable state) and correspondingly increases (or decreases) the transmitted light amount of the liquid crystal cell to cause a hysteresis in the transmitted light amount-voltage characteristic, wherein the drive control means is line sequential. In a first period (first frame) in scanning, a combined signal of the scan signal and the bright data signal is combined with an erase voltage level (0V) that brings the ferroelectric liquid crystal to the first stable state. A first liquid crystal transition from a first stable state to a second stable state;
Is formed as a waveform (E ₁ , W ₁ ) having a voltage level larger in absolute value than the threshold voltage (v ₁ ) of the above, and the composite signal of the scanning signal and the dark data signal is converted into the erase voltage level (0 V ) And the first threshold voltage (v ₁ ) in absolute value
The waveform (E ₂ , W ₂ ) having the following voltage levels is formed and given, and a signal waveform (H) for holding the state of the ferroelectric liquid crystal by the synthesized signal is given as a signal following these waveforms (E ₂ , W ₂ ). In the second period (second frame), the composite signal of the scanning signal and the bright data signal is given.
A waveform having an erase voltage level (0 V) and a voltage level larger in absolute value than a second threshold voltage (v ₁ ′) for shifting the ferroelectric liquid crystal from the first stable state to the third stable state ( E ₁ ′, W ₁ ′), and the combined signal of the scan signal and the dark data signal is a voltage level equal to or lower than the second threshold voltage (v ₁ ′) in absolute value and the erase voltage level. waveform having a _{(E 2 ', W 2'} ) together to impart formed as, as a signal for subsequent thereto, imparts a signal waveform which holds a state of the ferroelectric liquid crystal by the synthesized signal (H ') It is characterized by doing so.

According to a second aspect of the present invention, in the matrix-type ferroelectric liquid crystal display device according to the first aspect, the subsequent signal in the first period (first frame) is the first threshold value in absolute value. A signal waveform having a voltage level equal to or lower than a voltage (v ₁ ) and equal to or higher than a threshold voltage (v ₃ ) for shifting the ferroelectric liquid crystal from the second stable state to the first stable state, the second period The subsequent signal in the (second frame) is equal to or lower than the second threshold voltage (v ₁ ′) in absolute value, and is a threshold value that shifts the ferroelectric liquid crystal from the third stable state to the first stable state. It is characterized in that it is a signal waveform having a voltage level higher than the voltage (v ₃ ′).

According to a third aspect of the invention, in the matrix type ferroelectric liquid crystal display device according to the first or second aspect, the erase voltage level is 0 level.

According to a fourth aspect of the present invention, in the matrix type liquid crystal display device according to any one of the first to third aspects, the erase voltage level of the ferroelectric liquid crystal is one of the second and third erase voltages. It is characterized in that it is continuously applied for a response time (t ₀ ) or more required to change to the first stable state even in the stable state.

According to a fifth aspect of the present invention, in the matrix type liquid crystal display device according to any one of the first to fourth aspects, a voltage level larger in absolute value than the first threshold voltage causes the liquid crystal to have the The first saturation voltage (v ₂ ) that brings the liquid crystal to the second stable state, and the voltage level that is larger in absolute value than the second threshold voltage has the second saturation voltage (v ₂ ) that brings the liquid crystal to the third stable state. v ₂ ′).

Note that the reference numerals and symbols in the parentheses described above show the correspondence with the specific means described in the embodiments described later.

[Action]

In the present invention thus configured, the ferroelectric liquid crystal has three stable states depending on the applied voltage level,
In switching between those states, since the applied voltage-transmitted light amount characteristic has the hysteresis characteristic as described above, the display contrast in this type of display device is premised on the clear hysteresis characteristic of the ferroelectric liquid crystal. Can be improved.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the overall structure of a matrix type ferroelectric liquid crystal display device according to the present invention. This type of display device includes a matrix type liquid crystal cell 10. The liquid crystal cell 10 has a pair of electrode substrates as shown in FIGS.
11, 12 are arranged in parallel to each other with a gap of, for example, 1 to 10 μm, and 4- (1-trifluoromethylheptyloxycarbonyl) phenyl-4 having the following structural formula is provided between the electrode substrates 11 and 12. ′ -Octyloxybiphenyl-4
-Sealing the carboxylate (hereinafter abbreviated as TFMHPOBC) 13, [4- (1- t ri f luoro m ethyl h eptyloxycarbony
l) p henyl 4'- o ctyloxy b iphenyl-4- c arboxyl
ate] Further, polarizing plates 14 and 15 each having polarization axes orthogonal to each other are attached to the electrode substrates 11 and 12 from the outside.

As shown in FIGS. 1 and 2, the electrode substrate 11 has a transparent conductive film 11b made of indium oxide or tin oxide along the inner surface of a transparent glass plate 11 and an n-shaped row electrode X.
₁ , X ₂ , ..., X _n are formed by providing a space in the vertical direction in FIG. 1 and projecting parallel to the horizontal direction in the drawing in FIG. Meanwhile electrode substrate 12 as shown in FIGS. 1 and 2, a transparent-like conductive film 12b made of indium oxide or tin oxide along its inner surface a transparent shaped glass plate 12a m-shaped column electrodes Y _1, Y ₂ , ..., Y _m are spaced from each other in the lateral direction shown in FIG.
X _1, X _2, ..., it is constructed by projecting formed so as to be perpendicular to each other in X _n.

Further, polymer films 16 and 17 made of polyimide, polyamide or the like are attached to the inner surfaces of the conductive films 11b and 12b, and the ferroelectric liquid crystal molecules 1
Polymer film 16 so that 3a is oriented parallel to electrode substrates 11 and 12.
The inner surface of 17 is rubbed. As a means for orienting the ferroelectric liquid crystal molecules, an oblique vapor deposition treatment method of silicon oxide or the like may be used instead of the rubbing treatment of the polymer film. In such a case, the ferroelectric liquid crystal in the liquid crystal cell 10
In sealing 13, the rubbing direction of the polymer films 16 and 17 is first parallel to the center line that passes through the center of the distance between the inner surfaces of the conductive films 11b and 12b and is parallel to the conductive films 11b and 12b. The two electrode substrates 11 and 12 are combined in parallel so that After that, the ferroelectric liquid crystal 13 is heated to be injected as an isotropic liquid phase between the electrode substrates 11 and 12 by utilizing the capillary phenomenon, and the entire liquid crystal cell 10 is heated to about 0.1 to 1 ° C. per minute. Then, the ferroelectric liquid crystal 13 is cooled until it becomes a smectic C ^* phase.

As a result of such cooling, the ferroelectric liquid crystal 13 in the smectic layer form is oriented along the rubbing direction of the polymer films 16 and 17, but as shown in FIG.
c is bent in the shape of "ku". The molecular arrangement in which a stable state is established depending on the electric field of the ferroelectric liquid crystal molecules 13 and its direction at this time will be described with reference to FIG. In the figure, the liquid crystal cell
The view seen from the direction of 10 normal lines and the cross-sectional perspective view thereof are shown in correspondence with each other. First, FIG. 3 (a) shows a stable liquid crystal molecule alignment in the absence of an electric field. Liquid crystal molecule 13a
The molecular long axis of is almost parallel to the rubbing direction,
In the upper half of the liquid crystal cell 10, the spontaneous polarization 13b is oriented rightward (or leftward), and in the lower half the spontaneous polarization 13b is oriented leftward (or rightward). Immediately, if the liquid crystal molecules 13a are represented on an orbit 13d (usually called a smectic cone) moved by an electric field, the liquid crystal molecules 13a are located in the lower half of the upper half of the liquid crystal cell 10 and in the upper half of the lower half, and the smectic layer 13c is formed. It is divided by the bent part in the shape of "ku". If this state is observed between orthogonal Nicols, the extinction position is observed.

Next, when an electric field is applied between the electrode substrates 11 and 12 of the liquid crystal cell 10 (from the bottom to the top in the sectional view of FIG. 3B), the liquid crystal molecules 13a are spontaneously polarized. Since the direction of 13b is aligned with the direction of the electric field, the molecular long axis is deviated from the orientation direction of FIG. 3 (a) by an angle θ, that is, the spontaneous polarization 13b is upward and is located on the right side of the smectic cone 13d. The state in which it does becomes a stable state. Further, when an electric field in the opposite direction is applied, the molecular long axis is deviated by an angle −θ in the direction opposite to that in FIG. 3 (b) for the same reason as described above in FIG. The state in which the polarization 13b is facing downward and is located on the left side of the smectic cone 13d is the stable state. When the states of FIGS. 3 (b) and 3 (c) are also observed between the orthogonal Nicols as in the case of FIG. 3 (a), the extinction properties are observed at positions offset by an angle 2θ.

Here, the polarization axes of the polarizing plates 14 and 15 attached to the liquid crystal cell 10 are determined as follows. The polarization axis of the polarizing plate 15 is shown in FIG. 3 (a).
Is parallel to the long axis of the molecule (dotted line arrow P shown in FIG. 3 (a)), and the polarization axis of the polarizing plate 14 is orthogonal to this (FIG. 3 (a)).
The solid arrow A) shown in FIG.

In such a case, the light transmission of the three stable states is described by the following equation.

Here, I is the intensity of transmitted light, I ₀ is a constant determined by the transmittance of the polarizing plate, θ ₀ is the angle between the polarization axis of the polarizing plate 15 and the long axis of the liquid crystal molecule (θ _{0 in} (a) of FIG. 3). = 0, in (b) θ ₀ = θ,
In (c), θ ₀ = −θ. In the case of TFMHPOBC, θ = 11 to 31 °, which changes with temperature. ) Δn is the difference in the refractive index of the liquid crystal between ordinary light and extraordinary light, d is the substrate gap of the liquid crystal cell, and λ is the wavelength. As you can see from this formula,
It is easily recognized that the light is not transmitted in the figure (a) and shows “dark”, and the light is transmitted and the “bright” is shown in FIGS. 3 (b) and 3 (c).

The relationship between the transmitted light intensity and the voltage applied to the liquid crystal cell 10 was measured by an experiment. The result is shown in FIG. The horizontal axis in FIG. 4 indicates the applied voltage, which is positive in the direction of the electric field shown in FIG. 3 (b) and negative in the direction shown in FIG. 3 (c). The vertical axis is the relative transmitted light intensity. When the positive applied voltage is increased to the state of FIG. 3 (a) without electric field, the threshold value v ₁ is increased due to the competition between the torque and the elastic torque based on the product of the electric field E and the spontaneous polarization P _s.
Then, the liquid crystal molecules arranged in the state of FIG. 3 (a) start to invert along the smectic cone 13d, and the saturation voltage v
_When it exceeds ₂ , the state shown in FIG. As a result, the transmitted light intensity also changes, and eventually switches from “dark” to “bright”. Here, the threshold voltage is defined as a voltage at which the transmitted light intensity changes by 10% from the initial value, and the saturation voltage is defined as a voltage at which the transmitted light intensity changes by 90%.

On the contrary, when the applied voltage is decreased from v ₂ or higher, the same change as when the voltage is increased does not occur, but shows hysteresis. That is, the threshold value
With v _{3, the} molecule starts to invert from the state of Fig. 3 (b),
The saturation voltage v ₄ changes the state to that shown in FIG. Along with this, the transmitted light intensity also changes, and eventually "bright" to "dark"
Switching to Similarly, when a voltage of opposite polarity is applied, hysteresis is similarly exhibited, and the state of FIG. 3 (a) and the state of FIG. 3 (c) change, and “dark” changes to “bright” and “bright” changes to “dark”. Change to “” and have thresholds v ₁ ′, v ₃ ′ and saturation voltage v ₂ ′, v ₄ ′, respectively. The present invention makes effective use of this characteristic.

The intersection of each of the row electrodes X ₁ , X ₂ , ... X _n and each of the column electrodes Y ₁ , Y ₂ , ... Y _m is displayed in each display pixel together with each ferroelectric liquid crystal portion present in each of these intersections. (1,1),… (1, m), (2,
1), ... (n, m) are constructed (see FIG. 1). When a proper polarity voltage is applied between the row electrode and the column electrode, the display pixel is in a state of transmitting light (that is, a bright display state) in a molecular orientation state that the ferroelectric liquid crystal can assume, , When a proper value below the threshold value is applied between the row electrode and the column electrode, the display pixel does not transmit light (that is, the dark display state) in the molecular alignment state that the ferroelectric liquid crystal can assume. The polarization axes of the polarizing plates 14 and 15 are defined in relation to the molecular long axis of the ferroelectric liquid crystal. A light source that projects light onto the polarizing plate 15 is arranged behind the polarizing plate 15.

As shown in FIG. 1, the liquid crystal display device includes a line sequential scanning circuit 20, a reference signal generating circuit 30 connected to the line sequential scanning circuit 20, a line sequential scanning circuit 20, and a reference signal generating circuit.
A line driving circuit 40 and a column driving circuit 50 connected to 30 are provided, and the line-sequential scanning circuit 20 is composed of a ROM 21 and a controller 22 connected to the ROM 21. ROM21 is
Display data representing predetermined display contents to be displayed on the liquid crystal cell 10 is stored in advance. The controller 22 sequentially generates the reference clock pulse a (Fig. 8a), sequentially generates the synchronization pulse b (Fig. 8b) having a cycle three times as long as the reference clock pulse a, and inverts every frame. Pulse c (Fig. 8c) is generated in sequence and shift clock pulse
Sk is sequentially generated, the column electrode display data from the ROM 21 is sequentially generated as the data pulse Py, and the row electrode data is sequentially generated as the data pulse Px.

As shown in FIG. 5, the reference signal generating circuit 30 includes an inverter 31 connected to the controller 22 and a D-type flip-flop 3 connected to the controller 22 and the inverter 31.
The inverter 31, which has 2, 33 and 34, sequentially inverts the synchronization pulse b from the controller 22 and outputs an inversion gate pulse. In the flip-flops 32, 33, 34, the output terminal of the flip-flop 34 and the data input terminal of 32 are
32 output terminals and 33 data input terminals
34 input terminals are connected to each
Is preset or cleared when the inversion gate pulse from the controller 22 is at a low level, outputs high, low, and low levels, respectively, and is synchronized with the rising edge of the reference clock pulse a from the controller 22.
The output is shifted in the order of 3,34, and the reference signal from the flip-flop 32 (Fig. 8d) and the reference signal from 33 (Fig. 8e).
A reference signal f (FIG. 8f) is generated from 34.

The row drive circuit 40 includes a controller 22 and a controller 22.
Shift register 40A connected to the
And logic circuits 40B1 and 40B connected to the shift register 40A
, ..., 40Bn, and the shift register 40A sequentially receives the synchronization pulse b from the controller 22 as a shift pulse, and synchronizes with the shift pulse, receives each data pulse Px from the controller 22 in each logic circuit. Data pulses g (FIG. 8g) are sequentially shifted to any of 40B1 to 40Bn from the logic circuit 40B1 to the logic circuit 40Bn.

As shown in FIG. 6, the logic circuit 40B1 includes a D type latch 41 connected to the shift register 40A and the controller 22.
c, inverter 41a connected to shift register 40A, latch 4
It includes an inverter 41b and a shift register 40A connected to 1c, a controller 22, AND gates 42a, 43a, 44a, 45a, 46a, 47a and 48a connected to the inverters 41a and 41b.

The D type latch 41c inputs the data pulse g from the shift register 40A to the G terminal and the frame pulse c from the controller 22 to the D terminal, and outputs the frame pulse c as it is from the Q terminal when the G terminal input is at a high level. Then, when the G terminal input becomes low level, the D terminal input signal level at the fall of the G terminal input signal is held and output from the Q terminal to generate the gate pulse c '. Inverter 41a
Inverts the data pulse g from the shift register 40A to generate an inverted data pulse. Inverter 41b
Inverts the gate pulse c'from the D-type latch 41c to generate an inverted gate pulse.

The AND gate 42a generates a gate pulse h (FIG. 8h) at a high level when the data pulse g from the shift register 40A, the gate pulse c'from the D type latch 41c, and the reference signal f are all at a high level. To do. The AND gate 43a generates a gate pulse f (FIG. 8f) at a high level when the data pulse g from the shift register 40A, the gate pulse c'from the D type latch 41c, and the reference signal e are all at a high level. . The AND gate 44a generates the gate pulse j (j in FIG. 8) at the high level when the data pulse g from the shift register 40A and the reference signal d are both at the high level. The AND gate 45a is a shift register 40A.
, The inversion gate pulse from the inverter 41b and the reference signal f are all at the high level, the gate pulse k (FIG. 8k) is generated at the high level. AND
The gate 46a receives the data pulse g from the shift register 40A.
Also, when the inverted gate pulse from the inverter 41b and the reference signal e are all at the high level, the gate pulse 1 (FIG. 8) is generated at the high level. The AND gate 47a generates the gate pulse m (FIG. 8m) at the high level when both the inverted data pulse from the inverter 41a and the gate pulse c'from the D type latch 41c are at the high level. The AND gate 48a generates a gate pulse n (n in FIG. 8) at a high level when both the inversion gate pulse from the inverter 41a and the inversion gate pulse from the inverter 41b are at a high level.

The transmission gate 44b shifts the gate pulse j to a zero level (that is, the ground level) in response to the gate pulse j from the AND gate 44a, and the scan signals S ₁ and S ₁ ′ (the eighth level) having the zero level. As shown in FIG. O and FIG. 9), it is generated from a common output terminal 49 with each transmission gate and applied to the row electrode X ₁ of the liquid crystal cell 10.

Further, the transmission gate 43c is the AND gate 43
In response to the gate pulse 1 from a, the gate pulse 1 is shifted to the level of (V ₀ −V ₁ ) based on the positive constant voltage (V ₀ −V ₁ ) from the constant voltage circuit 43b, and The transmission gate 42c responds to the gate pulse h from the AND gate 42 by sending the gate pulse h to the constant voltage circuit 42.
Based on the positive constant current (V ₀ + V ₁ ) from b, shift to the level of (V ₀ + V ₁ ). Therefore, the shift results of both transmission gates 43c and 42c are combined and generated as a scanning signal S ₂ (see FIGS. 8 and 9) from the common output terminal 49 of each transmission gate, It is applied to the row electrode X ₁ of the cell 10.

Similarly, transmission gates 47c, 46c, 45c, 48
c responds to the gate pulses m, l, k, and n from the AND gates 47a, 46a, 45a, and 48a, respectively, in response to the respective constant voltage circuits 47b.
(V ₀ ), 46b (− (V ₀ −V ₁ )), 45b (− (V ₀ + V ₁ )), 48b
Based on (-V ₀ ), scanning signals S ₃ , S ₂ ′, S ₃ ′ (see FIGS. 8 and 9) having the respective voltage levels are generated from the common output terminal 49 with each transmission gate. , To the row electrode X ₁ of the liquid crystal cell 10. In such a case, in the first frame, both the scanning signals S _1, S ₂ functions as a selection signal for selecting the row electrodes X _1, scanning signal S ₃ 'until the row electrodes X ₁ is selected, The post-selection scanning signal S ₃ functions as a non-selection signal for T / n, respectively (in the case of the row electrode X ₁ , the scanning signal S ₃ is the non-selection signal because it is selected at the beginning of the frame). However, T represents one frame display time. In the second frame, both scanning signals
S ₁ ', S _2' functions as a selection signal for selecting the row electrodes X _1, it is between the scanning signal S ₃ to the row electrodes X ₁ is selected,
The post-selection scanning signal S ₃ ′ functions as a non-selection signal for T / n, respectively (in the case of the row electrode X ₁ as in the first frame, only the scanning signal S ₃ ′ becomes a non-selection signal). The logic circuits 40B2 to 20Bn are both configured similarly to the logic circuit 40B1, and each of these logic circuits 40B2 to 40Bn is
In response to each data pulse g from the shift register 40A, frame pulse c from the controller 22 and each gate pulse d, c, f from the reference signal generating circuit, each scanning signal S ₁ , _{S 2, S 3, S 1} ', S 2' results respectively, and S ₃ '. Therefore, in the first frame, the scanning signals from the logic circuit 40B2 are both the scanning signals S ₁ and S ₂ as selection signals, and the scanning signals S ₃ ′ and S _{3 are} before selection of the row electrode X _2.
The latter non-selection signal is applied to the row electrode X ₃ of the liquid crystal cell 10, respectively. Similarly, in the first frame, the scanning signals from the logic circuit 40Bn are both scanning signals S ₁ and S ₂ as selection signals, and S ₃ ′ and S ₃ are before and after the row electrode X _n selection. , And both scanning signals S ₁ ′ and S ₂ ′ are selection signals in the second frame, and scanning signals S ₃ · S
₃ ′ is applied to the row electrode X _{n of the} liquid crystal cell 10 as a non-selection signal before and after the selection of the row electrode X _n .

The column drive circuit 50 includes a controller 22 and a controller 22.
Shift register 50A and latch 50B connected to each, and each logic circuit 50c1, connected to the reference signal generation circuit 30 and latch 50B
.., 50 cm, the shift register 50A sequentially receives serial data pulses Py from the controller 22 in response to the shift clock pulse Sk from the controller 22, and outputs m parallel data. It is repeatedly converted into a pulse and applied to the latch 50B. The latch 50B repeatedly latches each of the m data pulses from the shift register 50A in response to the synchronization pulse b from the controller 22 to form a data pulse p (FIG. 8p) in each of the logic circuits 50c1 and 50c.
2, ..., 50cm respectively.

As shown in FIG. 7, the logic circuit 50c1 includes an EXCLUSIVE-OR gate 51 connected to the latch 50B and the controller 22.
And an inverter 52 connected to the EXCLUSIVE-OR gate 51
Connected to the inverter 52 and the reference signal generation circuit 30
An AND gate 53a, an AND gate 53b connected to the EXCLUSIVE-OR 51 and the reference signal generation circuit 30, and an OR gate 53c connected to both AND gates 53a and 53b are provided.

The EXCLUSIVE-OR 51 takes the exclusive OR of the latch data pulse D from the latch 50B and the frame pulse c from the controller 22 to generate a gate pulse q (8th q). The AND gate 53a generates a gate pulse at a high level in response to the reference signal e from the reference signal generating circuit 30 while the q inversion gate pulse from the inverter 52 is at a high level, and also the q inversion gate. A gate pulse is generated at a low level when the pulse is at a low level. AND gate 53b
Generates a gate pulse at a high level in response to the reference signal f from the reference signal generating circuit 30 when the gate pulse q from the EXCLUSIVE OR51 is at a high level, and gates at a low level when the gate pulse q is at a low level. Generate a pulse. The OR gate 53c is one of the AND gates 53a and 53b.
When at least one of them is at the high level, the gate pulse r (FIG. 8r) is generated at the high level. NOR gate 54 is OR
Gate pulse r from gate 53c and reference signal generation circuit 3
When the reference signals d from 0 are both at the low level, they respond at the high level to generate the gate pulse s (FIG. 8s).

The transmission gate 56 includes a reference signal generating circuit 30.
Both gate pulses are shifted to a zero level (that is, the ground level) in response to the reference signal d from the respective transmission gates as data signals D1 and D1 '(see FIGS. 8 and 9) having a zero level. It is generated from the output terminal 58 common to 55b and 57b, and is applied to the column electrode Y ₁ of the liquid crystal cell 10.

Further, when the transmission gate 55b receives the gate pulse s from the NOR gate 54 and the transmission gate 57b receives the gate pulse r from the OR gate 53c, the transmission gate 55b sends the gate pulse s to the positive constant voltage from the constant voltage circuit 55a. with shifts to the level of the voltage (V _2), the transmission gate 57b shifts the gate pulse r to the level of the constant voltage circuit 57a umbrella negative constant voltage (-V _2). Therefore, such two transmission gates 55b, 57 b shifts the result of being synthesized, the data signal D _2, D ₃ and D ₂ ', D _3' (FIG. 8 O and ninth
Liquid crystal cell 10
To the column electrode Y ₁ . In such a case, in the first frame, both data signals D ₁ and D _{2 function} as ON data signals for the column electrode Y ₁ , and both data signals D ₁ and D ₃ function as OFF data signals during T / n. In the second frame, both data signals D ₁ ′ and D ₂ ′ are O for the column electrode Y ₁ .
As N data signals, both data signals D ₁ ′ and D ₃ ′ function as OFF data signals during T / n.

The remaining logic circuits 40C2-40Cm are both configured similarly to the logic circuit 40C1, and each of these logic circuits 40C2-40Cm is
In response to each data pulse from the latch 50B, the frame pulse c from the controller 22 and each gate pulse d, e, f from the reference signal generating circuit, like the logic circuit 40C1,
Produces respective data signals D ₁ , D ₂ , D ₃ , D ₁ ′, D ₂ ′ and D ₃ ′, respectively. Then, both data signals D ₁ and D from the logic circuit 40C2 are
₂ and both data signals D ₁ and D ₃ are ON data signals and OFF data signals in the first frame, and both data signals D ₁ ′ and D ₂ ′ and both data signals D ₁ ′ and D ₃ ′ are In the second frame, the ON data signal and the OFF data signal are applied to the column electrode Y ₂ of the liquid crystal cell 10, respectively. Logic circuit 40C3
Both data signals D ₁ and D ₂ and both data signals D ₁ and D ₃ are ON data signals and OFF data signals in the first frame, and both data signals D ₁ ′, D ₂ ′ and both data signals D
₁ ′, D ₃ ′ are ON data signal and OF in the second frame.
The F data signal is applied to the column electrode Y ₂ of the liquid crystal cell 10, respectively. Similarly, both data signals D ₁ and D ₂ and both data signals D ₁ and D ₃ from the logic circuit 40Cm are ON data signals and OFF data signals in the first frame, and both data signals D ₁ ′, D ₂ ′ and both data signals D ₁ ′ and D ₃ ′ are the second
In the frame, the ON data signal and the OFF data signal are applied to the column electrodes Y _m of the liquid crystal cell 10, respectively.

Here, the constant voltage (V ₀ + V
₁ ), constant voltage from constant voltage circuit 43b (V ₀ −V ₁ ), constant voltage from constant voltage circuit 45 b − (V ₀ + V ₁ ), constant voltage from constant voltage circuit 46 − (V ₀ −V _1). ), The constant voltage V ₀ from the constant voltage circuit 47b,
A method for determining the constant voltage −V ₀ from the constant voltage circuit 48b, and the constant voltage V ₂ from the constant voltage circuit 55a and the constant voltage −V ₂ from the constant voltage circuit 57a in FIG. 7 will be described. When a proper voltage is applied to the display pixel (n, m) in the dark display state to change it to the bright display state, the transmitted light amount of the display pixel (n, m) changes to 90% or more of the total change after the voltage is applied. And the response time of the ferroelectric liquid crystal 13 when an appropriate voltage is applied to the display pixel (n, m) in the bright display state to change it to the dark display state. Let t _{0 be} the time of and the set signal width of the scanning signals S ₁ , S ₁ ′ and the data signals D ₁ , D ₁ ′. Then, the signal widths of the scans S ₂ , S ₂ ′ and the data signals D ₂ , D ₂ ′, D ₃ , D ₃ ′ are set to 2t ₀ . At this time, in order to obtain a good contrast in relation to the applied voltage-transmitted light intensity characteristic curve of FIG. 4, the following equations (2) to (4)
Are determined so as to satisfy the following.

| V ₀ | = {(| v ₁ | + | V ₃ |) / 2 + (| v ₁ ′ | + | V ₃ ′ |) / 2} / 2 (2) | V ₂ | ≦ (| v ₁ | − | V ₃ |) / 2, (| v ₁ ′ | − | V ₃ ′ |) / 2 (3) | V ₀ | + | V ₁ | + | V ₂ |> | v ₂ |, | v ₂ ′ | (4) The application time of the ferroelectric liquid crystal 14 is ± (V ₀ + V 1 + V ₂ ).
Is the response time when the voltage is applied.

In the present embodiment configured as described above, the line-sequential scanning circuit 20 uses the reference clock pulse a and the synchronization pulse b, the frame pulse c, the shift clock pulse Sk, and the data pulse Px.
And the data pulse Py are sequentially generated, and the reference signal generation circuit 30 sequentially responds to the reference clock pulse a and the synchronization pulse b to generate the reference signals d, e and f at the respective timings shown in FIG. , Row drive circuit
In response to the synchronizing pulse b, the frame pulse c and the data pulse Px from the line-sequential scanning circuit 20 and the reference signals d, e and f from the reference signal generating circuit 30, a selection signal (both scanning) Signals S ₁ and S ₂ ) or a non-selection signal (scanning signal S ₃ or S ₃ ′), and a selection signal (both scanning signals S ₁ ′ and S ₂ ′) or a non-selection signal (scanning signal) in the second frame. S ₃ ′ or S ₃ ) is applied to any of the row electrodes X _{1 to} X _n of the liquid crystal cell 10 while being shifted by T / n from the row electrode X ₁ to the row electrode X _n . On the other hand, the column driving circuit 50 responds to the synchronizing pulse b, the frame pulse c, the shift clock pulse Sk and the data pulse Py from the line sequential scanning circuit 20 and the reference signals d, e and f from the reference signal generating circuit 30. , ON data signal (both data signals D ₁ and D ₂ ) or O in the first frame
The FF data signal (both data signals D ₁ and D ₃ ) is an ON data signal (both data signals D ₁ ′ and D ₂ ′) or O in the second frame.
The FF data signal (both data signals D ₁ ′, D ₃ ′) is transferred to the liquid crystal cell 1
The column electrodes Y _{1 to} Y _m of 0 are repeatedly applied.

In such a configuration, the liquid crystal cell 10 has the row drive circuit 40.
The display pixels (1,1) and (1,2) will be described as an example of how the matrix driving is performed by the column driving circuit 50. Here, for simplicity, the first frame and the second frame
It is assumed that the same display is performed in the frame. For example, in the first frame, the row driving circuit 40 applies a selection signal (both scanning signals S ₁ and S ₂ ) to the row electrode X ₁ , and the column driving circuit 40
50 is an ON data signal to column electrode Y ₁ (both data signals D ₁ and D ₂ )
Is added, the display pixel (1,1) functions as a bright display pixel (see FIG. 11). In this case, row electrode X ₁ and column electrode
An erase signal E ₁ (FIG. 12 (a)) obtained by synthesizing the scan signal S ₁ and the data signal D ₁ is applied to Y ₁ for t ₀ , and the scan signal S ₂ and the data signal D _{2 are} added. Write signal by combining with
W ₁ (Fig. 12 (a)) is added for 2t ₀ .
However, the erase signal E ₁ has one write signal W ₁ is 0V, the signal width _{t 0 (V 0 -V 1 -V} 2) level and the signal width t ₀ of _{(V 0 + V 1 + V} 2) Level Have.

Then, the display pixel (1,1). Based on the level (0V) of the erasing signal E ₁ and the signal width t ₀ , a dark display state (arranged state of FIG. 3 (a)) is once obtained, and then the state of the write signal W ₁ of FIG. 3 (b). Changes to saturation voltage v ₂ or higher level (V ₀ +
Based on V ₁ + V ₂ ) and the signal width t ₀ , a bright display state (arranged state of FIG. 3B) is obtained. After T / n, the row drive circuit 40
3 (b) by synthesizing the non-selection signal from the column driver and the ON data signal (or the OFF data signal) from the column driving circuit 50.
Threshold voltage v ₃ of the change from the state of Fig.
The holding signal H (FIG. 12 (a)) having the above level is applied to the display pixel (1,1) to hold the bright display state. A series of these states is shown by the change in transmitted light intensity in FIG.

Also in the second frame, similarly, the row drive circuit 40 applies a selection signal (both scanning signals S ₁ ′ and S ₂ ′) to the row power X ₁ , and the column drive circuit 50 outputs an ON data signal (both data) to the column electrode Y _1. signal
When D ₁ ′ and D ₂ ′ are added, the display pixel (1,1) functions as a bright display pixel (see FIG. 11). In such a case, the same reason as described in the first frame is used, and this time, the bright display state is realized by utilizing the change between FIG. 3 (a) and FIG. 3 (c). That is, the erase signal E ₁ ′ (see FIG. 12 (a)) obtained by synthesizing the scan signal S ₁ ′ and the data signal D ₁ ′ is applied for t _{0 and the} scan signal S ₂ ′ and the data signal D ₂ ′ are given. The write signal W ₁ ′ (FIG. 12 (a) 9 is given for 2t ₀ by the combination with and). However, the erase signal E ₁ ′ is 0V, while
Write signal W ₁ 'is a signal width t ₀ - has a level of _{(V 0 + V 1 + V} 2) - (V 0 -V 1 -V 2) level and signal width t ₂ of the.

Then, the display pixel (1,1) once enters the dark display state (the arrangement state of FIG. 3 (a)) based on the level (0V) of the erase signal E ₁ ′ and the signal width t ₀ . Third of built-in signal W ₁ ′
Level above saturation voltage V ₂ ′ that changes to the state of FIG.
(V ₀ + V ₁ + V ₂ ) and signal width t ₀ based on the bright display state (3rd
The arrangement state of FIG. Row drive circuit 4 after T / n
FIG. 3 (c) by combining the non-selection signal from 0 and the ON data signal (or OFF data signal) from the column driving circuit 50.
Threshold voltage of the change from the state of Fig.
Hold signal H'having a level below v ₃ '(FIG. 12 (a)
Reference) is added to the display pixel (1, 1) to maintain the bright display state. Here, the non-selection signal applied to each X electrode is
From sequential S ₃ each time the selection signal is applied changes to S ₃ '.
A series of these states is shown by the change in transmitted light intensity in FIG.

Further, a case where a dark display state is realized will be described.
OFF data signal (both data signals D ₁ and column driver circuit 50 to the column electrode Y ₂ together with the row drive circuit 40 in the first frame to impart a selection signal (both scanning signals S ₁ and S ₂₎ to the row electrodes X ₁ When D ₃ ) is added, the display pixel (1, 2) functions as a dark display pixel (see the shaded area in FIG. 11).

In such a case, the scanning signal is applied between the row electrode X ₁ and the column electrode Y _2.
An erase signal E ₂ (FIG. 12 (c)) obtained by combining S ₁ and data signal D ₁ is given for t ₀ , and a write signal W _{2 obtained} by combining scan signal S ₂ and data signal D ₃ and thus applied between 2t _0. However, the erase signal E ₂ is on the other hand a 0V, write signal W ₂ in level and the signal width t ₀ of the signal width _{t 0 (V 0 -V 1 +} V 2) ( V ₀ +
V ₁ −V ₂ ) level.

Thus, the display pixel (1,2) of the erase signal E ₂ levels (O
V) and the signal width t ₀ , a dark display state (arranged state of FIG. 3 (a)) is reached, and thereafter, at each write signal W ₂ and signal width t ₀ , the level (V ₀ −V ₁ + V ₂ ) And (V ₀ + V ₁ −V ₂ ) are below the threshold voltage v ₁ of the change from the arrangement of FIG. 3 (a) to the arrangement of FIG. 3 (b), Keep the state,
After all, the dark display state is realized. After T / n, the holding signal H is applied in the same manner as described above, but since the voltage levels are all V ₁ or less, the dark display state is held.

Similarly in the second frame, the row drive circuit 40 applies a selection signal (both scanning signals S ₁ ′ and S ₂ ′) to the row electrode X ₁ and the column drive circuit 50 supplies an OFF data signal (both data) to the column electrode Y _2. Signal D
_{When 1} ′ and D ₃ ′) are added, the display pixel (1, 2) functions as a dark display pixel (see the shaded area in FIG. 11). Even in such a case, the dark display state is realized by the same reason as described in the first frame. That is, the scan signal S ₁ ′ and the data signal D ₁ ′
Erase signal E ₂ by synthesis and 'together (Figure 12 (c)) is applied between t _0, the scanning signal S _2' 'write signal W ₂ by synthesis and' (12 a data signal D ₃ The figure (c)) is added during 2t ₀ . However, while the erase signal E ₂ ′ is 0 V, the write signal W ₂ ′ is − (V ₀ −V ₁ + V ₂ ) level and − of the signal width t _0.
And a level of (V ₀ + V ₁ −V ₂ ).

Therefore, the display pixel (1, 2) is in a dark display state (FIG. 3 (a)) based on the level (0V) of the erase signal E ₂ 'and the signal width t ₀ .
Since the level of the write signal W ₂ ′ after reaching the state of (1) is smaller than the threshold voltage v ₁ ′ of the change from FIG. 3A to FIG. The state is maintained.
After T / n, the non-selection signal from the row drive circuit 40 and the ON data signal (or OFF data signal) from the column drive circuit 50
A holding signal H ′ is added to the display pixel (1, 2) by the combination of the above, but both of them have a threshold voltage v ₁ ′ of the change from the state of FIG. 3A to the state of FIG. Since it is below, the dark display state is maintained. Here, in the non-selection signal applied to each X electrode, S ₃ sequentially changes to S ₃ ′ every time the selection signal is applied. A series of these states is shown by the change in transmitted light intensity in FIG.

Further, other display pixels are similarly driven, and as a result, the liquid crystal cell 10 is matrix-driven.

Note that FIG. 10 shows the timing of electrodes applied to the row electrodes and the column electrodes.

In the examples of the present invention, TFMHPOBC was used as the ferroelectric liquid crystal, but any compound may be used as long as it exhibits the above-mentioned three stable states and has the above-mentioned hysteresis. (TFMNPOBC, MHPOBC, TFMHB2FDB) may be used.

(1) TFMNPOBC [4- (1- t ri f luoro m ethyl n onyloxycarbony
l) p henyl 4'- o ctyloxy b iphenyl-4- c arboxyl
ate] (2) MHPOBC [4- (1- m ethyl h eptyloxycarbonyl) p henyl
4'- o ctyloxy b iphenyl-4- c arboxylate ] (3) TFMHB2FDB [4- (1- t ri f luoro m ethyl h eptyloxycarbony
l) -4'- b iphenyl 2- f luoro -4-decyloxy b en
zoate] Furthermore, a mixture of a plurality of liquid crystals at a predetermined ratio can be used as well.

Further, in implementing the present invention, the voltage polarity is reversed for each frame, but even if it is reversed for every plural frames,
It can be set freely if no substantial DC component remains in the liquid crystal cell.

In implementing the present invention, the liquid crystal cell 10 is not limited to the transmissive type, but may be the reflective type.

〔The invention's effect〕

As described above, the ferroelectric liquid crystal 13 is applied with the applied voltage −
When matrix driving is performed to clarify the bright display state and the dark display state of each pixel of the liquid crystal cell 10 by using the hysteresis represented by the transmitted light intensity characteristic, each row electrode X ₁ , ... X _n
This can be realized by simply giving a simple waveform change in relation to the applied voltage-transmitted light intensity characteristic to the scanning signal to be applied to the column electrode and the data signal to be applied to each column electrode Y ₁ , ... Y _m . Therefore, it is possible to greatly improve the contrast of this type of display device on the assumption that there are three stable states due to the applied voltage of the ferroelectric liquid crystal and the hysteresis characteristic.

[Brief description of the drawings]

1 is an overall configuration diagram showing an embodiment of the present invention, FIG. 2 is an enlarged sectional view of a liquid crystal cell in FIG. 1, FIG. 3 is a diagram showing an alignment state of liquid crystal molecules in FIG. 2, and FIG. FIG. 5 is a diagram showing the relationship between the light transmittance of the ferroelectric liquid crystal and the applied voltage, FIG. 5 is a detailed configuration diagram of the reference signal generation circuit in FIG. 1, and FIG. 6 is a logic in the row drive circuit in FIG. FIG. 7 is a detailed block diagram of the circuit, FIG. 7 is a detailed block diagram of the logic circuit in the column driving circuit in FIG. 1, and FIGS. 8, 9, and 12 are for explaining the operation of the embodiment shown in FIG. FIG. 10 is a signal waveform diagram, FIG. 10 is a diagram showing timing of signals applied to the liquid crystal cell, and FIG. 11 is a partially enlarged view of row electrodes and column electrodes. 10 ... Liquid crystal cell, 11, 12 ... Electrode substrate, 13 ... Ferroelectric liquid crystal, 20 ... Line sequential scanning circuit, 21 ... ROM, 22 ... Controller, 30 ... Reference signal generation circuit, 40 ... … Row drive circuit,
50 …… Column drive circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kaoru Mori 1-1, Showa-cho, Kariya, Aichi Prefecture, Nippon Denso Co., Ltd. (72) Inventor, Yuichiro Yamada 1-1-chome, Showa-cho, Kariya, Aichi Nippon Denso (72) Inventor Takashi Hagiwara 2-7-3 Marunouchi, Chiyoda-ku, Tokyo Showa Shell Sekiyu KK (72) Inventor Yoshikazu Suzuki 2-3-7 Marunouchi, Chiyoda-ku, Tokyo Showa Shell Sekiyu KK ( 72) Inventor Ichiro Kawamura 2-7-3 Marunouchi, Chiyoda-ku, Tokyo Within Showa Shell Sekiyu KK

Claims (5)

(57) [Claims] 1. A display device of nm number is formed by interposing a ferroelectric liquid crystal between both electrode substrates arranged in parallel so that n row electrodes and m row column electrodes face each other in a grid pattern. Sequential scanning signals are applied to the liquid crystal cell and the n row electrodes,
In a matrix type ferroelectric liquid crystal display device including a drive control unit configured to perform a line-sequential scanning method for applying a bright or dark data signal to the row column electrodes, the ferroelectric liquid crystal is an applied voltage. Within a predetermined voltage range of one polarity, the first stable state changes to the second stable state (or the second stable state to the first stable state) in response to an increase (or decrease) in the absolute value of the applied voltage. And, in accordance therewith, a hysteresis is generated in the transmitted light amount-voltage characteristic that increases (or decreases) the transmitted light amount of the liquid crystal cell, and the absolute value of the applied voltage increases (or decreases) within the predetermined voltage range of the reverse polarity of the applied voltage. ) According to the first stable state to the third stable state (or from the third stable state to the first stable state), and correspondingly increase (or decrease) the amount of light transmitted through the liquid crystal cell. Transmitted light In the first period of the line-sequential scanning, the drive control unit outputs a composite signal of the scan signal and the bright data signal to the ferroelectric liquid crystal. Formed as a waveform having an erase voltage level that brings the first stable state and a voltage level that is larger in absolute value than a first threshold voltage that shifts the ferroelectric liquid crystal from the first stable state to the second stable state. Then
A composite signal of the scanning signal and the dark data signal is formed and applied as a waveform having the erase voltage level and a voltage level of the absolute value which is equal to or lower than the first threshold voltage, and a signal subsequent thereto. As a signal waveform for holding the state of the ferroelectric liquid crystal by the composite signal, a composite signal of the scanning signal and the bright data signal is added to the erase voltage level and the ferroelectric liquid crystal in the second period. A liquid crystal having a voltage level higher in absolute value than a second threshold voltage that shifts the liquid crystal from the first stable state to the third stable state, and generates a composite signal of the scanning signal and the dark data signal. , A waveform having an erase voltage level and a voltage level having an absolute value that is equal to or lower than the second threshold voltage, and is applied. Matrix type ferroelectric liquid crystal display device which is characterized in that so as to impart a signal waveform which holds a state of the ferroelectric liquid crystal by forming signal. 2. The threshold value that is equal to or lower than the first threshold voltage in absolute value and that causes the ferroelectric liquid crystal to shift from the second stable state to the first stable state in the first period. A signal waveform having a voltage level equal to or higher than a voltage, wherein the following signal in the second period is equal to or less than the second threshold voltage in absolute value, and causes the ferroelectric liquid crystal to move from the third stable state to the first stable state. The matrix type ferroelectric liquid crystal display device according to claim 1, wherein the matrix type ferroelectric liquid crystal display device has a signal waveform having a voltage level equal to or higher than a threshold voltage for shifting to the stable state. 3. The matrix type ferroelectric liquid crystal display device according to claim 1, wherein the erase voltage level is substantially 0 level. 4. The erasing voltage level continues for at least a response time required to change to the first stable state regardless of whether the ferroelectric liquid crystal is in the second stable state or the third stable state. The matrix type liquid crystal display device according to claim 1, wherein the matrix type liquid crystal display device is provided. 5. The voltage level greater in absolute value than the first threshold voltage is a first saturation voltage that brings the liquid crystal into the second stable state, and is greater in absolute value than the second threshold voltage. 5. The matrix type liquid crystal display device according to claim 1, wherein the voltage level is a second saturation voltage that brings the liquid crystal into the third stable state.