JP2697671B2 - Matrix type liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type liquid crystal display device which performs a matrix display using liquid crystal cells forming mn display pixels.

[0002]

2. Description of the Related Art Conventionally, in a matrix type liquid crystal display device having a liquid crystal cell for forming mn display pixels and a scanning driving means, a ferroelectric liquid crystal has been disclosed in Japanese Patent Application Laid-Open No. 56-10726. Focusing on high-speed response and storage characteristics that are not available in nematic liquid crystals, these characteristics are effectively used to enable ON display pixels and OF in one display screen.
There is a configuration in which F display pixels are dynamically driven to perform matrix display.

[0003] The above-mentioned ON display pixel is a display area including a ferroelectric liquid crystal portion corresponding to the ON display pixel and transmitting light. On the other hand, the above-described OFF display pixel is a display region including a ferroelectric liquid crystal portion corresponding thereto and not transmitting light.

[0004]

By the way, in the ferroelectric liquid crystal having such a structure, ideally, the spontaneous polarization of the ferroelectric liquid crystal is controlled by the cell as described in JP-A-56-10726. In the state of being uniformly upward in the thickness direction (the above-mentioned O
N or OFF) and a uniformly downward state (corresponding to the above-described OFF or ON) should have memory characteristics and threshold characteristics that are important characteristics for dynamic driving.

However, in the ferroelectric liquid crystal in the above-described actual configuration, for example, JPN. J. APPL. PHYS.
VOL26, NO1, 1987, P1-4, in addition to the two states where the spontaneous polarization is uniform in the cell thickness direction, the spontaneous polarization of the ferroelectric liquid crystal is opposite to each other on the upper and lower substrates, In addition, there are four twisted states where the spontaneous polarization projected on the smectic surface in the cell thickness direction is twisted by 180 degrees, and the switching process is caused by the inversion mechanism of the spontaneous polarization led by the internal disclination. Has become apparent. In a matrix-type display device using such an inversion mechanism, problems such as a decrease in contrast and deterioration of threshold characteristics due to the presence of a twist state, and a decrease in response speed due to the presence of an internal rotation have been observed.

On the other hand, in order to secure the characteristics required for dynamic driving, control of the pulse width of the driving pulse, voltage dependence of the response speed of the ferroelectric liquid crystal, and negative dielectric anisotropy are required. Using the abnormal switching phenomenon of ferroelectric liquid crystal and the stabilization phenomenon due to high frequency, the pulse waveform of the drive pulse is devised, and the non-selection time until the next selection waveform is added, the stabilization effect by high frequency superposition It is conceivable to prevent the response of the liquid crystal and perform a matrix display.

However, such a method not only complicates the configuration of the drive circuit required to realize the above-described drive pulse, but also causes a problem that the display contrast is reduced and the display quality is greatly reduced. . The present inventors,
As a result of intensive research on the above-mentioned problems,
We have developed a liquid crystal as shown below. Liquid crystal that encapsulates this liquid crystal
In the cell, the absolute value of the applied voltage exceeds the first voltage
Up to the first light transmittance, and
When the absolute value of the pressure becomes a second voltage higher than the first voltage
The first light until a third voltage lower than the first voltage is reached;
Maintaining a state of a second light transmittance higher than the transmittance,
A fourth voltage or less whose absolute value of the applied voltage is smaller than the third voltage;
When it drops below, it maintains the state below the first light transmittance.
Hysteresis characteristics, the positive side of the applied voltage and
It is provided on each of the negative polarity sides. The present invention, this
It is an object of the present invention to simplify the configuration of the drive circuit and improve the display contrast by maintaining the display using the hysteresis characteristics on the positive and negative sides in the liquid crystal cell as described above .

[0008]

In order to achieve the above object, according to the first aspect of the present invention, an n-row electrode and an m-column electrode are juxtaposed so as to face each other in a grid pattern. a liquid crystal cell forming the mn number of display pixels by sealing liquid crystal between two electrode substrates were, a row drive circuit for applying a scanning signal to the row electrodes of the n Article data signals to the column electrodes of the m Article A column drive circuit for applying the mn display pixels.
In the matrix type liquid crystal display device configured to perform a matrix display by the liquid crystal cell ,
The absolute value to greater than the first voltage maintains the state of the following first light transmittance, the absolute value of the first voltage is greater than the second lower becomes the first voltage to the voltage third voltage of the applied voltage And maintaining a second light transmittance state larger than the first light transmittance until the absolute value of the applied voltage becomes the third light transmittance.
The hysteresis characteristic for maintaining the first of the following conditions light transmittance drops below a voltage less than the fourth voltage than the
Be one having a respective positive polarity side and the negative polarity side of the applied voltage, the scan signal is erased to erase the display
A signal to, a selection signal for selecting a display state, and is configured to have a non-selection signal for holding the selected display state, said non-selection signal, every predetermined time period, the positive polarity side Contact Yo
And the polarity is reversed to the negative side, and its absolute value is
It has a voltage between the first voltage and the third voltage, the non
A selection signal and the data signal are applied to the display pixel;
The display state is maintained .

In the invention described in claim 2 , the n
The row electrodes and the m-th column electrodes are opposed to each other in a grid pattern.
The liquid crystal is sealed between the two electrode substrates arranged side by side as shown in FIG.
The liquid crystal cell forming the display pixel and the n-row electrodes are scanned.
A row drive circuit for applying a signal, and data to the m-column electrodes.
And a column drive circuit for applying the mn signals.
A matrix that performs matrix display using display pixels
In the Rix type liquid crystal display device, the liquid crystal cell includes:
The first optical transmission is performed until the absolute value of the applied voltage exceeds the first voltage.
Maintain the state below the excess rate, the absolute value of the applied voltage is
When the second voltage becomes higher than the first voltage, the second voltage becomes higher than the first voltage.
Larger than the first light transmittance until the third voltage becomes low
Maintaining the state of the second light transmittance, the absolute value of the applied voltage
Is lower than the fourth voltage, which is smaller than the third voltage,
The hysteresis characteristic for maintaining the state below the first light transmittance.
The positive and negative sides of the applied voltage.
Be one having Les, the scanning signal, the display
An erasing signal for erasing, a selection signal for selecting a display state,
And a non-selection signal for holding the selected display state.
And is configured by the non-selection signal and the data signal.
The voltage applied to the display pixel is set to a positive polarity every predetermined period.
The polarity is reversed to the negative side and the negative side.
The applied voltage has a voltage between the first voltage and the third voltage.
And the display state of the display pixel is changed by the applied voltage.
It is characterized by being retained.

[0010] According to the third aspect of the present invention, in the first aspect or the third aspect,
3. In the matrix type liquid crystal display device according to 2,
Polarity reversal to the positive and negative sides when displaying one screen
It you are characterized performed within between. According to a fourth aspect of the present invention, in the matrix type liquid crystal display device according to any one of the first to third aspects, the liquid crystal is an electroless device.
It has a first stable molecular orientation state when the field, and electric field application
Has a different second stable molecular orientation state and at one of the first stable molecular orientation like <br/> state to the electric field direction, the other
It is characterized in that with respect to the electric field direction wherein the first and second stable molecular orientation state is shall to have a different third stable molecular orientation state.

[0011] According to the invention described in claim 5 , the invention according to claims 1 to
5. The matrix type liquid crystal display device according to any one of items 4 , wherein the liquid crystal is a smectic liquid crystal.

[0012]

[0013]

According to the first to fifth aspects of the present invention, the liquid crystal cell has a positive polarity side and a negative polarity side of the applied voltage.
Since a display having a hysteresis characteristic in light transmittance with respect to an applied voltage is used, and after a display state is selected by a selection signal, the display is held by a non-selection signal, the display in the non-selection period is performed. Since it is only necessary to set the holding according to the hysteresis characteristic, the driving circuit can be simplified, and the display contrast can be improved by using the holding in the hysteresis.

[0014]

[0015]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a view showing the overall configuration of a matrix type liquid crystal display device according to the present invention, FIG. 2 is an enlarged schematic view of a liquid crystal cell, FIG. 3 is a view showing an alignment state of liquid crystal molecules, and FIG. FIG. 4 is a diagram illustrating a relationship between transmittance and applied voltage.

The matrix type liquid crystal display device shown in FIG. 1 includes a matrix type liquid crystal cell 10, and this liquid crystal cell 10 has, as shown in FIGS.
A pair of electrode substrates 11 and 12 via a gap of 0 (μm).
Are disposed in parallel with each other, and 4- (1-trifluoromethylheptoxycarbonylphenyl) -4′-octyloxybiphenyl-4 is provided between the electrode substrates 11 and 12.
-Carboxylate (hereinafter abbreviated as TFHPOBC) 13
, And polarizers 14 and 15 having polarization axes orthogonal to each other are respectively attached to the electrode substrates 11 and 12 from the outside. The ferroelectric liquid crystal is
It is a smectic liquid crystal having a smectic phase.

Each row electrode X ₁ -X _n and each column electrode Y ₁
Each intersection of the to Y _m, respectively each display pixel with each ferroelectric liquid crystal moiety present in each of these intersections (1, 1),
.. (1, m), (2, 1),... (N, m). Further, when an appropriate negative polarity voltage is applied between the row electrode and the column electrode, the display pixel is in a state of transmitting light (ie, an ON display state) in a molecular alignment state that the ferroelectric liquid crystal can take. On the other hand, when a proper voltage equal to or less than a threshold is applied between the row electrode and the column electrode, the display pixel does not transmit light in a molecular orientation state that the ferroelectric liquid crystal can take (that is,
The polarization axis of each of the polarizing plates 14 and 15 is determined in relation to the molecular orientation axis of the ferroelectric liquid crystal so as to be in the OFF display state. A light source (not shown) for projecting light onto the polarizing plate 14 is arranged behind the polarizing plate 14.

Further, as shown in FIG.
A line-sequential scanning circuit 20; a reset pulse generating circuit 30 connected to the line-sequential scanning circuit 20;
A row drive circuit 40 and a column drive circuit 50 connected to the 0 and reset pulse generation circuit 30 are provided. The line sequential scanning circuit 20 includes a ROM 21 and a controller 22 connected to the ROM 21. ROM 21
Is for storing display data representing predetermined display contents to be displayed on the liquid crystal cell 10 in advance. The display data includes row electrode display data input to any of the row electrodes of the liquid crystal cell 10 and column electrode display data input to each column electrode of the liquid crystal cell 10.

The controller 22 includes a synchronization pulse LP, a frame pulse a (see FIG. 7), a shift clock pulse S
Sequentially generating the P, sequentially generates the row electrodes display data from the ROM21 as a data pulse P _x, and sequentially generates a column electrode display data from the ROM21 as a data pulse P _y. The reset pulse generation circuit 30 is configured by a monostable multivibrator IC (e.g., equivalent to 74HC123) or the like, and resets a reset pulse b having a desired pulse width to a low level in synchronization with the rise of a frame pulse a generated by the controller 22. Occur.

The reset pulse b is output to the controller 22 as a wait signal, and the same pulse is inserted at a normal line sequential scanning timing. Controller 22
Stops all functions while the reset pulse b is at low level, and restarts signal generation when the reset pulse b becomes high level. Next, a configuration outline of the liquid crystal cell will be described.

As shown in FIGS. 1 and 2, the electrode substrate 11 forms a transparent conductive film 11b made of indium oxide or tin oxide along the inner surface of a transparent glass plate 11a. The film 11b has n row electrodes X ₁ , X
_2, ........., an X _n, which together impart a distance from each other in the vertical direction are configured to protrude formed in parallel to each other in the left-right direction.

As shown in FIGS. 1 and 2, a transparent conductive film 12b made of indium oxide or tin oxide is formed along the inner surface of a transparent glass plate 12a, and On the film 12b, m column electrodes Y ₁ , Y
_2, ..., the Y _m, row electrodes X _1, X ₂ along with imparting a distance from each other in the left-right direction, and is configured to protrude formed perpendicular to ... X _n.

Further, polymer films 16 and 17 are provided on the inner surfaces of the conductive films 11b and 12b. Polymer film 16, 1
The surface of 7 is subjected to a rubbing process so that the ferroelectric liquid crystal molecules 13a are arranged parallel to the upper and lower substrates and in a direction perpendicular to the normal line P. Instead of the polymer films 16 and 17, a thin film having a crystal orientation such as an oblique deposition film of silicon oxide may be used.

When the ferroelectric liquid crystal 13 is sealed in the liquid crystal cell 10, first, the rubbing orientation of the polymer films 16 and 17 passes through the center of the distance between the inner surfaces of the conductive films 11b and 12b. Parallel to the membranes 11b, 12b (ie, normal P
The electrode substrates 11 and 12 are combined in parallel with respect to a center line that is perpendicular to the center line. Thereafter, the ferroelectric liquid crystal 13 is heated to be injected as an isotropic liquid phase between the two electrode substrates 11 and 12 using the capillary phenomenon, and the entire liquid crystal cell 10 is heated at about 1 ° C. per minute. By slow cooling, the ferroelectric liquid crystal 13 is cooled to a smectic C ^* phase.

As a result of such cooling, the ferroelectric liquid crystal 13 in the form of a smectic layer is oriented along the rubbing direction of the polymer films 16 and 17, but as shown in FIG. It is bent in the shape of "ku". FIG.
(A), (b) and (c) show the alignment state of liquid crystal molecules according to the state of application of an electric field to the liquid crystal. In FIG. 3, the diagram on the left shows the polarization direction, the diagram at the center shows the liquid crystal molecules as viewed from above, and the diagram on the right shows the smectic cone in the liquid crystal cross-sectional direction.

In the absence of an electric field, the ferroelectric liquid crystal molecules 13a
As shown in FIG. 3 (a), in the upper half of the liquid crystal cell 10, the spontaneous electrodes are oriented so as to face the left direction (right direction), and in the lower half, the spontaneous polarization faces the right direction (left direction). Orient. That is, if the movement of the liquid crystal molecules 13a is represented on a smectic cone, the liquid crystal molecules 13a are located in the upper half of the liquid crystal cell 10 in the upper half and in the lower half of the lower half. Is done. This first state is a stable state in which the light is quenched when observed under crossed Nicols.

When an electric field is applied between the two electrode substrates 11 and 12 from the bottom to the top of the drawing, the liquid crystal molecules 13a oriented as shown in FIG. The product torque and the elastic torque compete. When the electric field E exceeds a certain threshold value, the orientation state of the liquid crystal molecules 13a is such that the spontaneous polarization is all upward as shown in FIG. 3B (second state). In other words, when viewed from a smectic cone, it changes to be located on the right side of the cone.

Now, the polarization axis of the orthogonal polarizing plate is shown in FIG.
When arranged as shown in (a), the light transmission intensity I becomes
Given by

[0029]

I = I _O Sin ² 4θ · Sin ² (πΔnd / λ) where I _O is a constant mainly determined by the transmittance of the polarizing plate, and θ is a tilt angle and changes with temperature in the case of TFHPOBC. However, it is 11 to 31 degrees. Δn is the difference between the refractive indexes of the liquid crystal with respect to ordinary light and extraordinary light, d is the cell gap, and λ is the wavelength. It can be seen from Equation 1 that the light transmittance in the second state is a bright state.

Further, in the state shown in FIG. 3A, when an electric field is applied from the near side to the back side of the paper and exceeds a certain threshold, the alignment state of the liquid crystal molecules 13a is changed as shown in FIG. 3C. All spontaneous polarizations are directed downward (third state). That is, if it is shown by a smectic cone, it changes so that the molecule is located on the left side of the cone. According to Equation 1, the light transmittance in the third state also becomes a bright state.

The relationship between the liquid crystal molecules and the spontaneous polarization may be such that the spontaneous electrode is upward when the cone is on the left side, and this depends on the material. In this case, the position of the liquid crystal molecules 13a and the direction of the spontaneous polarization are different from those described above. Reverse. The relationship between the applied voltage and the light transmittance of the ferroelectric liquid crystal 13 subjected to the alignment treatment as described above was confirmed by an experiment. As a result, a hysteresis curve x was obtained as shown in FIG.

That is, when a positive voltage is applied to change from the stable first state at the time of no voltage to the stable second state, the voltage at which the light transmittance changes by 10% is represented by v ₃ , 90%
The varying voltage and v _4. Further, when the applied voltage is changed from the stable second state to which the positive voltage is applied to the first state by reducing the applied voltage, the voltage having a light transmittance of 90% is changed to v ₂ , and the voltage of 10% is changed to v ₂ . v ₁ to. Then, it can be easily confirmed that a hysteresis loop is formed by these voltages v ₁ , v ₂ , v ₃ , and v ₄ . Also, it goes without saying that when applying a voltage of the opposite polarity from the stable first state to the third state, substantially the same result as described above is obtained. In addition,
As can be seen from the hysteresis characteristics, the first stable state is not limited to when no voltage is applied, but remains in the first stable state up to a predetermined voltage. Also, the voltages v ₁ , v ₂ , v ₃ , v ₄
Corresponds to the fourth voltage, the third voltage, the first voltage, and the second voltage, respectively, but the second and third voltages when a hysteresis loop is formed are fixed to those shown in FIG. Instead, another voltage may be used.

On the other hand, when the relationship between the applied voltage and the light transmittance in the conventional ferroelectric liquid crystal was confirmed by an experiment, it was obtained as a curve y as shown in FIG. Both curves x,
As can be easily understood from the comparison of y, it can be confirmed that the ferroelectric liquid crystal 13 exhibits hysteresis characteristics not exhibited by the conventional ferroelectric liquid crystal. Next, an example of a logic circuit included in the row driving circuit and the column driving circuit illustrated in FIG. 1 will be described.

FIG. 5 is a detailed diagram of a logic circuit forming a row driving circuit, FIG. 6 is a detailed diagram of a logic circuit forming a column driving circuit,
7 and 8 are output waveform diagrams for explaining the operation of the logic circuit. As shown in FIG. 1, the row drive circuit 40 includes a shift register 40A connected to the controller 22, and each of the logic circuits 40B ₁ and 40B connected to the controller 22, the reset pulse generation circuit 30, and the shift register 40A.
_2, ........., has a 40B _n, the shift register 4
0A sequentially receives the synchronization pulse LP from the controller 22 as a shift pulse, and sequentially shifts the data pulse P _x from the controller 22 in synchronization with each of the shift pulses to obtain a data pulse c, thereby obtaining each logic circuit 40B _1.
It applied to any of the ~40B _n.

The logic circuit 40B ₁ is, as shown in FIG. 5, an inverter 41, 42, 44, D-type latch 48, AN
D gates 43a, 43b, 43c, 43d, constant voltage circuits 45a, 45b, 45c, 45d, and transmission gates 46a, 46b, 46c, 46d, 46e are provided. The inverter 41 is connected to the shift register 40
A, the inverter 42 is connected to the D-type latch 48, and the inverter 44 is connected to the reset pulse generation circuit 30, respectively. The D type latch 48 is provided with a shift register 40A.
To the G terminal and the frame pulse a from the controller 22 to the D terminal. When the G terminal input is at a high level, the frame pulse a is output from the Q terminal as it is, and the G terminal input is at a low level. Then, the D terminal input signal level at the time of the falling of the G terminal input signal is held, and Q
Output from the terminal to generate a gate pulse a '. Also,
The AND gates 43a, 43b, 43c, and 43d each include one of the shift register 40A and the inverter 41,
One of the controller 23 and the inverter 42,
And a reset pulse generating circuit 30.

The AND gate 43a, as shown in FIG.
Data pulse c from shift register 40A, reset pulse b from reset pulse generation circuit 30, and latch 4
Only when all of the gate pulses a 'from 8 are at the high level, the gate pulse d is generated at the high level in response. A
The ND gate 43b responds only when all of the inverted gate pulse c, the reset pulse b, and the gate pulse a 'from the inverter 41 are at the high level, and generates the gate pulse e at the high level.

The AND gate 43c generates a gate pulse f at a high level in response only when all of the data pulse c, the reset pulse b, and the inverted gate pulse from the inverter 42 are at a high level. AND gate 43d
Inverting gate pulse c of inverter 41 and inverter 42
The gate pulse g is generated at a high level in response only when all of the inverted gate pulse and the reset pulse b are at a high level. Further, the inverter 44 inverts the reset pulse b and generates an inverted gate pulse h.

The transmission gate 46a has an AN
In response to the gate pulse d from the D gate 43a,
Gate pulse d is a positive constant voltage from constant voltage circuit 45a.
(+ V _Three), (+ V_ThreeShift to level)
Then, as the scanning signal S1, each transmission gate 4
6b, 46c, 46e, and output to a common output terminal 47,
Row electrode X of liquid crystal cell 10₁To be given.

When the transmission gate 46b is
D receiving the gate pulse e from the gate 43b when shifting the gate pulse e to the level of the positive constant voltage (+ V _2), and outputs to the output terminal 47 as a scanning signal S2, applied to the row electrodes X _1. The transmission gate 46c
Upon receiving the gate pulse f from the AND gate 43c, shifts the gate pulse f to the level of the negative constant voltage (-V _3), and outputs to the output terminal 47 as a scanning signal S3,
It applied to the row electrodes X _1.

When the transmission gate 46d is an AN
D receives a gate pulse g from gate 43d when shifting the gate pulse g to the level of the negative constant voltage (-V _2), and outputs to the output terminal 47 as a scanning signal S4, applied to the row electrodes X _1. The transmission gate 46e is
Upon receiving the gate pulse h from the inverter 44 shifts the gate pulse to the zero level, and outputs to the output terminal as a scanning signal S0, it is applied to the row electrodes X _1.

[0041] When such functions as reset signal scanning signal S0 to erase the display, scanning signals S1 and S3 functions as a selection signal for selecting the row electrodes X _1, the scanning signal S2 and S4 are the same electrode It functions as a non-selection signal for non-selection. The selection signal and the non-selection signal have a voltage waveform whose polarity is inverted around the voltage level (0 V) of the reset signal (erase signal).

The remaining logic circuits 40B _{2 to} 40B _n have the same configuration as the logic circuit 40B1, and each of the logic circuits 40B _{2 to} 40B _n has a shift register 40A.
Frame pulse a from the data pulse c and the controller 22 from, in response to the reset pulse b from the reset pulse generating circuit 30, similarly to the logic circuit 40B _1, the scanning signals S0, S1, S2, S3, S4 Respectively.

[0043] Thus, the scanning signals S0 and both the scanning signals from the logic circuit 40B ₂ S1, S3 and both the scanning signal S2,
S4 are respectively as a reset signal and the selection signal and the non-selection signal is applied to the row electrodes X ₁ of the liquid crystal cell 10, the scanning signals S0 and both the scanning signal S1 from the logic circuit 40B _3,
S3 and two scanning signal S2, S4, respectively as the reset signal and the selection signal and the non-selection signal is applied to the row electrodes X ₃ of the liquid crystal cell 10, and so on, the logic circuit 40B
scanning signal from _n S0 and both the scanning signals S1, S3 and both the scanning signals S2, S4, respectively applied to the row electrodes X _n of the liquid crystal cell 10 as a reset signal and the selection signal and the non-selection signal.

As shown in FIG. 1, the column drive circuit 50 includes a shift register 50A and a latch 50B connected to the controller 22, and a logic circuit 50 connected to the controller 22, the reset pulse generator 30 and the latch 50B.
C _1, 50C _2, ........., has a 50C _m, cysts register 50A is a serial data pulse Py from the controller 22, sequentially inputs in response to a shift clock pulse SP from the controller 22, m The data is converted into parallel data pulses and applied to the latch 50B.

The latch 50B responds to the synchronizing pulse LP from the controller 22, and latches m data pulses from the shift register 50A to obtain the data pulses j shown in FIG. 7 as logic pulses 50C ₁ , 50C ₂ ,. ... 50
Each grant to C _m. Logic circuit 50C ₁ is, as shown in FIG. 6, an inverter 51, the AND gates 52a, 52
b, NAND gate 53, constant voltage circuits 54a, 54b,
Transmission gates 55a, 55b and 55c are provided.

The inverter 51 is connected to the controller 2
2, the AND gate 52a is connected to the inverter 51, the reset pulse generation circuit 30, and the latch 50B, and the AND gate 52b is connected to the controller 22, the reset pulse generation circuit 30, and the latch 50B, and the NAN
D gate 53 is connected to reset pulse generating circuit 30 and latch 50B.

The AND gate 52a, as shown in FIG.
Only when all of the inverted gate pulse of the frame pulse a from the inverter 51, the reset pulse b from the reset pulse generating circuit 30 and the data pulse j from the latch 50B are at the high level, the gate pulse k at the high level
Occurs. The AND gate 52b responds only when the frame pulse a from the controller 22, the reset pulse b from the reset pulse generation circuit 30 and the data pulse j from the latch 50B are all at a high level. Occurs.

The NAND gate 53 is connected to the reset pulse b from the reset pulse generation circuit 30 and the latch 50.
Responds when at least one of the data pulses j from B is at a low level, and generates a gate pulse m at a high level. Transmission gate 55a responds to gate pulse k from AND gate 52a to apply the same gate pulse k to the level (+) of the positive constant voltage from constant voltage circuit 54a.
V ₁ ), and outputs a common output terminal 5 with each transmission gate 55b, 55c as a data signal D2.
Output to 6, applied to the column electrode Y ₁ of the liquid crystal cell 10.

The transmission gate 55b receives the gate pulse 1 from the AND gate 52b and shifts the same gate pulse 1 to the negative constant voltage level (-V ₁ ) from the constant voltage circuit 54b and outputs it as the data signal D1. output to terminal 56, applied to the column electrode Y _1. Further, the transmission gate 55c outputs shifted from NAND gate 53 to the zero level of the same gate pulse m and receives a gate pulse m to the output terminal 56 as a data signal D3, applied to column electrodes Y _1.

In such a case, the data signals D1 and D2 are turned on.
It functions as a data signal, and the data signal D3 functions as an OFF data signal. The remainder of the logic circuit 50C ₂ ~50
C _m are both have the same structure as the logic circuit 50C _1, each of these logic circuits 50C ₂ ~50C _m, the latch 5
0B, a frame pulse a from the controller 22, and a reset pulse b from the reset pulse generation circuit 30.
Each data signal in the same manner as C ₁ D1, D2, resulting in D3.

[0051] Thus, both data signals D1, D2 and the data signal D3 from the logic circuit 50C ₂ are respectively applied to the column electrodes Y ₂ of the liquid crystal cell 10 as ON data signal and OFF data signal from the logic circuit 50C ₃ Are applied to the column electrode Y3 of the liquid crystal cell 10 as an ON data signal and an OFF data signal, respectively.
Both data signal from C _m D1, D2 and the data signal D3
As ON data signal and OFF data signal are respectively applied to the column electrodes Y _m of the liquid crystal cell 10.

Next, the constant voltage (+ V ₃ ) from each constant voltage circuit 45a and the constant voltage (+ V ₃ ) from the constant voltage circuit 45b
V ₂ ), constant voltage (−V ₃ ) from constant voltage circuit 45 c, constant voltage (−V ₂ ) from constant voltage circuit 45 d, constant voltage circuit 5
How to determine the constant voltage (+ V ₁ ) from the constant voltage circuit 4a and the constant voltage (−V ₁ ) from the constant voltage circuit 54b will be described. O
When a voltage is applied to the display pixel (m, n) in the FF display state to change the display state to the ON display state, the time required for the light transmittance of the display pixel (m, n) to reach 90% after the voltage is applied is a ferroelectric liquid crystal. 13 and the data signal D as shown in FIG.
The response time corresponding to 0 or the signal width of the scanning signal S0 is set to a set response time to, and the response time responding to the signal width of the data signal D1 or the scanning signal S1 is set to the same to.

At this time, the bias voltages are set to + V ₂ ４18 (V) and + V ₂ in relation to the curve x shown in FIG.
_{If 1} ≒ 5 (V) and + V ₃ ≒ 22 (V), dynamic driving becomes possible. The negative bias is-
V ₂ ≒ −18 (V), −V ₁ ≒ −5 (V), −V ₃ ≒ −
22 (V). However, the set response time to is V ₂ = 1
The response time when a voltage of 8 (V) is applied.

In this embodiment constructed as described above,
When the sequential scanning circuit 20 receives the frame pulse a and the synchronization pulse L
P, shift clock pulse SP, date pulse Px and
Generate a data pulse Py and generate a reset pulse
The raw circuit 30 responds to the frame pulse a,
When the row b is generated, as shown in FIG.
Are the synchronization pulse LP and the data from the line-sequential scanning circuit 20.
From the reset pulse generation circuit 30
In response to the reset pulse b, the reset signal (S0) or
Is a selection signal (scanning signals S1, S3) or a non-selection signal
(Scanning signals S2, S4) are applied to each row electrode X of the liquid crystal cell 10.
₁~ X_nRow electrode X₁To row electrode X _nTo
To be applied while shifting every T / n. (However, T is
One screen display time).

On the other hand, the column driving circuit 50 outputs the synchronization pulse LP and the shift clock pulse SP from the line-sequential scanning circuit 20.
In response to the data pulse Py, the frame pulse a, and the reset pulse b from the reset pulse generation circuit 30, the ON data signal (data signal D1, D2) or the OFF data signal (data signal D3) is transmitted to the liquid crystal cell 10
Repeatedly applied to each column electrode Y ₁ to Y _m in.

Therefore, the display state of the display pixel is determined by the data signal from the column drive circuit 50 when the selection signal is applied to the row electrode from the row drive circuit 40. In the case of the ON data signal, the ON and OFF data are displayed. It turns off in the case of a signal. That is, according to the hysteresis characteristic of FIG. 4, when the voltage by the selection signal and the OFF data signal is applied to the liquid crystal, the display is turned off, but the voltage by the selection signal and the ON data signal (second voltage according to claim). Is turned on when is applied to the liquid crystal.

When the display is turned on, while the non-selection signal following the selection signal is applied to the row electrode, the display state is changed regardless of whether the data signal is an ON data signal or an OFF data signal. That is, a voltage (a voltage between the second voltage and the third voltage described in claims) that does not decrease the light transmittance due to the hysteresis characteristic of FIG. 4 is applied to the liquid crystal.

FIG. 10 is a partially enlarged view of a row electrode and a column electrode. Assuming that the display pixels (1, 1) are OFF and the display pixels (1, 2) are ON, the voltage waveform applied to the liquid crystal cell is shown in FIG. 11 (c) for the former and FIG. 11 (c) for the latter.
The light transmittance at this time is shown in Fig.
(d) and (b). The operation of the present invention will be described in detail with reference to FIG.

First, all of the n × m display pixels are turned off by 0V during the first time to of one screen display time.
The display is reset (corresponding to the first state). Then, utilizing the hysteresis observed in the light transmittance-voltage characteristics between the first state and the second state, n · T / (2
During (n + 1), the ON display pixels are written according to the display data.

During the next n · T / (2n + 1), a signal whose polarity is inverted is used, and the hysteresis observed in the light transmittance-voltage characteristic between the first state and the third state is used. Then, the ON display pixels are written according to the same display data as above to complete the display of one screen. This will be described more specifically with reference to voltage waveforms applied to the ON display pixels (1, 2) and the OFF display pixels (1, 1).

FIG. 11 shows the ON display pixels (1, 2).
The voltage waveform shown in FIG.
OFF display (corresponding to the first state in terms of the state of the liquid crystal molecules), and ON display by the pulse of the voltage (V ₃ + V ₁ ) resulting from the combination of the next selection signal S1 and ON data signal D1 ( In terms of the state of the liquid crystal molecules, this corresponds to the second state). Thereafter, the ON display is (n−n) by the voltage V _{2 obtained} by combining the non-selection signal S 2 and the data signal D 3.
1) It is held for T / (2n + 1). That is, the voltage V ₂ is displayed holding for a voltage that does not change the light transmittance than the hysteresis characteristic is carried out.

Then, the next selection signal S3 and data signal D
Another ON by the voltage − (V ₃ + V ₁ ) by combining 3
Display (corresponding to the third state in terms of the state of liquid crystal molecules) is obtained. The subsequent non-selection signal S4 and data signal D3
The ON display by synthesis by the voltage -V ₂ is also held. This situation is shown in FIG. 11B in terms of the relationship between light transmittance and time.

Next, the voltage waveform shown in FIG. 11C is applied to the OFF display pixel (1, 1).
After being reset to the OFF display in the V period, the selection signal S1
The OFF display and the voltage V ₃ by synthesis OFF data signal D3. Thereafter, a voltage (V ₂ + V ₁ ) or V ₂ resulting from the synthesis of the non-selection signal S2 and the ON data signal D1 or the OFF data signal D3 is applied to the liquid crystal. Because of low, OF
The F display is maintained.

The selection signal S3 and the OFF data signal D
Third voltage by synthesis and voltage -V ₂ and the selection signal S4 by combining ON data signal D2 or OFF data signal D3 - liquid crystal molecules to (V ₂ + V ₁₎ or -V ₂ does not respond O
Maintain the FF display. This situation is shown in FIG. 11D in the relationship between light transmittance and time. Note that the voltage applied to the liquid crystal at the time of generation of the erase signal need not be completely 0 V but may be substantially 0 V.

In practicing the present invention, the polymer films 16 and 17 are formed on both the conductive films 11b and 12b, respectively.
The embodiment may be implemented such that the polymer film 16 or 17 is formed only on one side of 2b. In practicing the present invention, the liquid crystal cell 10 is not limited to a transmission type, but may be a reflection type.

In practicing the present invention, the erasure signal is generated at time 0 as X _{1 to} X _n and Y _{1 to} Y _m as shown in FIG.
It is needless to say that an erase signal is applied to a plurality of X electrodes and Y electrodes and a plurality of erase signal application times are provided during one screen display time T in addition to the case where the erase signal is applied once. is there. As described above, according to this embodiment, the ferroelectric liquid crystal 13 has the light transmittance-voltage characteristic specified by the curve x in FIG. In order to clarify the state and the OFF display state, dynamic driving is performed so that each row electrode X ₁ to
Scanning signal to be applied to X _n, and the data signal applied to each column electrode Y ₁ to Y _m, the light transmittance - may only impart a simple waveform change in the context of the voltage characteristic.

Therefore, assuming the existence of three stable states with respect to the applied voltage of the ferroelectric liquid crystal 13 and the hysteresis characteristic, the circuit configuration of the column driving circuit and the row driving circuit of this type of display device is greatly simplified. The display contrast can be improved. Also, the data signal D2 and the scanning signal S1, which are opposite in polarity to the data signal D1, so that the voltages applied to the liquid crystal display cell 10 are all canceled out to zero in one screen display time T.
Scanning signals S3 and S4 having polarities opposite to S2 are applied for a time (T + to).
Since the voltage is applied after / 2, deterioration of the ferroelectric liquid crystal due to the direct current component can be prevented beforehand.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention.

FIG. 2 is an enlarged schematic sectional view of the liquid crystal cell in FIG.

FIG. 3 is a view showing an alignment state of liquid crystal molecules in FIG.

FIG. 4 is a diagram showing a relationship between light transmittance of a ferroelectric liquid crystal and applied voltage.

FIG. 5 is a detailed diagram of a logic circuit of the row drive circuit in FIG.

FIG. 6 is a detailed diagram of a logic circuit of the column driving circuit in FIG.

FIG. 7 is an output waveform diagram for explaining the operation of the circuit shown in FIG. 5;

FIG. 8 is an output waveform diagram for explaining the operation of the circuit shown in FIG. 6;

9 is an explanatory diagram of signals applied to the liquid crystal cell shown in FIG.

FIG. 10 is a partially enlarged view of a row electrode and a column electrode.

FIG. 11 is an explanatory diagram of a voltage applied to a liquid crystal cell.

[Explanation of symbols]

10: liquid crystal cell, 11, 12: electrode substrate, 13: ferroelectric liquid crystal, 14, 15: deflection plate, 16, 17: polymer film,
Reference numeral 20: line sequential scanning circuit, 21: ROM, 22: controller, 30: reset pulse generation circuit, 40: row drive circuit, 50: column drive circuit.

Continuing on the front page (72) Inventor Ichiro Kawamura 2-7-3 Marunouchi, Chiyoda-ku, Tokyo Inside Showa Shell Sekiyu KK (72) Inventor Masao Tokunaga 1-1-1, Showa-cho, Kariya-shi, Aichi, Japan Denso Co., Ltd. (72) Inventor Kaoru Mori 1-1-1, Showa-cho, Kariya-shi, Aichi Japan Nihon Denso, Inc. Norio 1-1, Showa-cho, Kariya-shi, Aichi Prefecture Japan Denso Co., Ltd.

Claims (5)

(57) [Claims] 1. A liquid crystal cell for forming mn display pixels by sealing a liquid crystal between two electrode substrates in which n rows of electrodes and m rows of electrodes are arranged side by side so as to face each other in a grid pattern. performed when the row drive circuit for applying a scanning signal to the row electrodes of the n Article and a column drive circuit for applying data signals to the column electrodes of the m Article matrix display by the mn number of display pixels In the matrix type liquid crystal display device described above, the liquid crystal cell maintains a state of being equal to or lower than the first light transmittance until the absolute value of the applied voltage exceeds the first voltage, and the absolute value of the applied voltage is equal to or less than the absolute value of the applied voltage. until the lower third voltage than the first voltage to become first voltage greater than the second voltage maintains the state of the first light transmittance is greater than the second light transmittance, the absolute value of the applied voltage is the When it falls below a third voltage smaller than the fourth voltage A hysteresis characteristic to maintain the serial first of the following conditions light transmittance, the positive polarity side of the applied voltage and
Be one having a respective negative side, the scan signal has an erase signal for erasing the display, a selection signal for selecting a display state, and a non-selection signal for holding the selected display state The non-selection signal is supplied to the positive side and the negative side every predetermined period.
The polarity is inverted to the polarity side, the absolute value of which is
The voltage between the first voltage and the third voltage possess, the non-selected
A signal and the data signal are applied to the display pixel,
A matrix type liquid crystal display device wherein a display state is maintained . 2. An n-row electrode and an m-column electrode are connected to each other.
The liquid crystal is placed between the two electrode substrates
And a liquid crystal cell forming mn display pixels by enclosing
A row driving circuit for applying a scanning signal to the row electrodes of the n rows;
A column driving circuit for applying a data signal to the column electrode
Equipped with a matrix display by the mn display pixels.
Matrix type liquid crystal display device
Te, the liquid crystal cell, the absolute value of the applied voltage exceeds a first voltage
Up to the first light transmittance, and
When the absolute value of the pressure becomes a second voltage higher than the first voltage
The first light until a third voltage lower than the first voltage is reached;
Maintaining a state of a second light transmittance higher than the transmittance,
A fourth voltage or less whose absolute value of the applied voltage is smaller than the third voltage;
When it drops below, it maintains the state below the first light transmittance.
That the hysteresis characteristic, the positive polarity side of the applied voltage and
The scanning signal includes an erasing signal for erasing the display and a display signal.
Holds the selection signal for selecting the state and the selected display state
To the display pixel by the non-selection signal and the data signal.
The applied voltage of the positive polarity side and the negative polarity
The polarity is inverted to the side, and the applied voltage is
A voltage between the first voltage and the third voltage;
The display state of the display pixel is maintained by an applied voltage
A matrix type liquid crystal display device characterized by the above-mentioned. 3. The polarity counter to the positive polarity side and the negative polarity side.
Is performed within one screen display time.
3. A matrix type liquid crystal display device according to claim 1 or 2. Wherein said liquid crystal has a first stable minute when no electric field
It has a child orientation state, and the one electric field direction when an electric field is applied
Against the have different second stable molecular orientation state to the first stable molecular orientation state, a third stabilizing different from the other the relative electric field direction of the first and second stable molecular orientation state
Matrix liquid crystal display device according to any one of claims 1 to 3, characterized in that the shall which have a a molecular alignment state. 5. A matrix-type liquid crystal display device according to the liquid crystal is any one of claims 1 to 4, characterized in that a smectic liquid crystal.