JPH0723938B2 - Liquid crystal display manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a liquid crystal display device that enables a high duty ratio.

Conventionally, liquid crystal display devices have been widely used in desk-top electronic calculators and electronic timepieces, but as the cost and performance of microcomputers have been reduced in recent years, microcomputers for liquid crystal displays that are small and thin and have low power consumption have been developed. Application to portable terminals has come to be considered. In such applications, the panel area is large and it is necessary to display many characters and pictures at the same time. For word processors, for example, 20 lines of 64 alphabetic characters must be able to be displayed simultaneously. At this time, multiplex drive is indispensable, but the drive duty at this time is 1/16
It becomes 0. On the other hand, since the response speed of the liquid crystal itself is slow, the current duty that can be driven is 1/16 in the normal voltage averaging method, which is 1% higher than the required duty.
It is a bad value.

Therefore, as a means for improving the drive duty, there has been proposed a method of driving a liquid crystal through a non-linear element or a switching element to increase a drive margin. The non-linear element may be a metal-insulator-metal (MIM) element, a varistor element, a diode element, or the like, and a switching element is a compound semiconductor or a thin film transistor made of amorphous silicon.

FIG. 1 shows a pixel 13 including a liquid crystal cell 11 and a charge storage capacitor 12 connected in parallel with the thin film transistor (TFT) 10 as a switching element. Actually, the pixels are arranged in a matrix of (m × n) along the timing lines T1 to Tm and the data lines D1 to Dn, and this figure shows the cell at the address (i, j). ing.

FIG. 2 shows the operation of this cell. Gj is j
Shows the gate voltage applied to the timing line Tj of the row,
Di represents a data signal applied to the i-th column data line Di. VS indicates the voltage applied to the liquid crystal cell and the charge storage capacitor. When the j-th timing line Tj is selected, a gate voltage as shown in Gj of FIG. 2 is applied to the transistor. This gate voltage turns on the transistor. At this time, the signal applied to the data line Di is written in the pixel as the voltage VS via the source / drain of the transistor. Then, when the writing to the pixel is completed, the timing line is in the non-selected state, that is, the transistor is in the OFF state, and the charge written to the pixel is held by the liquid crystal cell and the charge holding capacitor, and the next signal is written. Drive the liquid crystal up to. A high drive duty can be obtained by this write / hold operation.

Generally, such a TFT can be used to form a display panel having a large number of pixels. On the contrary, the TFT manufacturing process is normally performed with 6 film deposition steps and 5 photoetching steps.
The process and process are long. Therefore, in addition to the increase in manufacturing cost, the possibility of introducing defects is increased due to the long process, the yield is reduced and the defect cost is also increased. Also,
As a result, it is difficult to form a large-area panel.

Therefore, it is an object of the present invention to provide a method of manufacturing a liquid crystal display device having a thin film transistor that can be manufactured by a simple process. In particular, the charge storage capacitor can be manufactured in exactly the same process as the thin film transistor. Another feature is that the characteristics of the storage capacitor can be optimized by forming the electrode that forms the charge storage capacitor and the wiring layer that holds the electrode at a constant potential with different materials.

FIG. 3 shows an embodiment of the present invention. 30 is
One pixel cell is shown. The wiring 31 is a data line, the wiring 32 is a timing line, and the wiring 53 is a GND wiring to which the first electrode of the charge storage capacitor is connected and which is held at a constant potential. Wiring 31, 3
The members 2 and 53 are preferably members having a relatively low resistance such as metal or semiconductor.

On the other hand, at the intersections 41 and 42, the data line 31 and the timing line 32
The data line 31 and the GND wiring 53 are connected to the insulating films 33 and 3 respectively.
Crossed with 5 insulated. Transistor 3
Reference numeral 9 denotes a TFT, which includes a semiconductor layer 40, a gate insulating film 34, a gate electrode 32 'integrally formed with the timing line 32, and a TF.
The wiring 31 ′ connecting the source region of T and the data line 31 and the TFT
Wiring 38 connecting the drain region of the pixel electrode 45 and the pixel electrode 45. The pixel electrode 45 is an electrode that holds the charge supplied from the data line and drives the liquid crystal, and is made of a transparent conductive material.

The charge storage capacitor 44 includes a semiconductor layer 43 which is a first electrode, an insulating film 36 which is a dielectric film, and a pixel electrode 45 which is a second electrode.
Consists of. Then, the semiconductor layer 43 is connected to the GND wiring 53 held at a constant potential. This charge storage capacity 44
Can be omitted if the pixel area is large to some extent. Of course, in that case, the GND wiring 53 becomes unnecessary. In addition, in this embodiment, the GND wiring 53 is provided separately from the timing line 32, but instead of being provided on the GND wiring, the timing line of the next row, that is, the timing line of the (j + 1) th row may be used. Good.

In this embodiment, the semiconductor layers 46 and 4 are formed on the transparent insulating substrate.
7, 40, 43 are formed, and an insulating film 3 is formed on each of the semiconductor layers.
3, 35, 34, 36 are formed, and wiring layers 31, 32, 38, 53 are further formed.
And forming a pixel electrode 45 made of a transparent conductor,
Since it has a four-layer structure, the photo-etching process can be manufactured in four processes.

This point will be described with reference to FIG. FIG. 4 shows (A)-(B), (C)-(D), and FIG.
It is the figure which showed the (E)-(F) cross section.

First, on a transparent insulating substrate such as quartz glass or Pyrex glass, a semiconductor film such as amorphous silicon or polycrystalline silicon is formed and photoetched into a desired shape to form semiconductor films 41, 42, 40, 43. To get Then 2000 ~
About 5000 insulating films such as SiO ₂ and Al ₂ O ₃ are deposited by the CVD method or plasma oxidation, thermal oxidation or the like, and then photoetched to form the insulating layers 33, 35, 34 and 36. then,
Impurities such as ion implantation are diffused into the semiconductor layer using the insulating film as a mask.

By the way, in a thin-film semiconductor layer, the diffusion rate of impurities is high, and if some heat is applied, the impurities easily diffuse laterally. For example, by implanting impurities in the silicon film, 600
When heat of ℃ is applied for 1 hour, the diffusion distance of impurities in the lateral direction
xj is as large as 10 μm.

As described above, the semiconductor film formed at the intersections 41 and 42 and the semiconductor film forming the charge storage capacitor must have low resistance. On the other hand, the part that becomes the channel region of the transistor 39 needs to have high resistance. Therefore, the length L ₁ of the insulating film 33 or 35 at the crossing portion, the overlap amount L ₃ between the semiconductor film 44 forming the charge storage capacitor and the insulating film 36 partially overlapping the upper layer thereof, L ₃ , the transistor
If the length of the gate insulating film of 39 is L ₂ and the lateral diffusion distance xj due to heat after implantation of impurities is xj, in order to make the channel region of the transistor high resistance and other semiconductor films low resistance, It suffices if the relationship of is established.

L ₁ , 2 × L ₃ <2 × xj <L ₂ (1) In other words, as can be seen from the cross-sectional views of (A)-(B) of FIG. Since impurities are diffused from both ends, if the relationship of L ₁ <2 × xj is satisfied, all the impurities are diffused into the semiconductor layer and the resistance is reduced. Then, in the charge storage capacitor, FIG. (E) - As can be seen from (F) cross section, with respect to the overlap portion L _3, since the observed impurities from the left come to spread, L ₃ <xj the relationship Should be satisfied. Since the (D) as seen from the sectional view, the impurity from the right and left sides with respect to L ₂ is diffused, - finally, the transistor portion, FIG. (C)
If the relationship of 2 × xj <L ₂ is not satisfied, it becomes impossible to secure a channel region in which impurities are not diffused. Therefore, by organizing the above, the relationship shown in the equation (1) is obtained. Then, by setting L ₁ , L ₂ , and L ₃ so as to satisfy such a relationship, the process can be simplified and a low resistance region and a high resistance region can be formed at the same time.

Finally, the wiring layer 32, 31, 38, 53 and the pixel electrode 45 are formed to complete the display device.

FIG. 5 illustrates the diffusion distance xj of FIG.
A semiconductor layer 51 is formed on a substrate 50, and a gate insulating film 52 is formed thereon. Then, using the insulating film 52 as a mask, impurities are implanted and diffused. At this time, the lateral diffusion distance xj extends from the edge of the insulating film into the region below the insulating film.

As the mask material at this time, the Si film on the insulating film
₃ N ₄ is piled up to make it thicker, etching off after diffusion,
Different materials may be used for the diffusion mask material and the insulating material.

Furthermore, if a transparent conductive film is used for the wirings 31, 32, 38, 53 used in the present invention, the same material as the pixel electrode 45 is used, and the film forming step and the photoetching step can be each simplified once.

As described above, according to the present invention, the liquid crystal display device can be formed by the minimum film forming process 3 times and the photo etching process 3 times, that is, the liquid crystal display device can be formed by about half the process of the related art. It enables cost reduction. In addition, by providing an independent charge storage capacitor without increasing the manufacturing process or changing the process,
It is possible to achieve a liquid crystal display device capable of retaining sufficient electric charges and excellent in writing / holding operations.

Then, since the first electrode of the charge storage capacitor and the wiring for holding the first electrode at a constant potential are separate members and a low resistance member can be used for the constant potential line, the wiring can be long. It is possible to easily deal with large-sized panels.

Further, since the insulating film for holding the charge is the same as the gate insulating film of the thin film transistor, the insulating film is sufficiently thin, and it is possible to form the charge holding capacitor having a large capacity per unit area. It is possible to secure a sufficient capacity, and it is possible to secure a sufficient aperture ratio even in a transmissive display device.

[Brief description of drawings]

FIG. 1 shows a liquid crystal pixel cell using a TFT. FIG. 2 is a drive waveform of the cell of FIG. FIG. 3 is a plan view of a pixel cell using the TFT of the present invention. FIG. 4 is a sectional view of FIG. FIG. 5 is a diagram showing lateral diffusion. 10 …… TFT, 11 …… Liquid crystal 12 …… Charge holding capacity 31, 32, 38, 53 …… Wiring 40, 43, 46, 47 …… Semiconductor film 33, 34, 35, 36 …… Insulating film 45 …… Pixel electrode 51 …… Semiconductor film, 52 …… Diffusion mask

Claims (1)

[Claims] 1. A liquid crystal is sandwiched between a pair of glass substrates, and a plurality of data lines and timing lines are arranged so as to intersect with each other on one substrate of the glass substrates. A thin film transistor made of non-single-crystal silicon is formed in the vicinity of the intersection of, the source region of the thin film transistor is connected to the data line, the gate electrode of the thin film transistor is connected to the timing line, and the drain region of the thin film transistor is In a method of manufacturing a liquid crystal display device, which is connected to a pixel electrode that drives the liquid crystal, and in which the pixel electrode is formed with a charge storage capacitor that stores a charge supplied from the data line, the source region of the thin film transistor, The semiconductor layer forming the channel region and the drain region and the first electrode of the charge storage capacitor are formed of the amorphous silicon. And a second step of forming a gate insulating film of the thin film transistor and a dielectric film covering the first electrode by a length L ₃ with the same insulating film, and masking the same insulating film. As a third step of implanting impurities into the semiconductor layer and the first electrode and thermally diffusing the impurities, and the timing line and the first line substantially parallel to the timing line.
A fourth step of forming a constant potential line formed so as to cross over the electrode of the metal material by a metal material; and a fifth step of forming the pixel electrode so as to partially cover the dielectric film.
2 × L ₃ <2 × xj <L ₂ , where xj is between the length L ₂ in the channel direction of the gate insulating film when implanting the impurities and the L _3. A method of manufacturing a liquid crystal display device, characterized in that a relationship of a diffusion distance due to the thermal diffusion is established.