JPH07235774A - Formation of insulation film - Google Patents

Abstract

PURPOSE:To reduce polishing cracks and to solve problems such as etching residue of wiring metal generated in a following process due to polishing cracks by forming a photosensitive polyimide film on a surface of an insulation film which is mechanically polished. CONSTITUTION:A glass plate is used as a substrate 2 and polyimide 4 is applied thereto by using a spin coater. A film thickness of the polyimide is made 20mum after fully cured and tape polishing is performed for a surface thereof (the state shown in (b) wherein cracks exist in the surface). After tape polishing, photosensitive polyimide 6 is applied by using a spin coater (the state shown in (c)). An application film is made 3mum thick. A through-hole 9 is further formed on a via stud by exposure development for continuity of a wiring (the state of (d)). Thereby, it is possible to prevent line short-circuiting by making a wiring substrate highly flat and by reducing cracks of the surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thick film / thin film mixed multilayer substrate, a printed circuit board and a semiconductor substrate, and more particularly to a method of flattening a substrate having fine and high aspect ratio wiring and through holes and forming an insulating film. Regarding

[0002]

2. Description of the Related Art In the substrate shown in FIG. 1, when an insulating film 4 is formed on a wiring or via stud, a step 3 due to the wiring or via stud 1 appears on the surface of the substrate.
This step on the substrate surface becomes an obstacle to highly accurate wiring formation in the subsequent wiring process. That is, as the number of wiring layers increases, there is a problem that the surface step becomes more severe and it becomes difficult to form the upper insulating layer and the wiring pattern.

The mechanical polishing for reducing the level difference on the substrate surface is described in Japanese Patent Laid-Open No. 4-84495.

Therefore, in order to eliminate the above-mentioned step, mechanical polishing is performed to flatten the surface. However, due to polishing scratches at that time, wiring metal etching residue or the like occurs in a later step, causing a short circuit problem. It was

[0005]

[Patent Document 1] Japanese Patent Application Laid-Open No. 4-84495
The publication describes a method of polishing the resin on the surface melted from the through hole with a belt sander. Inclusion of mechanical polishing has a great effect on planarization. However, when it is actually introduced into the substrate manufacturing process, there is a problem that short circuit occurs due to etching metal wiring residue and the like in the subsequent process.

The present invention realizes a high degree of flatness by polishing and further reduces polishing scratches. In the planar polishing as in the above-mentioned conventional technique, a short circuit between lines was caused by polishing scratches due to excessive polishing, but the possibility is reduced by reducing the scratches on the surface.

[0007]

In order to solve the above-mentioned problems, a method of forming a film thickness of an insulating layer thicker than a required film to mechanically flatten a step of wiring and then reducing scratches is proposed. You can use it.

That is, this is a method of flattening the steps by tape polishing or the like and then forming a photosensitive polyimide on the scratches to reduce the polishing scratches. Further, patterning is performed using photosensitive polyimide in order to achieve electrical continuity with the upper wiring.

[0009]

In the present invention, the steps on the surface of the substrate are planarized by mechanically polishing. By this polishing, the surface step difference on the surface can be significantly flattened. On the other hand,
As the wiring becomes denser and finer, due to polishing scratches,
In the subsequent process, the wiring metal remained unetched, causing a problem such as a short circuit. In order to solve this problem, a reduction treatment of polishing scratches is performed after the mechanical polishing to solve the problems such as the etching residue of the wiring metal generated in the subsequent process due to the polishing scratches.

[0010]

EXAMPLE FIG. 2 shows a method for reducing the step difference on the substrate surface and the scratches on the resin surface. A glass plate is used as the substrate 2, and polyimide 4 (Hitachi Chemical Industry Co., Ltd. PI
Q) was applied using a spin coater. The film thickness of the polyimide was 20 μm after full cure, and the surface was tape-polished (state of FIG. 2b: scratches exist on the surface). Polishing tape (Dainippon Micro Coating Co., Ltd.)
The products manufactured by # 1000, # 2000, and # 4000 were used. The polishing conditions are shown in Table 1.

This apparatus has a structure in which the tape vibrates (tape frequency in Table 1) and increases the polishing rate.
After tape polishing, photosensitive polyimide 6 (Photo-PIQ, Hitachi Chemical Co., Ltd.) was applied using a spin coater (state of FIG. 2c). The coating film thickness was 3 μm.
Further, through holes 9 were formed on the via studs by exposure and development in order to establish electrical connection with the upper wiring. A film thickness of 1 μm was obtained after full curing (state of FIG. 2d). The results of measuring the surface roughness are shown in Table 2.

[0012]

[Table 1]

[0013]

[Table 2]

FIG. 3 shows a portion measured at each step of the above processing. The height from the surface of the insulating material to the top of the via stud is 10 in FIG. 3, and the height from the surface of the insulating material to the wiring portion is 11 in FIG. Table 3 shows the change in level difference of the wiring.

[0015]

[Table 3]

As a result, the level difference between the via stud portion and the wiring portion was highly flattened to 2.0 μm, demonstrating the effectiveness of the present invention. Also, the scratch on the flat part has a height difference of 0.06.
It was highly flattened to μm.

[0017]

According to the present invention, it is possible to prevent a short circuit between lines by highly flattening the wiring board and reducing scratches on the surface.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a wiring board.

FIG. 2 is a diagram showing a method for producing a circuit board to which the present invention is applied.

FIG. 3 is a diagram showing a step measuring portion.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Wiring, 2 ... Substrate, 3 ... Step difference part, 4 ... Insulating material, 5 ... Surface enlarged view, 6 ... Flattening material, 7 ... Wiring height 20 μm, 8 ... Via stud height 20 μm, 9 ... Through hole, 10 ... Wiring + height of via stud, 11 ... Height of via stud.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 23/14 H05K 3/22 B 7511-4E (72) Inventor Tetsuya Yamazaki Totsuka Ward, Yokohama City, Kanagawa Prefecture Hitachi Engineering Co., Ltd. 292, Yoshidacho (72) Inventor Hidetaka Shigi 292 Yoshidacho Co., Ltd., Totsuka-ku, Yokohama, Kanagawa

Claims (6)

[Claims] 1. A method for forming an insulating film, which comprises forming a photosensitive polyimide film on the surface of the insulating film that has been mechanically polished. 2. A photosensitive polyimide film is formed on the surface of the insulating film mechanically polished according to claim 1, and through holes and patterns are formed in the photosensitive polyimide film. Method for forming insulating film. 3. A method for forming an insulating film, characterized in that a scratch due to mechanical polishing according to claim 1 is covered with a film of a photosensitive polyimide. 4. A printed thick film thin film hybrid multilayer substrate, comprising an insulating film formed by the method for forming an insulating film according to claim 1. 5. A circuit board having an insulating film formed by the method for forming an insulating film according to claim 1. 6. A semiconductor substrate having an insulating film formed by the method for forming an insulating film according to claim 1.