JPH07235758A - Circuit substrate - Google Patents

Abstract

PURPOSE:To provide a circuit substrate capable of reducing the size by preventing deviation in the position of surface mount. parts until cream solder is hardened and by omitting through-holes. CONSTITUTION:A substrate 1 is formed, the surface of which is formed with a connecting pattern connected to a signal line pad 10 and a signal line pad 10 connected to a lead wire 215 of a surface mounting part 20 and the inner layer of which is formed with inner layer conductive patterns 11 and 12; lead wire inserting recesses 22 and 23 are formed in this substrate; and the position of the surface mounting part 20 is determined by inserting the lead wires 21V and 21G of the surface mounting parts 20 to the lead wire inserting recesses 22 and 23. And the through-holes are omitted by directly connecting inner layer conductive pattern 11 or 12 exposed to the bottom of lead inserting recesses 22 and 23, thereby miniaturizing a circuit substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a signal line pad to which surface mount components are connected and a connection pattern connected to the signal line pad formed on the surface, and at least one or more inner layer conductive patterns are formed on the inner layer. Printed circuit board.

[0002]

2. Description of the Related Art In recent electric equipment, a multilayer circuit board is frequently used in order to improve wiring efficiency. An example of the related art will be described below with reference to FIG. 2A is a plan view of the substrate 1, FIG. 2B is a cross-sectional view taken along the line AA in FIG. 2A, and FIG. 2C is a line B-B taken in FIG. 2A. FIG. As shown in FIGS. 2B and 2C, the substrate 1 is formed by joining three insulating plates 2, 3 and 4, and through holes 5 are formed in these insulating plates 2, 3 and 4.
Are formed. Then, on the surface of the uppermost insulating plate 2, lands 6, 7 continuous from the through hole 5, a VCC pad 8 connected to the land 6, a GND pad 9 connected to the land 7, and a large number of Signal line pad 10 and
A connection pattern (not shown) connected to these signal line pads 10 is formed. Further, a VCC conductive pattern 11 which is an inner layer conductive pattern connected to the land 6 is formed on the lower surface of the insulating plate 3 of the next layer, and an upper layer GN which is an inner layer conductive pattern connected to the land 7 is formed on the upper surface.
The D conductive pattern 12 is formed. Further, lands 13 and 14 continuous from the through hole 5 are formed on the lower surface of the lowermost insulating plate 4. Further, on the surface of the uppermost insulating plate 2, a symbol mark 16 indicating the mounting position of the corresponding surface mount component 15 is printed corresponding to each surface mount component 15.

When the surface mount component 15 such as an IC package is connected to the circuit board 18 thus formed, first, the VCC pad 8, the GND pad 9 and the signal line pad 10 on the board 1 are mounted. 2 is coated with cream solder, and as shown in FIG. 2C, the lead wire 17V for power input of the surface mount component 15 is placed on the VCC pad 8,
As shown in (b), connect the ground lead wire 17G to GND.
The surface mount component 15 is mounted on the surface of the substrate 1 by mounting it on the pad 9 and mounting the signal wire input / output lead wire 17S on the signal wire pad 10 and melting and cooling the cream solder to solidify it. In this state, the power input lead wire 17V
Is connected to the VCC conductive pattern 11 through the VCC pad 8 and the through hole 5, and the grounding lead wire 17G is connected to the GND conductive pattern 12 through the GND pad 9 and the through hole 5.

[0004]

In the conventional structure in which the lead wires 17V and 17G are connected to the VCC conductive pattern 11 or the GND conductive pattern 12 through the through hole 5, the through hole 5 of the surface mount component 15 is connected. Since it has to be positioned on the outside and formed on the substrate 1, the substrate 1 becomes large. Also, before the cream solder hardens,
The position of the surface mount component 15 on the substrate 1 may shift due to vibration.

[0005]

According to the present invention, a signal line pad to which a lead wire of a surface mount component is connected and a connection pattern connected to the signal line pad are formed on the surface, and an inner layer conductive pattern is formed on the inner layer. And a depth of reaching the inner layer conductive pattern by arranging a lead wire insertion recess into which the lead wire of the surface mount component for connecting to the inner layer conductive pattern is inserted within the projected area of the surface mount component. It is a circuit board formed on the above substrate.

[0006]

It is possible to directly connect the lead wire of the surface mount component to the inner layer conductive pattern in a state where the lead wire is inserted into the lead wire insertion recess.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIG. The same parts as those described in FIG. 2 will be described using the same reference numerals. FIG. 1A is a plan view of the substrate 1, FIG.
1B is a cross-sectional view taken along the line C-C in FIG.
1C is a cross-sectional view taken along the line D-D in FIG. As shown in FIGS. 3B and 3C, the substrate 1 is formed by joining three insulating plates 2, 3, and 4.
A large number of signal line pads 10 are provided on the surface of the uppermost insulating plate 2.
And a connection pattern (not shown) connected to these signal line pads 10. Further, a VCC conductive pattern 11 which is an inner layer conductive pattern is formed on the lower surface of the insulating plate 3 of the next layer, and a GND conductive pattern 12 which is an inner layer conductive pattern is formed on the upper surface. Furthermore, the symbol mark 16 corresponding to each surface mount component 20 is printed on the surface of the uppermost insulating plate 2.

Then, the lead wire insertion recesses 22 and 23 into which the lead wires 21V and 21G of the surface mount component 20 are inserted.
Are arranged within the projected area of the surface-mounted component 20 and formed on the substrate 1. One lead wire insertion recess 22
Is formed with a depth reaching the VCC conductive pattern 11 from the surface of the uppermost insulating plate 2, and the other lead wire insertion recess 23 has a depth reaching the GND conductive pattern 12 from the surface of the uppermost insulating plate 2. Has been formed.
As shown in FIG. 1C, the GND conductive pattern 1
A space 24 is formed in a part of 2 to avoid contact with the lead wire 21V for power input connected to the VCC conductive pattern 11 therebelow.

When the surface mount component 20 such as an IC package is connected to the circuit board 25 thus formed, first, the VCC conductive pattern 11 and the GND conductive pattern exposed from the lead wire insertion recesses 22 and 23 are formed. 1
2 and the signal line pad 10 are coated with cream solder, and as shown in FIG. 1C, the lead wire 21V for inputting the power source of the surface mount component 20 is inserted into the lead wire insertion concave portion 22 to be VCC. The lead wire 21G for grounding is placed on the conductive pattern 11 and, as shown in FIG.
3 is mounted on the GND conductive pattern 12, the lead wire 21S for signal line input / output is mounted on the signal line pad 10, and the cream solder is melted, cooled, and solidified, so that the surface mount component 20 is mounted on the surface of the substrate 1. To implement. In this state,
The lead wire 21V for power input is the VCC conductive pattern 11
The grounding lead wire 21G is directly connected to the GND conductive pattern 12.

As described above, since the lead wires 21V and 21G can be connected to the VCC conductive pattern 11 or the GND conductive pattern 12 with the lead wires 21V and 21G inserted in the lead wire insertion recesses 22 and 23, the board can be set before the cream solder is solidified. 1
On the other hand, the surface mount component 20 does not move due to vibration or the like. In addition, the lead wires 21V and 21G are connected to the surface mount component 2
Since it can be directly connected to the VCC conductive pattern 11 or the GND conductive pattern 12 within the projected area of 0, it is not necessary to form a through hole or a land around the surface mount component 20 on the substrate 1, and that portion is connected. It can be effectively used as a pattern arrangement space, and the substrate 1 can be downsized accordingly.

Although not shown, a wiring pattern is also formed on the lower surface of the lowermost insulating plate 4. Therefore, in this embodiment, a four-layer circuit in which three insulating plates 2, 3 and 4 are laminated is provided. However, the present invention is not limited to a circuit board having four or more layers, and a signal line pad to which surface mount components are connected and a connection pattern connected to the signal line pad are provided on the surface. The present invention is also applied to a circuit board in which at least one inner layer conductive pattern is formed on the inner layer.

[0012]

According to the present invention, the lead wire of the surface mount component mounted on the surface of the substrate can be connected to the inner layer conductive pattern in a state of being inserted into the lead wire insertion recess, so that the cream solder is hardened. In addition, it is possible to prevent surface mount parts from moving due to vibration etc.
Further, since the lead wire can be directly connected to the inner layer conductive pattern within the projected area of the surface mount component, it is not necessary to form a through hole or land around the surface mount component on the substrate, and the corresponding portion can be connected pattern. Can be effectively used as an array space of, and the substrate can be downsized accordingly.

[Brief description of drawings]

1A and 1B show a part of a substrate according to an embodiment of the present invention, in which FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along line CC in FIG. 1A, and FIG. It is sectional drawing of the DD line part in 1 (a).

FIG. 2 shows a part of a conventional substrate, (a) is a plan view, (b) is a cross-sectional view taken along the line AA in (a),
(C) is sectional drawing of the BB line | wire part in (a). Is.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate 10 Signal line pad 11, 12 Inner layer conductive pattern 20 Surface mount component 21V, 21G, Lead wire 21S connected to inner layer conductive pattern 21S Lead wire 22, 23 connected to signal line pad Lead wire insertion recess

Claims (1)

[Claims] 1. A substrate having a signal line pad to which a lead wire of a surface mount component is connected and a connection pattern connected to the signal line pad formed on the surface and an inner layer conductive pattern formed on the inner layer, the inner layer being provided. The lead wire insertion recess, into which the lead wire of the surface mount component for connecting to the conductive pattern is inserted, is formed in the substrate with a depth reaching the inner layer conductive pattern by being located within the projected area of the surface mount component. Circuit board characterized by.