JP3228841B2 - Shield device - Google Patents
Shield deviceInfo
- Publication number
- JP3228841B2 JP3228841B2 JP26081394A JP26081394A JP3228841B2 JP 3228841 B2 JP3228841 B2 JP 3228841B2 JP 26081394 A JP26081394 A JP 26081394A JP 26081394 A JP26081394 A JP 26081394A JP 3228841 B2 JP3228841 B2 JP 3228841B2
- Authority
- JP
- Japan
- Prior art keywords
- bga
- substrate
- shield
- shield device
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はセラミックＢＧＡ（Ball
grid array ）を用いて高密度実装した基板におけるシ
ールド装置に関する。The present invention relates to a ceramic BGA (Ball
The present invention relates to a shield device on a substrate mounted at high density using a grid array.
【０００２】[0002]
【従来の技術】近来、電子機器のプリント基板はデジタ
ル回路化され、当然のことながら高密度実装が施され、
そのため他の回路との妨害が生じないようにシールドに
ついて配慮しなければならない。2. Description of the Related Art In recent years, printed circuit boards of electronic devices have been converted into digital circuits, and of course, high-density mounting has been performed.
Therefore, shields must be considered so as not to interfere with other circuits.
【０００３】従来のシールド装置について説明する。図
４に示すように、枠状をした金属製のシールドケース本
体１５に四角形状のプリント基板１６を挿入し、前記シ
ールドケース本体１５の周板に形成した複数の固定爪２
４を折り曲げてプリント基板１６を仮固定する。さらに
プリント基板１６の表裏の周縁に形成した半田付け部２
２をシールドケース本体１５の固定爪２４のいくつかに
半田付けして、プリント基板１６とシールドケース１５
を固定する。さらにプリント基板１６の面に実装した複
数のＩＣ２３の表面に放熱板１７を当接し、また、プリ
ント基板１６の反対側のＩＣ部にも放熱板１８を当接
し、これらを固定用ビス１９で締め付ける。さらにシー
ルドケース蓋２０，２１でシールドケース本体１５の両
側を覆い、シールドケース蓋２０，２１の下部の半田付
け部２５とプリント基板１６とを半田付けするという構
成としている。[0003] A conventional shield device will be described. As shown in FIG. 4, a rectangular printed circuit board 16 is inserted into a frame-shaped metal shield case body 15, and a plurality of fixed claws 2 formed on a peripheral plate of the shield case body 15.
The printed circuit board 16 is temporarily fixed by bending the printed circuit board 4. Further, the soldering portion 2 formed on the front and back peripheral edges of the printed circuit board 16
2 are soldered to some of the fixing claws 24 of the shield case body 15 so that the printed circuit board 16 and the shield case 15
Is fixed. Further, the heat radiating plate 17 is in contact with the surface of the plurality of ICs 23 mounted on the surface of the printed circuit board 16, and the heat radiating plate 18 is also in contact with the IC portion on the opposite side of the printed circuit board 16, and these are fastened with fixing screws 19. . Further, both sides of the shield case main body 15 are covered with the shield case lids 20 and 21, and the soldered portion 25 below the shield case lids 20 and 21 and the printed circuit board 16 are soldered.
【０００４】[0004]
【発明が解決しようとする課題】ところで上述の従来の
シールド装置の構成では、シールドケースを用いるため
に構成部が大型化する。また、その組立てにおいても半
田付け箇所が多く、組立て工数が多くなる。In the structure of the above-mentioned conventional shield device, however, the size of the component is increased due to the use of the shield case. In addition, there are many soldering points in the assembling, and the number of assembling steps increases.
【０００５】本発明は前記従来の問題に留意し、シール
ドケースを不要にし、小型で、しかも所期のシールドが
得られるシールド装置を提供することを目的とする。An object of the present invention is to provide a shield device which does not require a shield case, is small in size, and can obtain an intended shield, taking the above conventional problems into consideration.
【０００６】[0006]
【課題を解決するための手段】前記目的を達成するため
に本発明は、基板上のパターンにＬＳＩチップを接続し
て設けた上にシールド板を設けるとともに、前記基板の
周辺にＢＧＡのピンピッチもしくはピンピッチの整数倍
の間隔でスルーホールを形成し、前記スルーホールの下
部に電極端子となる半田ボールを設けるＢＧＡセラミッ
ク基板と、前記ＢＧＡセラミック基板を実装すると共に
前記電極端子を囲んでアース箔を形成する多層基板とを
備え、前記多層基板の内層に配線パターンを設ける構成
とする。In order to achieve the above object, the present invention relates to a method of connecting an LSI chip to a pattern on a substrate.
In addition to providing a shield plate on the
Around the BGA pin pitch or an integer multiple of the pin pitch
Form through holes at intervals of
BGA ceramic with solder balls to be used as electrode terminals
Mounting the substrate and the BGA ceramic substrate
A multilayer substrate surrounding the electrode terminals to form a ground foil.
And a configuration in which a wiring pattern is provided on an inner layer of the multilayer substrate .
【０００７】[0007]
【作用】上記構成のシールド装置において、ＢＧＡセラ
ミック基板の周辺の半田ボールのうちアース端子となる
ものは多層基板側で前記半田ボール群を囲むアース箔に
接続されるので、上部のシールド板とともにシールド
し、他に別個のシールドケースを不要とすることとな
る。In the shield device having the above-mentioned structure, the solder ball around the BGA ceramic substrate which is to be the ground terminal is connected to the ground foil surrounding the solder ball group on the side of the multi-layer substrate, so that it is shielded together with the upper shield plate. However, a separate shield case is not required.
【０００８】[0008]
【実施例】以下に本発明の一実施例を図１および図２を
参照して説明する。図において１はＢＧＡセラミック基
板であり、その上面のモールド樹脂４で装着されたＬＳ
Ｉチップパターン２にはＬＳＩを実装しており、さらに
前記ＬＳＩチップパターン２を含むＢＧＡセラミック基
板１の上面はシールド板５で覆われている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In the figure, reference numeral 1 denotes a BGA ceramic substrate, and LS mounted on a top surface thereof with a molding resin 4.
An LSI is mounted on the I chip pattern 2, and the upper surface of the BGA ceramic substrate 1 including the LSI chip pattern 2 is covered with a shield plate 5.
【０００９】前記ＢＧＡセラミック基板１の周辺部に
は、ピンピッチもしくはピンピッチの整数倍の間隔でス
ルーホール３を形成してあり、この各スルーホール３の
下部にそれぞれ電極端子となる半田ボール６を設けてい
る。そして前記半田ボール６を備えたＢＧＡセラミック
基板１は回路端子をもつ多層基板７の表面側の外層８に
前記半田ボール６を溶かして接合して実装される。前記
外層８におけるＢＧＡセラミック基板１の周辺にはアー
ス箔を設けてアースされており、また、多層基板７の裏
面側の外層１０にはほぼ全面にわたりアース箔１１が形
成されている。なお配線パターンは多層基板７の内層９
において配線する。In the peripheral portion of the BGA ceramic substrate 1, through holes 3 are formed at pin pitches or at intervals of an integral multiple of the pin pitch. Solder balls 6 serving as electrode terminals are provided below each of the through holes 3. ing. The BGA ceramic substrate 1 provided with the solder balls 6 is mounted by melting and bonding the solder balls 6 to an outer layer 8 on the front side of a multilayer substrate 7 having circuit terminals. A ground foil is provided around the BGA ceramic substrate 1 in the outer layer 8 to be grounded, and a ground foil 11 is formed on almost the entire outer layer 10 on the back surface side of the multilayer substrate 7. The wiring pattern is the inner layer 9 of the multilayer substrate 7.
Wiring.
【００１０】上記構成においては、半田ボール６が電極
端子となり、所要の接続が行なわれるとともに、半田ボ
ール、すなわち電極端子が多層基板７の外層８のアース
箔で囲まれそして、そのアース箔とシールド板５とでシ
ールドすることができる。また、多層基板７の外層１０
に施したアース箔１１とともに十分なシールド効果が得
られ、シールドケースを不要とし、組立の自動化を可能
にする。In the above configuration, the solder balls 6 serve as electrode terminals, and the required connection is made. In addition, the solder balls, ie, the electrode terminals, are surrounded by the ground foil of the outer layer 8 of the multilayer substrate 7, and the ground foil and the shield It can be shielded with the plate 5. The outer layer 10 of the multilayer substrate 7
A sufficient shielding effect can be obtained together with the ground foil 11 applied to the above, making a shield case unnecessary and enabling the assembly to be automated.
【００１１】図３は本発明の他の実施例を示す。この実
施例はＥＭＩフィルターのシールドに係るものであり、
ＥＭＩフィルター本体１２の側面下部および裏面の周辺
には全てアース箔１３を設けている。前記ＥＭＩフィル
ター本体１２の裏面にはアース電極１４、入力端子部１
５、出力端子部１６が設けられ、アース電極１４は前記
アース箔１３に接続され、入力端子部１５と出力端子部
１６はアース箔１３によって囲まれている。FIG. 3 shows another embodiment of the present invention. This embodiment relates to the shielding of an EMI filter.
The ground foil 13 is provided all around the lower part of the side surface and the back surface of the EMI filter main body 12. A ground electrode 14 and an input terminal 1 are provided on the back of the EMI filter body 12.
5, an output terminal portion 16 is provided, the ground electrode 14 is connected to the ground foil 13, and the input terminal portion 15 and the output terminal portion 16 are surrounded by the ground foil 13.
【００１２】上記構成のＥＭＩフィルタ本体１２は、図
示しない基板のパターンにその下面を接続するが、スル
ーホールを用いてＥＭＩフィルターの下側でパターン設
計することにより上部に配線箔が露出することなく実装
できることから、シールドケースを用いなくてもシール
ドされ、他の回路よりの妨害の影響を受けにくい。The lower surface of the EMI filter body 12 having the above structure is connected to a pattern of a substrate (not shown). By designing the pattern on the lower side of the EMI filter using through holes, the wiring foil is not exposed on the upper side. Because it can be mounted, it is shielded without using a shield case, and is less susceptible to interference from other circuits.
【００１３】前記のように各実施例においては、シール
ドケースを用いることなくシールドされ、構成部を小型
にでき、しかも組立てを容易にする。As described above, in each of the embodiments, the shield is performed without using the shield case, the size of the components can be reduced, and the assembly is facilitated.
【００１４】[0014]
【発明の効果】前記実施例の説明より明らかなように、
本発明のシールド装置は下記の効果を得ることができ
る。 （１）ＢＧＡセラミック基板の周辺に半田ボール端子を
設けているため、多層基板側でこれを囲むアース箔を設
けることにより、シールドケースを用いなくてもシール
ドできる基板実装ができる。 （２）ＢＧＡセラミック基板を用いているため実装が容
易であり、実装面積の縮小を図ることができる。As is clear from the description of the above embodiment,
The shield device of the present invention can obtain the following effects. (1) Since the solder ball terminals are provided around the BGA ceramic substrate, by providing an earth foil surrounding the solder ball terminals on the multi-layer substrate side, it is possible to mount the substrate without using a shield case. (2) Since the BGA ceramic substrate is used, mounting is easy and the mounting area can be reduced.
【図１】（ａ）は本発明の一実施例のシールド装置の断
面図 （ｂ）は同シールド装置の要部断面図 （ｃ）は同シールド装置の要部斜視図1A is a cross-sectional view of a shield device according to an embodiment of the present invention; FIG. 1B is a cross-sectional view of a main part of the shield device;
【図２】同シールド装置の下面を示す斜視図FIG. 2 is a perspective view showing a lower surface of the shield device.
【図３】（ａ）は本発明の他の実施例のシールド装置の
斜視図 （ｂ）は同シールド装置の下面を示す斜視図3A is a perspective view of a shield device according to another embodiment of the present invention, and FIG. 3B is a perspective view showing a lower surface of the shield device.
【図４】従来のシールド装置の分解斜視図FIG. 4 is an exploded perspective view of a conventional shield device.
１ ＢＧＡセラミック基板 ２ ＬＳＩチップパターン ３ スルーホール ４ モールド樹脂 ５ シールド板 ６ 半田ボール ７ 多層基板 ８ 外層 ９ 内層 １０ 外層 １１ アース箔 Reference Signs List 1 BGA ceramic substrate 2 LSI chip pattern 3 Through hole 4 Mold resin 5 Shield plate 6 Solder ball 7 Multilayer substrate 8 Outer layer 9 Inner layer 10 Outer layer 11 Ground foil
フロントページの続き (56)参考文献 特開 平６−204681（ＪＰ，Ａ) 特開 昭63−86600（ＪＰ，Ａ) 特開 平５−14015（ＪＰ，Ａ) 特開 平６−268407（ＪＰ，Ａ) 特開 平６−275463（ＪＰ，Ａ) 特開 平４−79352（ＪＰ，Ａ) 実開 平６−52191（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 9/00 Continuation of front page (56) References JP-A-6-204681 (JP, A) JP-A-63-86600 (JP, A) JP-A-5-14015 (JP, A) JP-A-6-268407 (JP) JP-A-6-275463 (JP, A) JP-A-4-79352 (JP, A) JP-A-6-52191 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB Name) H05K 9/00
Claims (1)
して設けた上にシールド板を設けるとともに、前記基板
の周辺にＢＧＡのピンピッチもしくはピンピッチの整数
倍の間隔でスルーホールを形成し、前記スルーホールの
下部に電極端子となる半田ボールを設けるＢＧＡセラミ
ック基板と、前記ＢＧＡセラミック基板を実装すると共
に前記電極端子を囲んでアース箔を形成する多層基板と
を備え、前記多層基板の内層に配線パターンを設けるこ
とを特徴とするシールド装置。An LSI chip is connected to a pattern on a substrate.
A shield plate is provided on the
Around the BGA pin pitch or an integer of the pin pitch
Form through holes at twice the spacing,
BGA ceramic with solder balls at the bottom to serve as electrode terminals
And mounting the BGA ceramic substrate
A multilayer substrate surrounding the electrode terminals to form a ground foil;
And providing a wiring pattern on the inner layer of the multilayer substrate.
And a shielding device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26081394A JP3228841B2 (en) | 1994-10-26 | 1994-10-26 | Shield device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26081394A JP3228841B2 (en) | 1994-10-26 | 1994-10-26 | Shield device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08125379A JPH08125379A (en) | 1996-05-17 |
| JP3228841B2 true JP3228841B2 (en) | 2001-11-12 |
Family
ID=17353118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26081394A Expired - Fee Related JP3228841B2 (en) | 1994-10-26 | 1994-10-26 | Shield device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3228841B2 (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2324649A (en) * | 1997-04-16 | 1998-10-28 | Ibm | Shielded semiconductor package |
| US6805278B1 (en) | 1999-10-19 | 2004-10-19 | Fci America Technology, Inc. | Self-centering connector with hold down |
| TW531948B (en) * | 1999-10-19 | 2003-05-11 | Fci Sa | Electrical connector with strain relief |
| US6791845B2 (en) | 2002-09-26 | 2004-09-14 | Fci Americas Technology, Inc. | Surface mounted electrical components |
| US6900389B2 (en) | 2003-01-10 | 2005-05-31 | Fci Americas Technology, Inc. | Cover for ball-grid array connector |
| US8366485B2 (en) | 2009-03-19 | 2013-02-05 | Fci Americas Technology Llc | Electrical connector having ribbed ground plate |
| EP2624034A1 (en) | 2012-01-31 | 2013-08-07 | Fci | Dismountable optical coupling device |
| US8944831B2 (en) | 2012-04-13 | 2015-02-03 | Fci Americas Technology Llc | Electrical connector having ribbed ground plate with engagement members |
| US9257778B2 (en) | 2012-04-13 | 2016-02-09 | Fci Americas Technology | High speed electrical connector |
| USD727852S1 (en) | 2012-04-13 | 2015-04-28 | Fci Americas Technology Llc | Ground shield for a right angle electrical connector |
| USD727268S1 (en) | 2012-04-13 | 2015-04-21 | Fci Americas Technology Llc | Vertical electrical connector |
| USD718253S1 (en) | 2012-04-13 | 2014-11-25 | Fci Americas Technology Llc | Electrical cable connector |
| US9543703B2 (en) | 2012-07-11 | 2017-01-10 | Fci Americas Technology Llc | Electrical connector with reduced stack height |
| USD751507S1 (en) | 2012-07-11 | 2016-03-15 | Fci Americas Technology Llc | Electrical connector |
| USD745852S1 (en) | 2013-01-25 | 2015-12-22 | Fci Americas Technology Llc | Electrical connector |
| USD720698S1 (en) | 2013-03-15 | 2015-01-06 | Fci Americas Technology Llc | Electrical cable connector |
-
1994
- 1994-10-26 JP JP26081394A patent/JP3228841B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08125379A (en) | 1996-05-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5030800A (en) | Printed wiring board with an electronic wave shielding layer | |
| JP3228841B2 (en) | Shield device | |
| US5519580A (en) | Method of controlling solder ball size of BGA IC components | |
| KR100357657B1 (en) | A multi-level electronic package and method for making same | |
| JP3111053B2 (en) | Multilayer circuit board with primary and secondary through holes | |
| EP0489118A4 (en) | Multi-layer circuit board that suppresses radio frequency interference from high frequency signals | |
| JP3287673B2 (en) | Semiconductor device | |
| JP2004134669A (en) | Multilayer substrate with built-in ic chip and its manufacture | |
| JPS616846A (en) | Plug-in package with capacitor | |
| US6369334B1 (en) | Printed circuit board with wire adds and component adds having 7-shaped and semicircular terminations | |
| JP3082579B2 (en) | Shield case | |
| US20050235488A1 (en) | Selective area solder placement | |
| JP3166490B2 (en) | BGA type semiconductor device | |
| US20010040296A1 (en) | Printed-circuit board and method of mounting electric components thereon | |
| JPH02301182A (en) | Printed circuit board for flat mounting structure | |
| JP2734318B2 (en) | Manufacturing method of hybrid integrated circuit device | |
| US20060006533A1 (en) | Motherboard structure for preventing short circuit | |
| JP2021111718A (en) | Electronic apparatus | |
| JPH04262590A (en) | Flexible circuit board | |
| US6009619A (en) | Process for manufacturing an electronic circuit card | |
| JP4212880B2 (en) | Circuit board assembly | |
| JP2933729B2 (en) | Printed wiring board device | |
| JPH0745992Y2 (en) | Grounding structure between electronic parts and shield case | |
| JP3932907B2 (en) | Module board | |
| JPH0336796A (en) | Shielded printed board for surface mount component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080907 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080907 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090907 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090907 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100907 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |