JPH07235195A - Memory circuit - Google Patents

Abstract

PURPOSE:To obtain a memory circuit which can directly hold multi-valued data. CONSTITUTION:The memory circuit comprises a plurality of parallel bistable circuits T1-Tn in which an output voltage when an initial input voltage is removed is converged to low or high voltage according to the relationship of magnitude between the initial input voltage and a threshold voltage, and capacitors C11-C1n respectively connected to outputs of the bistable circuits. The bistable circuits are so connected as to input a common analog voltage X as the initial input voltage. The capacitors ate connected to each other as a common output A. The circuits T1-Tn are so stepwisely set that the respective threshold voltages are relatively different from the initial input voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit for storing analog multi-valued data.

[0002]

2. Description of the Related Art A conventional memory circuit is a digital type which holds two states, a high level and a low level, in a bit unit and cannot directly store analog multi-valued data.

[0003]

Therefore, in order to use the conventional memory circuit in an analog computer to store analog data, an A / D converter is provided at the front stage of the memory and a D / A converter is provided at the rear stage of the memory. The problem is that it must be stored using multiple bits.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide a memory circuit capable of directly holding at least multivalued data.

[0005]

In order to achieve the above object, the memory circuit according to the present invention has a low output voltage when the initial input voltage is removed due to the magnitude relationship between the initial input voltage and the threshold voltage. A plurality of bistable circuits that converge to either a high voltage state are provided in parallel, and the bistable circuits are connected so that a common analog voltage can be input as the initial input voltage, and the threshold voltage of each bistable circuit is initialized. Set stepwise to be relatively different with respect to the input voltage, and connect a capacitance to the output side of each bistable circuit,
It is characterized in that the respective capacitances are connected to each other to form a common output terminal.

[0006]

Embodiments of the memory circuit according to the present invention will be described below.

[0007]

First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a memory circuit according to the present invention. The memory circuit of the first embodiment is
A plurality of bistable circuits T1, T2 provided in parallel, in which the output voltage when the initial input voltage is removed is converged to either a low voltage or a high voltage depending on the magnitude relationship between the initial input voltage and the threshold voltage. , Tn and capacitances C11, C12, C13, ..., C1n connected to the output side of each bistable circuit. A common analog voltage X is connected to each bistable circuit so that a common analog voltage X can be input as an initial input voltage, and each capacitance is connected to each other to form a common output A.

Each of the bistable circuits T1, T2, T3, ... Tn is set stepwise so that the threshold voltage thereof is relatively different from the initial input voltage. In this example, the threshold voltage of each bistable circuit itself is set to be different stepwise at equal intervals.

In the example of FIG. 1, the analog input voltage applied as the initial input voltage increases as the threshold value of each bistable circuit is made to differ stepwise, so that the convergence voltage after the initial input voltage is removed. Are sequentially reversed from T1. Therefore, by capacitively coupling the output voltages of the respective bistable circuits and adding them, it is possible to hold multi-valued data of n values according to the magnitude of the analog input voltage.

In the example of FIG. 1, each bistable circuit inverts the output after convergence to the initial state only when it becomes higher than its own threshold voltage, that is, the output of the bistable circuit with a higher threshold value. When is inverted, all the outputs of the bistable circuit whose threshold is lower than that are inverted, so even if the output of each bistable circuit is not weighted, the multi-valued output Can be set. Therefore, in this embodiment, the convergence voltage of each bistable circuit and the capacitances of the capacitances C11, C12, C13, ..., C1n are set to the same value.

According to the above configuration, the analog input voltage X
Accordingly, for example, as shown in FIG. 2A, it is possible to obtain stepwise multi-valued output with equal intervals for both the input voltage X and the output voltage A.

In order to weight the output of each bistable circuit, there are means for gradually setting the output of the bistable circuit itself and means for gradually setting the capacitance of the capacitance provided on the output side. Conceivable. By any means, as shown in FIG. 2B, for example, the output voltage can be changed exponentially or exponentially with respect to the constant change of the input voltage X.

On the other hand, in the case where the threshold difference of the bistable circuit is not constant and the pitches are unequal, as shown in FIG. You can get the output. Further, an input / output relationship such as that shown in both FIGS. 2B and 2C can be arbitrarily obtained by setting the weighting of the output of the bistable circuit and the threshold value.

FIG. 3 shows a modification of the first embodiment. Capacitors C21, C22, C23, ..., C2n having different capacities are connected to the input side of each bistable circuit. In this example, the threshold values of the bistable circuits are all set to be the same, and the analog input voltage is weighted by capacitance before being input to the bistable circuit, so that the output inversion voltage of the bistable circuit is changed. ing. The other configuration is the same as that of the circuit of FIG. 1, and the input / output relationship can be similarly set arbitrarily.

The bistable circuit is composed of the circuits shown in FIGS. 4 and 5, for example. These circuits are MOS
The Id-Vg characteristic of the FET is recursively used to generate a stable output voltage according to the initial voltage, and this is used as holding data.

The bistable circuit shown in FIG. 4 includes first and second MOS transistors TR1 and TR2 connected so that the drain voltage of one becomes the gate voltages Vg1 and Vg2 of the other. Pull-up resistors R1 and R2 are connected to the drains of the respective transistors, and a voltage Vd is applied to the other end of the resistors. The voltage Vs is applied to the source of each transistor.

Here, the drain currents Id1 and Id2 of the transistors TR1 and TR2 are determined as follows.

[0018]

## EQU1 ## Id1 = (k1 / 2) (W / L) (Vg1-VSL1) ² {1 + λ1 (Vg2-Vd)} (1) Id1 = (k2 / 2) (W / L) (Vg2-VSL2) ² {1 + λ2 (Vg1-Vd)} (2) Vg2 = Vd-Id1R1 (3) Vg1 = Vd-Id2R2 (4) k1 = μ1Cox1 (5) k2 = μ2Cox2 (6) However, W: channel width L: channel length VSL1, VSL2: TR1 and TR2 threshold voltage λ1, λ2: TR1 and TR2 representative indices of output resistance μ1, μ2: TR1 and TR2 mobility in the channel region Cox1, Cox2: per unit area of TR1 and TR2 Gate oxide film capacity

If the input voltage is applied to the gate of the transistor TR1 and the output voltage is obtained from the drain of the transistor TR1, the initial value Vin of the input voltage is once applied to the gate of the transistor TR1 and then the input voltage Vin is removed. The output voltage Vg2 converges to either a high or low convergence value corresponding to the initial voltage Vin.

FIG. 5 shows a modified example of the bistable circuit shown in FIG. 4. The difference from the circuit shown in FIG. 4 is pull-down resistors R1 and R2.
Is connected to the source side of the transistors TR1 and TR2. In this configuration, the equations (3) and (4) are transformed into the following equations (7) and (8).

[0021]

## EQU00002 ## Vg2 = Id1R1 (7) Vg1 = Id2R2 (8)

[0022]

Second Embodiment FIG. 6 is a circuit diagram showing a memory circuit according to a second embodiment. In the second embodiment, as a bistable circuit, 2
It uses a plow-pitch inverter circuit configured by connecting the input and output of each inverter.

That is, the memory circuit according to the second embodiment has three cross-cutting inverter circuits (bistable circuits) T1, T2, T3 composed of two inverters INV1, INV2.
Are provided in parallel, and the output of one inverter INV2 of each crossing inverter circuit is input terminals X, Y, Z.
Then, the output of the other inverter INV2 is capacitively coupled by the capacitances C1, C2, and C3 to form a common output terminal A.

The thresholds of the respective inverter circuits are set to be different stepwise, and the capacitances C1, C2 and C3 are the same so as to simply add the outputs of the respective counter circuits T1, T2 and T3. It is set to capacity.
When used as a memory circuit, the input terminals X, Y and Z are connected to form a common input terminal.

Focusing on one inverter circuit, each inverter INV1, INV2 has one output V
If 1 is H, the other output V2 is L, so it has two stable points. FIG. 7 shows the input / output characteristics of each TASKIGAKE inverter circuit, and E (= E0− | V1−V2
|, E0: reference voltage) and the input voltage V1. In the circuit of FIG. 6, the inverted output with respect to the input is the output of each crossing inverter circuit, so the characteristic can be expressed by a quadratic function in which the coefficient of the quadratic term is negative.

As shown by the arrows in FIG. 7, each crossing inverter circuit converges and stabilizes in the direction in which the potential difference between the input side voltage V1 and the output side voltage V2 increases. Therefore, each crossing inverter circuit functions as a binary memory. The direction of stability is determined according to the input voltage, with the apex of the characteristic curve as the threshold value.

A plurality of such crossing inverter circuits are provided in parallel and the input / output voltage characteristics (threshold value of the circuit) in each crossing inverter circuit are appropriately made different, so that multi-valued output combinations are obtained. A memory circuit can be configured.

For example, as shown in FIG. 8 for the input / output voltage characteristics, the voltage XOU at the output side of each crossing inverter circuit is shown.
If T, YOUT, and ZOUT have characteristic distributions such that the stable point on the high potential side of the circuit above is the intermediate point (threshold value of the circuit), these are combined and added to produce the output voltage. It is possible to hold four gradation voltages depending on the state.

The relationship between the input voltage VIN and the output voltage VOUT is as shown in Table 1 below when the coefficient due to capacitance is taken to be 1. In this case, it functions as a 4-valued multi-valued memory. Moreover, the stage of the output voltage can be arbitrarily set by appropriately changing the capacitance of the capacitance.

[0030]

[Table 1] Input voltage VIN Output voltage VOUT V1 to Va V1 + V1 + V1 Va to V2 V2 + V1 + V1 V2 to V3 V2 + V3 + V1 V3 to V4 V2 + V3 + V4 where Va = (V2-V1) / 2

In contrast to the circuit of FIG. 6, FIG. 9 connects the non-inverting output to the capacitance for the input of each crossing inverter circuit T1, T2, T3. According to such a connection, the EV characteristic of each crossing inverter circuit is inverted from that shown in FIG. 7, and is expressed by a quadratic function having a positive quadratic coefficient.

The circuit of FIG. 6 can be used not only as the above-mentioned application but also as a 3-bit buffered D / A converter. In this case, the characteristics of each inverter circuit are set to be the same, and the capacitance ratio of capacitance is set to 1: 2: 4, for example. As a result, an analog output as shown in Table 2 below can be obtained according to the digital input to each terminal, and this output is held even after the input is cut off. In the input signals in the table, 0 is high level and 1 is low level. Further, the output signal is shown as a value obtained by multiplying the value 0 when the output of each pegging inverter circuit is low level and the value 1 when the output is high level by a coefficient by the capacitance of each capacitance.

[0033]

[Table 2] Input signal Output signal XYZ 0 0 0 0 + 0 + 0 = 0 1 1 0 0 1 + 0 + 0 = 1 0 1 1 0 0 + 2 + 0 = 2 1 1 1 0 1 + 2 + 0 = 3 0 0 1 0 + 0 + 4 = 4 1 0 1 1 1 + 0 + 4 0 + 2 + 4 = 6 1 1 1 1 + 2 + 4 = 7

[0034]

Third Embodiment FIG. 10 shows a third embodiment of the memory circuit according to the present invention. In this example, a flip-flop circuit is used as a bistable circuit.

That is, the memory circuit of FIG. 10 has flip-flop circuits F0, F1,
, Fn are provided in parallel and capacitances C10, C11, C12, ..., C1n for weighting the outputs Y0, Y1, Y2, ..., Yn of the respective flip-flop circuits according to the threshold level.
Are connected, and these capacitances are connected to each other to form an output.

The threshold value of each flip-flop circuit becomes 2 ¹ , 2 ² , ..., 2 ^{n in} order with the lowest threshold value as the reference 2 ⁰ , and the capacitance of the capacitances C10, C11, C12, ..., C1 n is also based on C10. It is set that 2 ⁰ is 2 ¹ , 2 ² , ..., 2 ^{n in} order.

On the input side of each flip-flop circuit, a common analog input voltage X and inverted outputs Y'0, Y'1, Y'2,
, Y'n are capacitively coupled and connected via a weighted capacitance similar to the threshold value of the flip-flop circuit.

[0038] For example the capacity of the capacitance which is provided to the input side of the flip-flop circuit F0, based 2 ⁰ the volume of capacitance analog input voltage X is input, the inversion of the flip-flop circuit F1 with the threshold of one level The capacitance of the capacitance to which the output Y′1 is input is 2 ¹ , and the capacitance of the capacitance to which the inverted output Y′2 of the flip-flop circuit F2 is input is 2 ² , which has the threshold of n stages. The capacitance of the capacitance to which the inverted output Y'n of the flip-flop circuit Fn is input is 2 ⁿ
Has become.

The inverted output means (Vdd-Vout) when the non-inverted output is Vout and the reference voltage is Vdd. Therefore, when integrating the inverted outputs, it is necessary to remove Vdd that enters as an offset. Therefore, in the circuit of FIG. 10, -Vdd is applied to each input by the capacitance C below.
The effect of offset is eliminated by inputting through the capacitance with vdd. The capacity is i
This is the value for the th flip-flop circuit.

[0040]

[Equation 3]

By setting the threshold value and the capacitance as described above, the output of each flip-flop circuit is n with respect to the number n.
It has a meaning as each bit of bit binary data. The output of each flip-flop circuit according to the analog input voltage X is as shown in Table 1 below.

[0042]

[Table 3] X 0 1 2 3 4 5 6 7 8 9 ... Y0 0 1 0 1 1 0 1 0 1 1 0 1 ... Y1 0 0 1 1 1 0 0 0 1 1 0 0 ... Y2 0 0 0 0 0 1 1 1 1 1 0 ... Y3 0 0 0 0 0 0 0 0 0 1 1 ...

FIG. 11 shows a first modification of the third embodiment, in which the output of the flip-flop circuit is provided at a branch point between each flip-flop circuit and each weighting capacitance connected to the output side of the circuit. Capacitance C10, C11,
, C1n and switches SW0, SW1, SW2, ..., SWn that are selectively connected between the digital output section B and C12.

These switches are analog switches or digital switches which are simultaneously switched by the analog / digital selection output signal S1. When they are connected to the capacitance side, analog output is obtained and the digital output section B side is provided. When connected, n-bit digital data is output in parallel.

The output itself of the flip-flop is 0,
Since it is 1 digital output, if it is capacitively coupled through capacitances having different capacitances, it becomes multi-valued data of 2 ⁿ steps, and if it is branched and output in parallel before inputting to the capacitance, it is an n-bit digital output. It can also be used as data.

FIG. 12 is a block diagram showing a structure of a memory IC using the memory circuit shown in FIG. 11 as a basic element. A plurality of memory circuits M1, M2, Mn are provided in parallel, and the analog input voltage X is selectively input to and held in each memory circuit via the write addressing switches SW11, SW12, ..., SW1n. , SW2n for designating the read address are selectively output.

A digital signal similar to that of the conventional memory circuit is used for addressing, and the switch of the specified address is selected via the decoders D1 and D2 for writing and reading, respectively. The signal written and held is multi-valued information, but the output information can be taken out in either digital or multi-valued format according to the selection signal.

FIG. 13 shows the terminals of the circuit of FIG. On the input side, analog input terminal X, write address designation terminals WAd0 to WAd9, read address designation terminals RAd0 to RA
d9, an analog digital selection terminal S is provided,
On the output side, multi-level signal output terminals Um0 to Um3 and digital signal output terminals Ud0 to Ud15 are provided. Since the output time of a multi-valued signal may be longer than that of a digital signal, four output terminals are provided so that four addresses can be output at one time.

According to the configuration of the third embodiment, it is possible to provide a memory that holds multi-valued data with a circuit scale equivalent to SRAM.
If the scale of the memory circuit, which is the basic circuit, is increased, the precision of the held data can be improved in proportion to it, and if the precision of the required output data is low with respect to the circuit scale, If the high-order bit or the low-order bit equivalent is not used, the speed can be improved by that amount. Further, as a characteristic of SRAM, reading and writing can be executed simultaneously.

[0050]

As described above, according to the present invention, by providing a plurality of bistable circuits in parallel and connecting them via a capacitance, the analog voltage input to the common input terminal remains analog. It can be stored as multi-valued data.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a memory circuit according to a first embodiment.

FIG. 2 is a graph showing the input / output relationship of the memory circuit of the first embodiment.

FIG. 3 is a circuit diagram of a memory circuit showing a modified example of the first embodiment.

FIG. 4 is a circuit diagram showing a specific example of a bistable circuit according to the first embodiment.

FIG. 5 is a circuit diagram showing another specific example of the bistable circuit according to the first embodiment.

FIG. 6 is a circuit diagram showing a configuration of a memory circuit according to a second embodiment.

FIG. 7 is a graph showing characteristics of a plow-off inverter circuit.

FIG. 8 is a graph showing a setting example of three plucking inverter circuits.

FIG. 9 is a memory circuit circuit diagram showing a modification of the second embodiment.

FIG. 10 is a circuit diagram showing a memory circuit according to a third embodiment.

FIG. 11 is a circuit diagram of a memory circuit showing a modification of the third embodiment.

FIG. 12 is a block diagram of a memory using the memory circuit of Example 3 as a basic element.

13 is an explanatory diagram showing a configuration of terminals of the memory of FIG.

[Explanation of symbols]

 T1, T2, T3, Tn Bistable circuit C11, C12, C13, C1n capacitance

Claims (18)

[Claims] 1. A plurality of bistable circuits are provided in parallel so that the output voltage when the initial input voltage is removed is converged to either a low voltage or a high voltage depending on the magnitude relationship between the initial input voltage and the threshold voltage. A common analog voltage is connected to each of the bistable circuits so as to be input as the initial input voltage, and the threshold voltage of each bistable circuit is set stepwise so as to be relatively different from the initial input voltage, and A memory circuit, wherein a capacitance is connected to an output side of each of the bistable circuits, and the capacitances are connected to each other to form a common output terminal. 2. The value of the voltage of at least the converged voltage of each bistable circuit when inverted from the initial state is set to be different stepwise according to the relative relationship between the threshold voltage and the initial input voltage, The memory circuit according to claim 1, wherein the capacitances of the respective capacitances are set to be the same. 3. The convergence voltage of each bistable circuit is the same, and the capacitance of the capacitance is set to be weighted stepwise according to the relative relationship between the threshold voltage and the initial input voltage. The memory circuit according to claim 1, wherein: 4. The memory circuit according to claim 1, wherein the bistable circuit is a stacking inverter circuit configured by connecting the input and output of two inverters, respectively. 5. The bistable circuit includes first and second MOS field effect transistors each having a drain connected to a pull-up resistor and one drain connected to the other gate. The memory circuit according to claim 1, wherein a gate and a drain of the field effect transistor are used as an input and an output, respectively. 6. The bistable circuit has first and second MOS field effect transistors each having a source connected to a pull-down resistor and one source connected to the other gate. 2. The memory circuit according to claim 1, wherein the gate and the source of the effect transistor are input and output, respectively. 7. The memory circuit according to claim 1, wherein each bistable circuit is set such that a threshold voltage of each circuit itself is different stepwise. 8. The memory circuit according to claim 1, wherein each bistable circuit inverts an output only when a voltage corresponding to the analog input voltage becomes higher than a threshold voltage. 9. The memory circuit according to claim 3, wherein the bistable circuit is a flip-flop circuit. 10. The analog input voltage and the inverting outputs of all the bistable circuits with higher weighting are capacitively coupled via a capacitance having a capacitance corresponding to the weighting and input to each of the bistable circuits. At the output of the bistable circuit,
11. The memory circuit according to claim 10, wherein the number n has a meaning as each bit of n-bit binary data. 11. A plurality of bistable circuits are provided in parallel so that the output voltage when the initial input voltage is removed is converged to either a low voltage or a high voltage depending on the magnitude relationship between the initial input voltage and the threshold voltage. A common analog voltage is connected to each of the bistable circuits so as to be input as the initial input voltage, the convergence voltage of each of the bistable circuits is made common, and the threshold voltage is set to be different stepwise, and On the output side of each bistable circuit, a capacitance having a stepwise different capacitance according to the relative relationship between the threshold voltage and the initial input voltage is connected and weighted, and each capacitance is connected to form a common output terminal. A memory circuit characterized by the above. 12. The memory circuit according to claim 12, wherein the bistable circuit is a stacking inverter circuit configured by connecting the input and output of two inverters, respectively. 13. The bistable circuit includes first and second MOS field effect transistors each having a drain connected to a pull-up resistor and one drain connected to the other gate. 13. The memory circuit according to claim 12, wherein the gate and the drain of the field effect transistor are used as an input and an output, respectively. 14. The bistable circuit has first and second MOS field effect transistors each having a source connected to a pull-down resistor and one source connected to the other gate. The gate of the effect transistor,
13. The memory circuit according to claim 12, wherein the sources are input and output, respectively. 15. A plurality of plucking inverter circuits configured by connecting inputs and outputs of two inverters are provided in parallel, and the output of one inverter of each plucking inverter circuit is used as a common input terminal, and the other is provided. A memory circuit characterized in that the outputs of the inverters are connected to each other via a capacitance to form a common output terminal, and the thresholds of the respective inverter circuits are set to be different stepwise. 16. A flip-flop circuit having a plurality of stepwise different thresholds is provided in parallel, and a capacitance for weighting according to the step of the threshold is connected to the output side of each flip-flop circuit, and the plurality of capacitances are mutually connected. The analog input voltage common to the input side of each flip-flop circuit and the inverted output of the flip-flop circuit having a larger weight are weighted in the same manner as the threshold value of the flip-flop circuit while being connected and output. A memory circuit, which is capacitively coupled and connected via a capacitance of a capacitance, and the output of each flip-flop circuit has a meaning as each bit of n-bit binary data with respect to the number n thereof. 17. An output for providing a branch point between each flip-flop circuit and each weighting capacitance connected to the output side of the circuit, and outputting the output from each branch point in parallel as n-bit digital data. 18. The memory circuit according to claim 17, further comprising a section. 18. The switch according to claim 17, wherein the branch point is provided with a switch that selectively connects the output of the flip-flop circuit between the capacitance and the output section. Memory circuit.