JPS6010495A - Sense amplifier - Google Patents

Abstract

PURPOSE:To furnish a circuit suitable for multi-value level memory that can perform accurate operation even when input power varies remarkably and accordingly reference voltage becomes low by making a power source to a flip flop circuit off until just before starting sense operation. CONSTITUTION:Clocks CLKn, CLKp applied to switching circuits Q5, Q6 and Q11, Q12 are so designed that CLKn rises first and then CLKp falls. At first CLKn is L level, and CLKp is H level and a flip flop circuit FF does not operate. When a memory cell is read out and the output D is applied to a transistor Q7, CLKn rises, and Q6 becomes on and Q5 becomes off. However, as Q12 is in and Q11 is off, the current of passage Vcc, Q3, P1, Q8, ground and Vcc, Q4, P2, Q12, ground does not flow. Then, CLKp falls, Q11 becomes on, Q12 becomes off, and the voltage of a power source Vcc is applied to the flip flop circuit FF. One of transistors Q1, Q2 becomes on, and another becomes off.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a sense amplifier for multi-level reading, and more particularly to a CMOS sense amplifier for multi-level read-only memory.

Prior Art and Problems Most semiconductor memories store one bit of binary data "1" (IIQ) in their memory cells, but as a means to meet the demand for larger memory capacities, the degree of integration has been increased. In addition to increasing the number of memory cells, it is being considered to store multi-level data in the memory cells.The data to be stored in the memory cells is not binary, but 4-level, 8-level, etc.
・The memory capacity can be doubled, quadrupled, etc. From this point of view, the higher the number of multivalued levels, the better, but the larger the number of levels, the more difficult it is to distinguish. Therefore, the four-value type, which uses one bit of a memory cell as two binary bits, is attracting attention. For binary 2 bits, it is 11,10°01
．． There are four states of 00, which are stored as different voltage values as shown in FIG. That is, the power supply voltage Vcc is 5■
If this is the highest voltage and the lowest voltage is about 2■, divide this period into four equal parts and get state ■.

Assign to ■, ■, ■. These conditions are described in 11.1 above.
It corresponds to 0.01.00. To detect these states, three types of reference levels Ref 1, 2, and 3 are provided, and if it is higher than Ref 1, the state
If between, state ■, if between Ref3 and Ref2, state ■,
If Ref 3 or less, the status is ■.

For reading, use a sense amplifier of 5AI- as shown in Figure 3.
31 fixed installation of 3A3, these driver transistors Q
It knows which one of I and Q2 is on, and decodes it as a read output. For example, if the state is ■, the sense amplifier SA
1, the left transistor Q1 is on, the right transistor Q2 is off, and the sense amplifier SA2. In SA3, the right transistor Q2 is on and the left transistor Q1 is off, so the state of the sense amplifier SAI is set to 0 and the sense amplifier SA2. If the state of SA3 is set to 1, a state of 011 will be obtained, and this will be decoded to obtain a state (2). Similarly, the state (2) becomes 111, the state (2) becomes 001, and the state (2) becomes 000. From this, the states (2), (2), and (2) are known. Furthermore, it is logically synthesized to obtain two binary values and two bits. In Figure 3, MC is a memory, L is its load, D is the output of the memory cell, D is the reference input, and each sense amplifier SA1
~SA3 have the same configuration except for the reference input.

Writing, that is, storing data, in a multilevel memory is performed by changing the dimensions of a part of the data and changing the gm of the transistor. FIG. 3 also shows a gm selection type memory, where a memory cell MC is composed of a single transistor, and its gm is set to a value corresponding to stored data 1i, io, oi, oo. Therefore, this memory is a mask ROM
It is produced as. When such a transistor is connected in series with a load resistor and energized, there will be a voltage at the series connection point corresponding to the gm of the transistor, which is the read output. The readout output varies depending on the load conditions, but takes one of four levels from 5V to 2V, for example, as shown in FIG.

If the data to be stored in the memory cell is 1-bit binary data, only one reference level is required, and if the read output is higher than the reference level, it can be "1", if it is lower, it can be "0", etc. The read output of dynamic RAM or static RAM is "l" or "o" of the stored data.
However, in multi-level memory, as shown in Figure 2, the bias voltage voltage varies greatly from the power supply Vcc to a value close to the ground OV (more specifically, the bias voltage voltage varies from the power supply Vcc to a value close to the ground OV), as shown in Figure 2. There are various circuits that are suitable for sensing input voltages with high bias or low bias, but the sense amplifier must react accordingly. There are few circuits that are suitable for sensing input voltages that vary significantly up to the bias level.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a circuit suitable for a sense amplifier for a multi-level memory in which input levels vary widely.

Structure of the Invention The present invention is a sense amplifier for reading multilevel levels of a memory that stores data represented by a plurality of binary bits in a memory cell, which comprises a flip-flop circuit formed by cross-connecting input and output terminals of a pair of inverters; an input side buffer connected to one of the input/output terminals to receive a read voltage; a reference side buffer connected to the other input/output terminal to receive a reference voltage; and a first buffer connected to the ground side of the flip-flop circuit. a first switching circuit that connects the ground side to the ground when a clock is input; and a second switching circuit that is connected to the power supply side of the flip-flop circuit and follows the first clock;
The second switching circuit connects the power supply side to the power supply when the clock is inputted, and this will be described in detail below with reference to the drawings.

Embodiment of the Invention FIG. 1 shows a circuit initially considered by the inventors as a sense amplifier circuit for a multi-level memory consisting of five CMO circuits. 0
As is well known, the M03 circuit has advantages such as low power consumption. In FIG. 1, Ql, Q2 are driver transistors, Q3. Q4 is a load transistor, and input/output terminals PI and P2 of these transistors are cross-connected as shown in the figure to form a flip-flop circuit FF. Transistors with arrows are p-channel, and transistors without arrows are n-channel. Therefore, Ql and Q3, and Q2 and Q4 constitute a CMOS inverter. Q5. Q6 is also a p-channel transistor and constitutes a CMOS inverter, and clock C
When LK becomes H (high) level, transistor Q6 turns on, connects the earth side of flip-flop circuit FF to the ground, and activates the circuit. Input stage transistors Q7 and Q8. Q9 and QIO are buffers,
Ql and Q9 are drivers, and Q8 and QIO are loads, forming a source follower circuit. The readout is at the input end.
That is, to the gate of transistor Q7 and to the reference voltage Re.
f is applied to the input terminal inB, ie, the gate of transistor Q9. In this circuit, if Ref>D, transistor Q1 is on and Q2 is off; if Ref<]), transistor Q2 is on and Ql is off, and a sensing operation is performed. In the case of multi-value levels, three sets of such sense amplifiers are provided as shown in FIG. 3, and are commonly connected to the memory cell output ends to receive read outputs. In a conventional memory sense amplifier circuit in which one memory cell is a binary 1-bit type, the input/output terminals PL and P2 of the flip-flop circuit FF are directly connected to the memory cell output terminal, and the buffers Q7. QB etc. are not provided, but if you do this with a multi-level memory, when one of the three sense amplifiers operates, that sense amplifier will pull up the memory cell output terminal to the power supply or pull it down to the ground, causing the memory cell to fail. Data cannot be read. Buffer Q7
If Q8 is provided, this will not happen. Buffers Q9 and QIO on the reference level side are essentially unnecessary, but are effective for maintaining symmetry with the data input side and eliminating adverse effects on the reference power supply.

However, the circuit shown in FIG. 1 has the following problems.

That is, as described above, in a multi-level memory, the read output changes significantly from the power supply voltage to near the ground level, and the reference voltage Ref changes accordingly.

When the input voltage drops too much, the flip-flow knob circuit FF uses p-channel transistor Q3. Q4 may turn on, and if these transistors turn on, the voltage V
cc, transistor Q3, input/output terminal P1. There is a problem in that current flows in a path from the transistor Q8 to the ground, and from the power supply Vcc, I to the transistor Q4, the input/output terminal P2, the transistor QIO, and the ground, changing the input voltage and reference voltage applied to the flip-flop circuit. FIG. 4 shows a circuit according to an embodiment of the present invention which is also improved in this respect.

In FIG. 4, the same parts as in FIG. 1 are given the same reference numerals, and as is clear from the comparison with FIG. The difference is that 0MO3 consisting of 0MO3 is provided and this is switched by the clock CLKp. CMOS impark (switching circuit) on the ground side of flip-flop circuit FF Q5. CLK is the clock added to Q6.
As shown in FIG. 5, first the clock CLKn rises, and then the clock CLKp rises.
is selected so that it falls.

When such a switching circuit is added, initially the clock CLKn is at L level and the clock CLKp is at T level, but transistor Q5 is on, Q6 is off, transistor Q12 is on, and Qll is off. Flip-flop circuit FF is inactive. When the memory cell is read and its output is applied to transistor Q7, clock CLKn rises and transistor Q6
is on and Q5 is off. Hence the transistor.

1.Q2. The circuit consisting of Q6 becomes active and transistors Q1 or Q2 are turned on (low resistance) more than the other depending on whether the read voltage is high or low relative to the reference voltage Ref. However, the switching circuits Qll and Q12 on the power supply side
Since Ql2 is still on and Qll is off, the above-mentioned Vcc, Q3 . P 1゜Q8, ground and Vcc,
Q4. P2. Q12: No current flows through the ground path. When the clock CLKp eventually falls, the transistor Qll is turned on and the transistor Ql2 is turned off, and the voltage of the power supply VCC is applied to the flip-flop circuit FF. In the flip-flop circuit FF, as mentioned above, there is a difference in the conduction states of the transistors Ql and Q2 depending on the read voltage D and the reference voltage Ref. Q1.
For Q2, one is on and the other is off. Thus, in the circuit, the read voltage and the reference voltage Ref are low and the p-channel transistor Q3. Even if Q4 is in the ON state,
The power is cut off until just before the start of the sensing operation, so no current flows, and the read voltage and reference voltage applied to the flip-flop circuit are not changed by the current.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described in detail, the present invention provides a CM suitable for multi-level memory, which can perform accurate operation even if the input terminal changes significantly and therefore the reference voltage may become low.
An OS sense amplifier circuit is obtained.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an example of a CMOS sense amplifier, Fig. 2 is a graph showing changes in read voltage and reference voltage, Fig. 3 is a block diagram showing main parts of a multi-level memory sense circuit, Fig. 4 5 is a circuit diagram showing an embodiment of the present invention, and FIG. 5 is a diagram explaining the timing relationship of clocks. In the drawing, MC is a memory cell, Q3 and Ql, Q4 and Q2 are C
MOS Impark, FF is a flip-flop circuit, Pl
, P2 is the input/output terminal, Q? , QB is the input end buffer, Q9
．． QIO is a reference value buffer, Q5. Q6 is a first switching circuit, Qll. Q12 is the second switching circuit, CLKn, CLK
p is a clock. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 Figure 4

Claims (1)

[Claims] A sense amplifier for reading multiple levels of a memory that stores data represented by a plurality of binary bits in a memory cell, the sense amplifier comprising an inverter, a flip-flop circuit formed by cross-connecting a pair of input and output terminals, and the input and output terminals. an input side buffer connected to one of the input/output terminals to receive a read voltage; a reference side buffer connected to the other input/output terminal to receive a reference voltage; and a reference side buffer connected to the ground side of the flip-flop circuit to receive a first clock. a first switching circuit that connects the ground side to the ground; and a first switching circuit that is connected to the power supply side of the flip-flop circuit and connects the power supply side to the power supply when a second clock is input following the first clock; A sense amplifier comprising: a second switching circuit.