JPS5827917B2 - MIS memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MI in which memory contents are retained using a flip-flop constituted by a field effect transistor having a Mis (metal-insulator-semiconductor) structure.
S storage circuit, especially an integrated circuit that prevents write signals from being applied to the read circuit and separates digit lines and sense lines to achieve faster read operations, simpler read circuits, and faster write operations. The present invention relates to a MIS storage circuit that has been transformed into a MIS storage circuit.

The memory cells of the MIS memory circuit conventionally have a configuration as shown in FIG.

That is, the source of an MIS field effect transistor (hereinafter referred to as an MJS transistor) Q is connected, and the drain of the MIS transistor Q is connected to the drain of the MIS transistor Q1 and the source and gate of the MIS transistor Q3, respectively. The gate of transistor Q1 is connected to the drain MI of MIS transistor Q2.
The SI transistor is connected to the source and gate of the transistor Q, the source of the MIS transistor Q2 is connected, and the drains of the M and 1Sl transistors Q3 and Q4 are connected to the power supply terminal VDD to form a memory holding flip-flop. It is configured.

The gate MIS transistor Q5 is connected by its source and drain between the Tigit line and the drain of the transistor Q1, and the gate MIS transistor Qa is connected by its source and drain to the Tigit line and the drain of the MlS transistor Q2. A word line R/W is connected to each gate of these MISI transistors Q, , Q6.

These gate MIS transistors Q5 and Q5 are used as memory cell selection gates when writing and reading information.

Generally, there are two types of MIS transistors: enhancement type and depletion type. In this specification, the display shown in Figure a will represent the enhancement type, and the representation shown in Figure 2 will represent the depletion type.

In the circuit shown in Figure 1, when the enhancement type and depletion type coexist configuration suitable for the static type is used, M
Depression type IS transistors are used for IS transistors Q3 and Q4, and enhancement type transistors are used for the rest.

In the following explanation, all circuit power supplies, pulse polarities, etc. will be taken up in the case of an N-channel MIS.

Figure 2 shows W when writing information with logical values of '1'' and O''.
and signal waveforms at the R word line R/W, Tigid line and D when reading information.

As shown in the W, lt 191 part of this figure, now the first
To write information whose logical value is 1'' to the memory cell shown in the figure, apply a high voltage VH to the word line R/W and apply it to the gate MIS+-
Transistors Q5 and Q6 are brought into conduction, and the digit wire is brought to a high voltage VH and the digit incense stick is brought to a low voltage.

At this time, flip-flop 11 and MIS transistor Q
The potential at the connection point T2 of 2 drops to OV, and the memory retention M
IS transistor Q1 becomes non-conductive.

In this state, a current flows from the TID line, and the gate potential of the memory holding Nll5I transistor Q2 rises to become conductive.

Through this process, the logical value ((, lj) is written into the memory cell.

Here, since the memory retention MIS transistors Q3 and Q4 are set to high and low resistance in order to reduce the power consumption of memory cells, even if the word line R/W is in the OV state, the potential at the connection point T2 remains unchanged. Hahazo is retained in the OV.

To write information whose logical value is O'', use Wu Oll in Figure 2.
As shown in the section, change the polarity of the Tigit line and the hundred.
M, 1S for memory retention by reversing the writing of
Exactly the same operation can be performed with the l-transistor Q1 in a conductive state.

Further, when reading information, a high voltage VH is applied to the word line R/W as shown by a portion R in FIG. 2, and a high voltage VH is also maintained on the word line D.

Now, if we pay attention to digit incense sticks, M'1 for memory retention.
Sl- transistor Q2 is conductive and the logical value is ■''
In the state where the information is written, a current flows to the ground through the gate MIS transistor Q6 and the memory holding MIS transistor Q2, and the potential of the Tigit incense stick decreases to around 0.

On the other hand, when the memory retention M1S transistor Q2 is in a non-conducting state and information with a logical value of 'O' is written, the ground current does not flow, so the potential of the Tigit curb is maintained at a high voltage. hold.

Therefore, by determining the voltage change of this digit incense stick, it becomes possible to read out the information of the logical value, .

゛When reading this information, in order to prevent the memory information from being destroyed, the logical value ((o MI for memory retention
It is necessary to set the mutual conductance gm2 of the S transistor Q2 to several times the mutual conductance gmQ of the gate MiS transistor Q6.

Also, when reading information with a logical value of 1pp, the connection point T1 between the flip-flop 11 and the MIS transistor Q5
The gm+ of the memory holding MISI transistor Q1 is connected to the gate MIS transistor Q, so that the potential of the memory holding Mis transistor Q2 does not exceed the threshold voltage of the memory holding Mis transistor Q2.
It is necessary to set the value to several times gm5.

In such conventional circuits, a large amplitude signal during writing is also applied to the reading circuit, so the stray capacitance between the wiring causes the reading circuit to recover to its original state after writing.
This will require a considerable amount of time.

In order to shorten this time and achieve high-speed operation, the readout circuit must have an extremely complex configuration.

It is also necessary to guarantee the withstand voltage of the input terminal of the readout circuit.

Furthermore, since the mutual conductance of gate MIS transistors Q5 and Q6 is small, the connection point T or T
2, the charging and discharging time is quite long, which prevents high-speed writing.

If the mutual conductance of the gate MIS transistors Q and Q6 is increased, it is natural that the memory holding M and lS transistors Q1 and Q2 will be
It is also necessary to set the mutual conductance to a correspondingly large value.

Furthermore, since the conventional memory cell as a whole shown in FIG. Another drawback is that only one piece of information can be retrieved from one memory cell.

A first object of the present invention is to prevent the application of a write signal to the read circuit by separating the digit line and the sense line, and to simplify the read circuit and increase the speed of circuit operation.

The second purpose is to enable the mutual conductance of the gate MIS transistor to be set larger than before, and to prevent the destruction of memory contents during reading by setting one gate of the MIS transistor used to separate the digit line and the sense line. A read-only signal line is attached to the memory to speed up the write operation.

A third object of the present invention is to enable two types of information to be retrieved from one memory cell by providing two readout circuits.

For this purpose, readout circuits are connected to the terminals of the flip-flops from which mutually opposite information can be obtained, and the word lines for selecting memory cells are also connected to two readout circuits, an A word line and a B word line. Set up a book, these are A word line, B
The two reading circuits are selected and operated by a signal applied to the word line.

In order to select the A word line and the B word line, an address signal that selects two addresses, A address and B address, is used, and this selection operation selects information on the sense line of the same memory cell or a different memory cell. The configuration is such that either sense line information can be obtained.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The MIS storage circuit of the present invention will be described in detail below based on embodiments thereof with reference to the drawings.

FIG. 4 is a circuit diagram showing the configuration of the first embodiment of the MIS storage circuit of the present invention, and parts corresponding to those in FIG. 1 are given the same reference numerals.

In this embodiment, the first readout MiS transistor Q.

Its gate is connected to A word AWL, and its drain is connected to A sense line S.
A, and the source is the first coupling MIS transistor Q9.
are connected to the drains of each.

Similarly, the second readout M], S transistor Qs U)
Gate is connected to B word line BWL, drain is connected to B sense line S
B, and the source is the second coupling MIS transistor Q1.
are connected to the drains of o.

1st and 2nd coupling MIS) transistors Q9 and QI
The source of O is grounded and its gate is connected to the connection point T1. T2
are connected to each.

MIS transistor Q5. Each gate of Qa is connected to a write-only word line WE.

Furthermore, first and second memory holding MIS transistors Q1.
Q2, first and second gate MIS transistors Q,
, transconductance of Qa gml + gm2t
When K between gm5 j grn6 (7) and 12 m6 = 2 at the knee, conditions are set such that gml gm2 and 2 are approximately equal to 1 or larger.

With such a configuration, the digit line and the sense line can be separated, and two sense lines can be provided.

Furthermore, due to the above-mentioned mutual conductance condition, the present invention allows the writing speed to be improved several times as compared to the conventional method.

Further, by applying the read command signal from the A word line AWL and the B word line BWL, which are separate from the write-only line WE, it is possible to avoid destroying the stored contents during reading.

The lines WE, AWL (or BWL), 11), D, at the time of writing to the circuit shown in FIG.
The SA (or SB) signal is shown in FIG.

As can be understood from this figure, the operation during writing is the same as the conventional one shown in FIG.
The relationship between the signals applied to digit 1 and D is reversed.

It is now assumed that the first memory holding MISI transistor Q1 is in an emergency conduction state, the connection point T1 is at a high potential, and the first coupling MISI transistor Q is in a conduction state.

When a read command is applied to the A word line AWL in this state, the first read M1S transistor Q7 also becomes conductive.

If the A sense line SA and B sense line SB are held at high voltage in this state, the first read MIS
A current flows to the ground through the transistor Q7 and the I-th coupling M-IS transistor Q9, and the potential of the A sense line SA changes from a high voltage to OV.

In this way, information on the logical value II Oj) is read out.

On the other hand, it is assumed that the first memory holding MIS transistor Q□ is in a conductive state, the connection point T is at a low potential, and the first coupling MIS transistor Q is in a non-conductive state.

In this state, even if a read command is issued and the first read MIS transistor Q7 becomes conductive, no current flows from the A sense line SA to the ground, and the A sense line remains at a high voltage. .

In this way, the information of the logical value +t 1 pp is read out.

Similar read operations are also possible on the B sense line side.

In this way, if the circuit of the embodiment shown in FIG. 4 is used, the digit line and the sense line operate separately from each other, so the write signal does not have an adverse effect on the sense line, increasing the read speed and the operation. It is possible to simplify the process and speed up the write operation.

FIG. 6 is a circuit diagram showing the configuration of a second embodiment of the MIS storage circuit of the present invention, and FIG. 7 is a signal waveform diagram at each part of the circuit of the second embodiment. And parts corresponding to those in FIG. 5 are given the same reference numerals (the same applies to the following figures).

The circuit of this second embodiment connects the first and second combined MIS
The gate of transistor Q9 + QI O is connected to the first and second memory holding MI S transistors Q and Q2.
This circuit is different from the circuit of the first embodiment in that the circuit is connected to the gate of the first embodiment.

This second embodiment is essentially the same as the first embodiment shown in FIG.
The circuit is the same as that of the conventional circuit shown in FIG. Match.

In this case, when the first memory holding transistor Q1 is in a non-conducting state, the connection point T becomes a high potential, and the connection point T
2 is held at a low potential of OV.

Therefore, the first coupling MIS transistor Q9 also becomes non-conductive, and even if a read command is sent to the A word line AWL and the first read MISI transistor Q7 becomes conductive, the A sense line SA is connected to ground. no current flows,
The A sense line is held at a high potential.

In this way, the information of the logical value (l I jfi) is read out.

On the other hand, the first memory holding MISI-transistor Q.

In the conductive state, the connection point T1 has a low potential of Ov, and the connection point T2 has a high potential.

Therefore, the first coupling MISI transistor Q becomes conductive, and the read command is applied to the A word line AWL.
When the read MISI transistor Q7 becomes conductive, a current flows from the A sense line SA through the first read MIS transistor Q7 and the first coupling MIS transistor Q to ground, and the current flows from the A sense line SA to the ground. The potential of OV decreases from a high potential to a low potential of OV.

In this way, information of logical value "0"" is read out.

In that the read circuit and the write circuit are provided separately, the circuits of the first and second embodiments can be simplified as shown in FIG. In the embodiment, the logic value <(1 fit or O'' is determined by the conduction/non-conduction of the first and second coupling MISI transistors Q and QIO, and the first and second read MISI
Information of memory cells was selected by S transistors Q7 and Q8.

On the other hand, in FIG. 8, the first and second memory holding MIS transistors Q1. Q2
Also has the role of determining the information of the first and second coupling MISI-ranjisques Q9 and QlO, and records the sources of the first and second reading M], S transistors Q7 and Q8, and for pupil retention. It has a configuration in which it is connected to the drains of MIS transistors Q, , and Q2.

However, when the A word line AWL or the B word line BWL is selected and the information on the connection point T1 or T2 is read, the information on the connection point T1 or T2 becomes a logical value ((o jj) The potential of the connection point T1 or T2 should not exceed the threshold voltage of the MISI for memory retention, the transistor Q2 or Ql, and the mutual conductance gm1 or gm2 of the transistor Q1 or Q2 for the MISI for reading. - It is necessary to set the transconductance of transistor Q7 or Q8 several times grn7 or 2m8.

This increases the size of the memory cells themselves, and the load capacity increases proportionally, which results in impeding high-speed read operations.

Also, in the write operation, since the mutual conductance grl15 gm6 of the gate MISI transistor Q or Q6 is small and the load capacitance of the connection point T1 or T2 is large, it takes time to charge the connection point T1 or T2. However, it is not possible to speed up the write operation accordingly.

In order to increase this speed, it is necessary to increase the mutual conductance gm (5) of the gate MISI transistor Q5 or Q6, but this increases the load capacitance of the connection point T1 or T2 and also increases the This results in an increase in the load capacity of the circuit, and does not provide any essential improvement in speeding up.

Each of the embodiments described above is aimed at detecting the voltage of the □ sense line, but the third and fourth embodiments of the present invention shown in FIGS. 10 and 12 are aimed at detecting the current. That is.

These circuits are similar to the first circuit of the present invention shown in FIGS. 4 and 6.
The second embodiment has a configuration in which the sources of the first and second coupling MIS1S transistors and QIO of the second embodiment are connected to the power supply instead of being connected to the ground.

In these circuits, the information of memory cells is connected to the first and second MISI transistors Q for coupling.

and QIO conduction/non-conduction, and the 10th
In the circuit shown in the figure, when the first memory holding MIS1S transistor is in a non-conductive state, the potential at the position T1 becomes a high potential, and therefore the first coupling MIS1S transistor becomes in a conductive state.

At this time, when a read command is given to the A word line AWL,
The first read MIS1S transistor becomes conductive, and current flows from the power supply through Q7 and Q9 to the A sense line S.
Flows to A.

This state is defined as reading the information of the logical value ((171).

On the other hand, when the first memory holding M1S transistor Q1 is in a conductive state, the potential at the position T1 becomes a low potential of OV,
The first coupling Mis transistor Q9 is in a non-conductive state.

In this state, a read command is applied to the A word line AWL, and no current flows to the A sense line even if the first read MISI-LAN disk Q7 becomes conductive.

This state is defined as reading information with a logical value of On.

Embodiment No. 4 of the present invention shown in FIG. The configuration is such that it is connected to a MISlS transistor for use.

This circuit is essentially the same as the third embodiment shown in FIG. There is.

That is, when the first memory holding MIS1S transistor is in a conductive state, the position T1 is at a low potential of OV, the position T2 is at a high potential, and the first coupling MIS1S transistor is in a conductive state.

At this time, if a read command is sent to the A word line AWL, the first
When the read MIS1S transistor becomes conductive, current flows from the power supply through Q7 and Q9 to the A sense line S.
Flows to A.

This state is defined as reading information of logical values u and jj.

Conversely, when the first memory holding MIS transistor Q1 is non-conductive, the position T1 is at a high potential and the position T2 is at a low potential of OV, and the first coupling MIS transistor Q1 is non-conductive.

At this time, even if a read command enters the A word line AWL and the first read MIS1S transistor becomes conductive, no current flows to the A sense line SA.

This state is defined as reading information of logical value (1o jj).

In this embodiment, the sense line is set close to the ground potential, making it possible to solve the conventional condition that the input terminal of the readout circuit must have a sufficient withstand voltage.

Therefore, the circuit design becomes easier, and since the sense line and digit line operate separately, the write signal does not have an adverse effect on the sense line, increasing the read speed, simplifying the read circuit, and increasing the speed of the write operation. becomes possible.

Furthermore, although the above embodiments have been described using N channels M and S, it is also possible to use a P channel MIS by reversing the polarity of the pulses, etc.

It is also possible to use only enhancement type transistors.

Also, read transistor Q7. One of Qs can also be omitted.

As explained in detail above, the MIS memory circuit of the present invention can speed up read and write operations, and can store two types of information by disposing two sense lines in one memory cell. Since it can be read out, excellent effects can be achieved by applying it to electronic circuit devices operating at high speed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the configuration of a conventionally used MIS storage circuit, Fig. 2 is a signal waveform diagram of each part of the circuit shown in Fig. 1, and Fig. 3 is a diagram showing enhancement type and depletion type displays. , 4th, 6th, 10th and 12th are the 1st and 12th figures of the present invention. Second. 3. Circuit diagram showing the configuration of the fourth embodiment; 5. 7゜Figures 11 and 13 are signal waveform diagrams of each part of the circuit of the corresponding embodiment, Figure 8 is a circuit diagram showing a comparative example, and Figure 9 is a signal waveform of each part of the comparative example of Figure 8. It is a diagram. VDD...Power supply, R/W...Word line, D...First digit line, 100...
Second digit line, WE...Write line, AW
L...A word line, BWL...B word line, SA...A sense line, SB...°°. B sense line.

Claims (1)

[Scope of Claims] 1. First and second memory holding M, IS transistors whose drains are connected to one end of a power supply;
The respective drains are connected to the gates and sources of the memory holding MIS1S transistors, the gates are connected to the gates and sources of the second and first memory holding MIS1S transistors, and the respective sources are connected to the power supply and other sources. 3rd and 4th memory holding MISlS connected to the end
a memory holding flip-flop transistor, a first coupling MlS transistor whose gate is connected to the drains of the third and fourth memory holding MISlS transistors, and the third and fourth memory holding MISlS transistors;
a second coupling MISlS transistor whose gate is connected to the drain of the transistor; first and second word lines are respectively connected to each gate and each source is connected to the first and second coupling MISlS transistor drains; first and second readout MISI-transistors;
The gate is connected to the write line, one of the source and drain is connected to the first and second digit lines, and the other of the source and drain is connected to the third and fourth memory holding MI.
first and second gate MIS transistors connected to the SlS transistor transistors respectively; The first and second sense lines are connected to each other, and mutual conductances gm1, gm2, gm5 of the fourth and third memory holding MISt-transistors and the first and second reading MISt-transistors. An MIS storage circuit characterized in that gm, gm2 are set to 1 and 2 are set to values larger than 1 or close to 1 as -"" k t and "" k2 between gm5 gmQ gm6.