JPH07234798A - Information processor provided with detecting function for address fault - Google Patents

Abstract

PURPOSE:To surely detect the fault of an address even when the fault of the address outputted from a bus utilizing device is a change of bit value from '0' to '1' or vice versa ranging over plural bits. CONSTITUTION:When CPU writes the address of a transfer destination to an address register of a bus master on a system bus. CPU detects the address on an address bus 181 specifying the address register by a decoder 24 and outputs a write signal to a register 231 in a register control circuit 23 corresponding to the bus master provided with the address register so as to write the address of the transfer destination being write-in data on a data bus 182 to the pertient register 231 as well. At the time of data transfer by the bus master in accordance with the address written into the address register, a comparator 25 compares the address on the address bus 181 from the pertient bus master and the contents of the register 231 in the corresponding register control circuit 23 and in the case when they are not coincident, an error signal 171 is outputted from a gate 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus equipped with a bus utilization device, and more particularly to an address fault detection function for detecting a fault of an address on the bus output from the bus utilization device for memory access or the like. The present invention relates to an information processing device having.

[0002]

2. Description of the Related Art Generally, a bus utilization device that acquires a bus and then outputs an address on the bus to access a memory or the like is called a bus master (bus master device). FIG. 4 shows a schematic configuration of a general information processing apparatus having such a bus master device. A system bus 41 is connected to a disk interface 42 as a bus master, for example. A disk device 43 is connected to the disk interface 42. The system bus 41 also has a disk interface 42.
Various I / O (input / output device) devices 44 similar to the above are connected. The system bus 41 is further provided with a CPU 45 and a memory controller 46 which are control centers of the system.
However, the bus control circuit 47, (similar to the system bus 41)
It is connected via an internal bus 48. The memory controller 46 is connected to a main memory 49 that stores various programs and data. The system bus 41 is
An address bus 411, a data bus 412 and a control bus 413 are provided, and an internal bus 48 is an address bus 481, a data bus 482 and a control bus 4.
It consists of 83.

In such an information processing apparatus, the operation of transferring the data of the disk device 43 to the main memory 49 is as follows. First, the CPU 45 writes a disk read command to the disk interface 42. Further, the CPU 45 writes a DMA transfer command (data transfer command) to the DMA device 421 in the disk interface 42. This DM
The A transfer command has a start address of a transfer destination on the main memory 49, a transfer length, and a transfer direction, and each specifies an address (I / O address) of a corresponding register (not shown) in the DMA device 421. As a result, the command is written.

The disk device 43 outputs data according to the command written in the disk interface 42. The DMA device 421 receives the data from the designated area of the disk device 43 and outputs it to the data bus 412 of the system bus 41 according to the command written in the DMA device 121, and (on the main memory 49).
The address is output to the address bus 411.

Data and addresses output from the DMA device 421 to the data bus 412 of the system bus 41 and the address bus 411 are sent to the memory controller 46 via the bus control circuit 47, the data bus 472 of the internal bus 48, and the address bus 471. Be guided. As a result, the memory controller 46 (according to the address on the address bus 481 (output from the DMA device 42)) (the DMA device 4)
The data on the data bus 482 (output from 2) is written to the main memory 49.

In this way, the DMA device 421 sequentially writes (transfers) data to the main memory 49 from the transfer destination address set (by the CPU 45).

[0007]

In the above-mentioned conventional information processing apparatus, the system bus 41 (the address bus 41 of the system bus 41) is used.
1) When an address failure occurs, such as C
There is a problem that a fatal failure is caused, such as destroying a memory area (program area) on the main memory 49 in which the program of the PU 45 is stored.

Therefore, a method of adding a parity to an address bus in order to detect an address failure on the bus has been conventionally known. However, the address failure detection method based on parity cannot be reliably detected for a failure of an address line extending over a plurality of bits, such as an address failure caused by a failure of an address driver. It was insufficient.

The present invention has been made in consideration of the above circumstances, and an object thereof is to retain a copy of an address indicating an access destination to a memory or the like set in a bus utilization device by a data transfer instructing means and retain it. By arranging to check the address on the bus output from the bus utilization device based on the contents, the garbled address of a plurality of bits due to some cause (address bit value "0" to "1" or " An object of the present invention is to provide an information processing device that can reliably detect the address failure even when a change from 1 "to" 0 "occurs.

Another object of the present invention is to provide an information processing apparatus capable of easily registering a reference address necessary for detecting an address failure. Yet another object of the present invention is to prevent an information failure from accessing a memory or the like in accordance with an erroneous address and destroying the contents of a memory area other than the original transfer destination even if an address failure occurs. To provide.

[0011]

SUMMARY OF THE INVENTION According to the present invention, the use of each bus for holding the same address as the address set in the first address holding means of each bus using device connected to the bus. Second provided corresponding to the device
Comparing the address output on the bus from the bus using device at the time of data transfer by the bus using device with the address held in the second address holding device corresponding to the bus using device, It is characterized by comprising a comparing means for detecting whether or not the address on the bus is correct depending on whether or not the two addresses match.

In the above configuration, since the same address as the address set in the first address holding means of the bus using device is held in the second address holding means, the first address holding of the bus using device is held. According to the address set in the means, when the memory or the like is accessed by the address output from the bus utilization device on the bus, with reference to the content held in the second address holding means corresponding to the bus utilization device, By comparing with the address on the bus by the comparing means and checking whether there is a match, it is possible to reliably detect whether or not the address on the bus output from the bus using device is normal.

Further, by adding the following address setting detecting means to the above structure, that is, detecting the address setting to the first address holding means in the bus using device by the data transfer instructing means and using the bus. By adding address setting detection means for outputting a write signal for writing the address set in the first address holding means via the bus by the data transfer instructing means to the second holding means corresponding to the device, It is possible to set the same address in the corresponding second holding means at the same time as setting the address in the first address holding means of the bus utilization device.

The address setting detecting means decodes an address on the bus which designates the first address holding means when the address is set from the data transfer instructing means to the first address holding means of the bus utilization device, and the address is detected. Decoding means for outputting a write signal for writing an address indicating an access destination, which is write data on the bus, to the second address holding means corresponding to the bus using device having the first address holding means specified by the address Can be realized by

However, in order for the above address setting detecting means (decoding means) to be applicable, the addresses assigned to the respective first address holding means of the respective bus utilization devices must be fixed in the system.

Therefore, the present invention relates to the first of the bus utilization devices.
In order to be applicable when the address assigned to the address holding means is not fixed in the system, the same address as the address set in the first address holding means of each bus utilization device connected to the bus is used. A second address holding means provided to correspond to each bus using device and an address designating a first address holding means of each bus using device are provided in each bus using device. The third address holding means provided correspondingly, the address output on the bus from the bus using device at the time of data transfer by the bus using device, and the second address holding means corresponding to the bus using device. And a first comparing means for detecting whether or not the address on the bus is correct by comparing the existing address with each other and determining whether the two addresses match. The address designating the first address holding means output to the bus for setting the address to the first address holding means in the bus utilization device by the data transfer instructing means is the address of each of the third address holding means. A second address holding means, which is write data on the bus, is written to the second address holding means corresponding to the third address holding means having the held content matching this address. Corresponding to the second comparing means for outputting the second write signal, the address designating the third address holding means, and the third address holding means as the data to be written in the third address holding means. Address setting for outputting the address designating the first address holding means of the bus using device to the bus, together with the third write signal, on the bus Stage, and in response to the third write signal from the address setting means, the address designating the third address holding means on the bus is decoded, and the third address holding means designated by the address decodes the bus It is also characterized in that it is provided with a decoding means for outputting a fourth write signal for writing an address designating the third address holding means, which is the above write data.

In the above configuration, for example, when the system is started up, an address for setting an address to be assigned to the first address holding means of the bus using device in the third address holding device corresponding to each bus using device. The setting operation is performed as follows. That is, the bus using device corresponding to the third address holding means as the address designating the third address holding means on the bus from the address setting means and the data to be written in the third address holding means. The address designating the first address holding means is output together with the third write signal.

The decoding means decodes the address on the bus (the address designating the second address holding means) output from the address setting means in response to the third write signal, and is designated by this address. The fourth write signal is output to the third address holding means. As a result, the write data on the bus output from the address setting means (the address designating the third address holding means) is registered in the second address holding means.

The address setting means repeats the above address setting operation for the third address holding means corresponding to each bus utilization device on the bus. When this address setting operation is performed, it is possible to set the same address in the corresponding second holding means at the same time as setting the address in the first address holding means in the bus utilization device by the data transfer instruction means. Become. That is, when the address is set in the first address holding means in the bus utilization device by the data transfer instructing means, the address on the bus output from the data transfer instructing means (the address designating the first address holding means) is , The second comparing means compares the contents held in the respective third address holding means with each other, and the second address holding means corresponding to the third address holding means having the held contents matching this address is transferred to the second address holding means. 2 write signals are output. As a result, the write data on the bus output from the data transfer instructing means (the address indicating the access destination set in the first address holding means of the corresponding bus utilization device) is written in the second address holding means. Be done.

As described above, when data transfer is performed by this bus utilization device according to the address set in the first address holding means of this bus utilization device, the address output from this bus utilization device is By comparing the contents of the second address holding means corresponding to the bus utilization device with the first comparing means, the presence / absence of an address fault is surely detected.

Further, according to the present invention, when it is detected that the address on the bus is not correct, the access control means for forcibly canceling the access from the bus utilization device as an error is provided, so that the memory according to the incorrect address is provided. It is also characterized in that the contents of the memory area which is not the original transfer destination is prevented from being destroyed by being accessed.

Further, according to the present invention, the bus utilization device updates the address with the address set in the first address register holding means of the bus utilization device as the start address of the DMA transfer, and at the same time, transfers the data of the designated transfer length. At the time of the DMA transfer in which the transfer is divided into a plurality of times, the address held in the second address holding means corresponding to the bus utilization device is changed for each transfer or each transfer in which the transfer address is detected to be correct. By providing the updating means for updating by the transfer size, it is possible to detect the failure of the address output from the bus utilization device during the DMA transfer, based on the content of the corresponding second address holding means. It is also characterized by what was done.

[0023]

1 is a block diagram showing the overall configuration of an information processing apparatus according to an embodiment of the present invention. In FIG. 1, 1
1 is a system bus. The system bus 11 comprises an address bus 111, a data bus 112 and a control bus 113.

A disk interface 12 as a bus master is connected to the system bus 11. The disk interface 12 transfers data (DM) between a main memory 15 and a disk device 13 described later.
It has a DMA device 121 that performs A transfer). A disk device 13 is connected to the disk interface 12.

The system bus 11 also has various I / O as a bus master similar to the disk interface 12.
The O device 14 is connected. The system bus 11 is further connected to a CPU 15 and a memory controller 16 which are control centers of the system, via a bus control circuit 17 and an internal bus 18 (similar to the system bus 11).

The memory controller 16 serves as an interface between the system bus 11 and a main memory 19 which will be described later, and does not destroy the memory area of the main memory 19 when an error signal 171 is received from the bus control circuit 17. The access to the main memory 19 is stopped.

The bus control circuit 17 receives a bus use request from the CPU 15 and a bus use request from the system bus 11 (a bus master such as the disk interface 12 connected to the system bus 11), and grants a bus use permission to one of them. It is designed to give. The bus control circuit 17 has an address failure detection function (which is different from the bus control circuit 47 in FIG. 4) for detecting the occurrence of an address failure (address error). An error signal 171 is output to the memory controller 16 when an address failure is detected.

The internal bus 18 is composed of an address bus 181, a data bus 182 and a control bus 183, like the system bus 11. Memory controller 16
A main memory 19 for storing various programs and data is connected to the.

FIG. 2 is a block diagram showing a detailed structure of the bus control circuit 17. First, the bus control circuit 17 is shown in FIG.
The bus request signal 11 included in the control bus 113 in the system bus 11 in addition to being connected to the address bus 111 and the data bus 112 in the system bus 11 shown in FIG.
4 group, bus use permission signal 115 group and command 1
It is also connected to 16.

Each bus request signal 114 corresponds to the system bus 1
This signal is connected to each of the bus masters (such as the disk interface 12) on 1 in a one-to-one relationship, and indicates that the corresponding bus master requests the use of the system bus 11. Each bus use permission signal 115
Is a signal which is connected to each bus master on the system bus 11 in a one-to-one manner and which gives a corresponding bus master permission to use the system bus 11. The command 116 is output from the bus master that has acquired the system bus 11 at the time of data transfer or the like.

Bus control circuit 17 also includes address bus 181 and data bus 18 in internal bus 18 shown in FIG.
In addition to being connected to 2, the write signal 184 included in the control bus 183 in the internal bus 18 is also connected. The write signal 184 is a signal for writing a command or the like from the CPU 15 to a bus master (internal register or the like) on the system bus 11.

The bus control circuit 17 comprises a control unit 20, an address bidirectional bus driver 21, a data bidirectional bus driver 22, a register control circuit 23, a decoder 24, a comparator 25 and a gate 26.

The control unit 20 receives a bus request signal 114 from each bus master on the system bus 11, performs a bus arbitration, and returns a bus use permission signal 115 to a request source having the highest priority. To have. The control unit 20 also receives the command 1 from the bus master that has acquired the bus use right.
16 has a function of outputting control signals 201 and 202 for controlling the opening of the bidirectional bus drivers 21 and 22 in accordance with 16. The control unit 20 further, when the bus master on the system bus 11 is using the bus 11, the bus master recognition signal 203 indicating the bus master that is using the bus.
And a transfer byte number signal 204 indicating the number of transfer bytes of the data transfer (DMA transfer) performed by the bus master,
The bus master has a function of outputting an access signal 205 indicating that the main memory 19 shown in FIG. 1 is being accessed.

The bidirectional bus driver 21 is controlled by the control signal 201 from the control unit 20 and inputs / outputs an address between the address buses 111 and 181. The bidirectional bus driver 22 is controlled by the control signal 202 from the control unit 20, and the data buses 112 and 182 are controlled.
Input and output data between.

The register control circuit 23 uses the system bus 1
1 to 1 for each maximum number of bus masters that can be connected
Corresponding register 231 (second address holding means)
Have a group of. Each register 231 has a data bus 182.
The above data (here, the transfer destination address) is used by the decoder 2
It is used to hold according to the write signal 241 output from No. 4. When the bus master on the system bus 11 is operating, the register control circuit 23 outputs the contents of the register 231 corresponding to the bus master indicated by the bus master recognition signal 203 as comparison address data 232 used for comparison in the comparator 25. Have the function to
The register control circuit 23 also updates (for example, increments) the content of the corresponding register 231 by the number corresponding to the transfer byte number indicated by the transfer byte number signal 204 when a match is detected by the comparison by the comparator 25. It has become.

The decoder 24 decodes the address on the address bus 181 in response to the write signal 184 from the CPU 15, and sends it to the register 231 corresponding to the address register (first address holding means) in the bus master designated by the address. The write signal 241 is generated.

The comparator 25 is for comparing the address on the address bus 181 output from the bus master with the comparison address data 232. This comparator 25
Is configured to output a valid non-match signal 251 when the above two addresses do not match.

The gate 26 is, for example, an AND circuit which outputs the non-coincidence signal 251 from the comparator 25 as it is while the access signal 205 from the control unit 20 is valid (active). The output of the gate 26 is the error signal 17
Used as 1.

Next, the operation of the embodiment of the present invention will be described by taking the DMA transfer from the disk device 43 to the main memory 49 as an example. When the DMA transfer from the disk device 13 to the main memory 19 is required, the CPU 15 writes a disk read command to the disk interface 12 as described below.

The CPU 15 first acquires the right to use the system bus 11. For the acquisition of this bus usage right, DM
The case of the A device 121 will be described later as an example. Next CPU15
To the disk interface 12 to the internal bus 1
8. The disk read command (data thereof) is sent via the bus control circuit 17 and the system bus 11 together with the address (I / O address) designating the write destination of the command and the write signal 184.

Then, in the disk interface 12, the disk read command sent from the CPU 15 is written to, for example, a register (not shown) designated by the address (I / O address) from the CPU 15 in response to the write signal 184. Be done.

Next, the CPU 15 writes a DMA transfer command to the DMA device 121 in the disk interface 12 as described below. That is, CPU1
5 is a transfer destination on the main memory 19 to the DMA device 121 via the internal bus 18, the bus control circuit 17 and the system bus 11 (transfer when data in the main memory 49 is transferred to the disk device 43). For each DMA transfer command that specifies the start address of the original), the transfer length, and the transfer direction, the address (I
/ O address) and the write signal 184. Here, the DMA transfer command is transmitted via the data bus 182 of the internal bus 18, the bus control circuit 17 and the data bus 112 of the system bus 11, and the write destination designation address is the address bus 181, the bus control circuit 17 and the system bus of the internal bus 18. 11 via the address bus 111.

In the DMA device 121, the DMA transfer command sent from the CPU 15 is written in the register designated by the address from the CPU 15 in response to the write signal 184. That is, the command designating the transfer destination address is written in an address register (first address holding means) (not shown) in the DMA device 121, and the command designating the transfer length (transfer size) is transferred in the DMA device 121. The command written in a register (not shown) and designating the transfer direction is written in the transfer direction register (not shown) in the DMA device 121.

The decoder 24 in the bus control circuit 17 has a C
The address on the address bus 181 is decoded according to the write signal 184 from the PU 15. If the address indicates an address register in the bus master connected to the system bus 11, the decoder 24 registers the register control circuit 2 corresponding to the bus master.
The write signal 241 to the internal register 231 is output.
Then, the data on the data bus 182 is written in the register 231 according to the write signal 241 from the decoder 24.

Therefore, the CPU 15 to DM
DM that specifies the start address of the transfer destination to the A device 121
At the time of writing the A transfer command, the DMA device 12
The start address of the same transfer destination as that written in the address register in 1 is written in the corresponding register 231 in the register control circuit 23.

When the above-mentioned series of DMA transfer commands are written from the CPU 15, the DMA device 121 acquires a valid system bus request signal 114 unique to itself in order to acquire the system bus 11 used for data transfer according to the commands.
Is output to the bus control circuit 17.

The control unit 20 in the bus control circuit 17 arbitrates the right to use the system bus 11 in response to the bus request signal 114 from each bus master. The control unit 20 sends the valid bus request signal 11 from the DMA device 121 as described above.
When 4 is output, the system bus 11 is empty,
If the valid bus request signal 114 is not output from the bus master having a higher priority than the DMA device 121, the DMA device 121 (with the disk having the right to use the system bus 11 is given to the DMA device 121. Bus use permission signal 11 specific to interface 12)
5 is output. At the same time, the control unit 20 controls the DMA device 1
The bus master recognition signal 203 indicating 21 is output to the register control circuit 23 to notify that the operation of the DMA device 121 has started.

When the DMA device 121 receives the bus use permission signal 115 from the control unit 20 in the bus control circuit 17, it is determined that the right to use the system bus 11 has been acquired, and the DMA transfer command written by the CPU 15 is designated. Data transfer (data transfer from the disk device 13 to the main memory 19) is started. That is, the DMA device 12
First, the first output of the transfer destination written in the address register in the DMA device 121 is output to the address bus 111 of the system bus 11 and the data from the disk device 13 is output to the data bus 112 of the system bus 11. At the same time, the command 116 instructing the write access to the main memory 19 is output to the control unit 20 in the bus control circuit 17. This command 116 includes the number of transfer bytes.

Upon receipt of this command 116, the control unit 20 controls the switching of the bidirectional bus drivers 21 and 22 by the control signals 201 and 202 to internally set the address on the address bus 111 output from the DMA device 121. DMA to the address bus 181 of the bus 18
The data on the device 121 is transferred to the data bus 18 of the internal bus 18.
Lead to 2, respectively.

Further, the control section 20 outputs a valid access signal 205 to the gate 26 in response to the command 116 from the DMA device 121 and registers the transfer byte number signal 204 indicating the transfer byte number designated by the command 116. Output to the control circuit 23.

The register control circuit 23, in response to the bus master recognition signal 203 from the control unit 20, outputs the signal 203.
The register 231 corresponding to the bus master indicated by is selected. Then, the register control circuit 23 uses the address held in the selected register 231 (here, the start address of the transfer destination written in the register 231 when the DMA transfer command is written to the DMA device 121 by the CPU 15 described above). ) Is the comparison address data 2
Output as 32.

This comparison address data 232 is guided to the comparator 25. The comparator 25 has an address on the address bus 181 of the internal bus 18, that is, the DMA device 12
The transfer destination address sent from 1 to the address bus 181 of the system bus 11 and the bidirectional bus driver 21 is also introduced. The comparator 25 compares these two addresses.

If there is no failure in the address bus 111 or the address bus 181, and no garbled address is generated, the above two addresses should match. In this case, the comparator 25 leaves the mismatch signal 251 false (indicating address match).

On the other hand, a failure occurs in the address bus 111, the address bus 181, or the like due to some cause,
If the addresses are garbled, the two addresses do not match. In this case, the comparator 25 outputs the mismatch signal 25.
Make 1 true. This non-coincidence signal 251 has no meaning unless the main memory 19 is being accessed.
It is gated by the gate 26 in response to the access signal 205 from the control unit 20. Here, the access signal 20
Since 5 is valid, the mismatch signal 251 is directly output to the memory controller 16 as the error signal 171 through the gate 26. This error signal 171 is the disagreement signal 25 when the access signal 205 is valid.
If 1 indicates an address mismatch (in the true state), it is true, indicating that the address for accessing the main memory 19 is incorrect.

If the error signal 171 from the bus control circuit 17 (inside the gate 26) is false, the memory controller 16 causes an area in the main memory 19 designated by the address sent via the address bus 181 to Data bus 1
Access control for writing data sent via 82 is performed.

On the other hand, when an address error is detected in which the error signal 171 from the bus control circuit 17 (inside the gate 26) is true, the memory controller 16 does not destroy the memory area of the main memory 19. Main memory 1
Stop access to 9.

As described above, in this embodiment, the system bus 1
When there is a memory access from the bus master connected to 1, the address output on the address bus 111 and led to the address bus 181 for the access is the register in the register control circuit 23 corresponding to the bus master. By checking with the comparator 25 whether or not it matches the address (comparison address data 232) held in 231, whether or not the address is correct is detected.

Further, in this embodiment, the address bus 181
When it is detected that the above address is not correct, the bus control circuit 17 (internal gate 26) outputs an error signal 171 to the memory controller 16 so that the memory access at that time is aborted as an error. I have to. As a result, it is possible to prevent the data in the area from being destroyed by the write access to the area in the main memory 19 designated by an incorrect address.

Now, when the access cycle of the main memory 19 is completed, the control unit 20 once sets the access signal 205 to the false state. At this time, if the error signal 171 from the gate 26 is not true, that is, if the write access to the main memory 19 is normally performed without an address error, the register control circuit 23 sends the bus master signal from the control unit 20. The contents of the register 231 designated by the recognition signal 203 are
Update by the number according to the transfer byte number indicated by the transfer byte number signal 204 from the control unit 20 (increment here)
To do. As a result, the DMA device 121 outputs the transfer destination address to the address bus 111 of the system bus 11 and the subsequent transfer data from the disk device 13 to the data bus 112 of the system bus 11 for the subsequent DMA transfer. In this case, the transfer destination address is compared by the comparator 25 with the contents of the updated register 231 as the comparison address data 232, and the address error is correctly detected.

On the other hand, the error signal 171 from the gate 26
Is true and the access to the main memory 19 is stopped, the contents of the register 231 designated by the bus master recognition signal 203 are not updated. In this case, by checking the contents of the register 231, it is possible to know at which transfer destination address the failure has occurred. However,
If this is not necessary, the contents of the register 231 designated by the bus master recognition signal 203 may be unconditionally updated.

The above is from the disk device 13 to the main memory 19
The case of the DMA transfer to the main memory 1 has been described.
The same applies to the case of DMA transfer from 9 to the disk device 13. However, in this case, there is no possibility that the contents of the corresponding area of the main memory 19 will be destroyed even if a failure occurs in the transfer address, and therefore the access to the main memory 49 does not necessarily have to be stopped.

The same applies to the case of data transfer between another I / O device 14 and the disk device 13, and also to the case where this data transfer is completed once. In the above embodiment, the address (I / O address) of the address register in the bus master connected to the system bus 11 needs to be fixed. If it is not fixed, it is necessary to configure the decoder 24 with a rewritable programmable logic and change the decoding function according to the system configuration.

When the decoder 24 whose decoding function cannot be changed is used, the start address of the transfer destination is written to the address register of the bus master (that is, separately from the writing of the DMA transfer command), and the bus master is not. By designating the address (I / O address) of the register 231 in the register control circuit 23 corresponding to, the CPU 15 may write the start address of the transfer destination in the register 231. However, the decoder 2
No. 4 needs to be configured not to decode the address assigned to the address register of the bus master, but to decode the address assigned to the register 231 in the register control circuit 23 corresponding to the bus master.

As described above, in order to apply the decoder 24, whose decoding function cannot be changed, to the system (the bus control circuit 17) in which the address of the address register in the bus master is not fixed, the CPU 15 DMAs the bus master. Each time a transfer command is written, the register 2 in the register control circuit 23 corresponding to the bus master
The address of 31 must be specified and the same address must be written in the register 231, which increases the load on the CPU 15.

Therefore, a configuration replacing the decoder 24 in FIG. 2 will be described with reference to FIG. The same parts as those in FIG. 2 are designated by the same reference numerals. 3 is the CP of FIG.
When writing the start address of the transfer destination from the U15 to the address register of the bus master on the system bus 11, a transfer address writing circuit 30 for automatically writing the address to the register 231 in the register control circuit 23 corresponding to the bus master. It is a block diagram which shows a structure.

The transfer address writing circuit 30 is used in place of the decoder 24 in FIG. 2, and has an I / O address registration / comparison circuit 31 that corresponds to each register 231 in the register control circuit 23 on a one-to-one basis. , And a decoder 32.

The I / O address registration / comparison circuit 31 sets and registers the data (in this case, I / O address) on the data bus 182 in response to the corresponding write signal 321 from the decoder 32, And a comparator 312. This comparator 312 has a register 31
The content of 1 is compared with the address on the address bus 181, and a match signal 313 is output when a match is detected. The I / O address registration / comparison circuit 31 further has a gate 314. This gate 314 is connected to the comparator 31.
During the period when the match signal 313 from 2 is valid, the CPU
The write signal 184 from the corresponding register control circuit 23 (to the relevant I / O address registration / comparison circuit 31)
It is, for example, an AND circuit which outputs the write signal 301 to the inner register 231.

The decoder 32 operates in the I / O address registration mode for registering the I / O address assigned to the address register of the bus master in the register 311 in the corresponding I / O address registration / comparison circuit 31.
Address bus 181 according to the write signal 302 from 5
The upper address (here, the I / O address designating the register 311) is decoded, and the register 311 is decoded.
To generate a write signal 321 to

Next, the operation of the transfer address writing circuit 30 shown in FIG. 3 will be described. In the initial state of the system, the CPU 15 sets and registers the I / O address assigned to the address register of each bus master on the system bus 11 in the register 311 in the I / O address registration / comparison circuit 31 corresponding to the bus master. Then, the following operation is performed.

That is, the CPU 15 assigns an address (I / O address) designating the register 311 in the I / O address registration / comparison circuit 31 corresponding to the target bus master.
An address set in the register 311 on the address bus 181 of the internal bus 18 (specifically, an I / O address assigned to the address register of the corresponding bus master).
Are sent to the data bus 182 of the internal bus 18 and a write signal 184 for setting and registering the I / O address is output.

The decoder 32 in the transfer address writing circuit 30 decodes the address on the address bus 181 in response to the write signal 302 from the CPU 15.
Then, the decoder 32 determines that the address is the I / O address registration / comparison circuit 3 in the transfer address writing circuit 30.
When the register 311 in the I / O address registration / comparison circuit 31 in the group 1 is indicated, the write signal 321 to the register 311 is output. Then, the data on the data bus 182, that is, the I / O address assigned to the address register of the corresponding bus master is written in the register 311 in response to the write signal 321 from the decoder 32.

In this way, each I / O address registration /
The I / O address assigned to the address register of the corresponding bus master is set and registered in the register 311 in the comparison circuit.

Now, I of the transfer address writing circuit 30
Comparator 3 provided in the / O address registration / comparison circuit 31
The reference numeral 12 constantly monitors the address bus 181, and when an I / O address that matches the setting registration contents of the register 311 is detected, an address register of a bus master on the system bus 11 to which the I / O address is assigned is detected. It outputs a valid match signal 313, assuming that the access from the CPU 15 has occurred.

If the access from the CPU 15 is a register write for writing the start address of the transfer destination into the address register of the bus master designated by the address (I / O address) on the address bus 181, the data bus 182 The top address of the transfer destination is output from the CPU 15 as in the above embodiment. Also CP
A write signal 184 is also output from U15.

The gate 314 in the I / O address registration / comparison circuit 31 keeps the write signal 184 from the CPU 15 as it is while the match signal 313 from the comparator 312 is valid, and the corresponding register in the register control circuit 23. Two
It is output as a write signal 301 to 31.

As a result, the head address of the transfer destination is designated from the CPU 15 to the address register of the bus master on the system bus 11 (for example, the address register of the DMA device 121 in the disk interface 12).
(Transfer command) When register access for writing is performed, the register 231 in the register 231 corresponding to the bus master receives the write signal 301 from the I / O address registration / comparison circuit 31 (internal gate 314) corresponding to the bus master. Then, the data on the data bus 182, that is, the start address of the same transfer destination as the address register of the bus master is written. Subsequent operations are the same as those in the above-described embodiment, and thus the description is omitted.

[0077]

As described in detail above, according to the present invention, a copy of the address indicating the access destination to the memory or the like set in the bus utilization device by the data transfer instruction means is stored in the address holding means (second address). Even if the address is garbled over a plurality of bits, the address failure can be ensured by holding the data in the holding means) and checking the address output from the bus using device based on the held content. Can be detected.

According to the present invention, the setting of the transfer address in the bus utilization device by the data transfer instruction means is detected, and the address holding means corresponding to the bus utilization device is used as the reference address for detecting the address failure. With the configuration in which the second address holding unit is set, the reference address can be easily set and registered.

Further, according to the present invention, the address (I / O address) assigned to the address holding means (first address holding means) of each bus utilization device is different from that provided for each bus utilization device. It is registered in the address holding means (third address holding means), and at the time of setting the transfer address in the first address holding means of a certain bus utilization device,
The third address holding means in which the address designating the first address holding means is registered is detected, and the third address holding means is detected.
When the same transfer address is set in the second address holding means corresponding to the address register holding means of No. 2, the address assigned to the first address holding means of each bus utilization device is not fixed in the system. However, when the address is set in the first address holding means of the bus utilization device, the address can be set in the corresponding second address holding means.

Further, according to the present invention, when it is detected that the address on the bus is incorrect, the access from the bus utilization device is forcibly aborted as an error so that the incorrect address can be obtained. It is possible to prevent access to the memory or the like and destruction of the contents of the memory area that is not the original transfer destination.

Further, according to the present invention, the bus utilization device updates the address while using the address set in the first address register holding means of the bus utilization device as the start address of the DMA transfer, and At the time of DMA transfer in which data is transferred in multiple steps, each transfer
Alternatively, each time the transfer address is detected to be correct, the address held in the second address holding means corresponding to the bus utilization device is updated by the transfer size, so that the DMA transfer period In addition, it is possible to reliably detect the failure of the address output from the bus utilization device with reference to the content of the corresponding second address holding means.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a bus control circuit 17 in FIG.

FIG. 3 is a block diagram showing a configuration of a transfer address writing circuit 30 which replaces the decoder 24 in FIG.

FIG. 4 is a block diagram showing the overall configuration of a conventional information processing device.

[Explanation of symbols]

11 ... System bus, 12 ... Disk interface (bus utilization device), 14 ... I / O device (bus utilization device), 15 ... CPU (data transfer instruction means, address setting means), 16 ... Memory controller (access control means) , 17 ... Bus control circuit, 18 ... Internal bus, 19 ... Main memory, 20 ... Control section, 23 ... Register control circuit (update means), 24 ... Decoder (address setting detection means, decoding means), 25 ... Comparator ( Comparing means, first comparing means), 30 ... Transfer address writing circuit, 31 ... I / O
Address registration / comparison circuit, 32 ... Decoder (decoding means), 171 ... Error signal, 184 ... Write signal (first
Write signal), 231, ... Register (second address holding means), 241 ... Write signal (second write signal),
301 ... Write signal (second write signal), 302 ... Write signal (third write signal), 311 ... Register (third address holding means), 312 ... Comparator (second comparing means), 321 ... Write signal (fourth write signal).

Claims (7)

[Claims] 1. A first address holding means is provided, and according to an address indicating an access destination set in the first address holding means by the data transfer instruction means via a bus,
In an information processing device including a plurality of bus utilization devices that perform data transfer via the bus, for retaining the same address as the address set in the first address retaining means of each bus utilization device, A second provided corresponding to each of the bus utilization devices
Address holding means, an address output from the bus using device on the bus during data transfer by the bus using device, and an address held in the second address holding device corresponding to the bus using device. An information processing apparatus comprising: a comparison unit that compares the addresses and determines whether the addresses on the bus are correct based on whether the addresses match. 2. The bus is monitored to detect an address setting in the first address holding means in the bus using device by the data transfer instructing means, and the second holding corresponding to the bus using device is detected. The means further comprises an address setting detection means for outputting a write signal for writing an address set in the first address holding means by the data transfer instruction means via the bus. 1. The information processing device according to 1. 3. The data transfer instruction means to the respective second address holding means corresponding to the respective bus utilization devices,
2. The information processing apparatus according to claim 1, further comprising means for setting a copy of the contents held by the first address holding means of each of the bus utilization devices. 4. A first address holding means is provided, and the first address holding means is provided.
A plurality of bus utilization devices for transferring data via the bus according to the address indicating the access destination set in the address retention means, an address designating the first address retention means in the bus utilization device, and the first address. By outputting the address indicating the access destination as the data to be written in the address holding means onto the bus together with the first write signal, the first address holding means indicates the access destination which is the write data on the bus. In an information processing apparatus having a data transfer instruction means for setting an address and instructing data transfer, for holding the same address as the address set in the first address holding means of each bus utilization device, respectively. Second provided corresponding to each of the bus utilization devices
Address holding means and the first write signal from the data transfer instructing means, the address designating the first address holding means on the bus is decoded, and the first address designated by the address is decoded. Decoding for outputting a second write signal for writing an address indicating an access destination, which is the write data on the bus, to the second address holding means corresponding to the bus using device having one address holding means. Comparing the address output on the bus from the bus using device at the time of data transfer by the bus using device with the address held in the second address holding means corresponding to the bus using device, Comparing means for detecting whether or not the address on the bus is correct depending on whether or not both addresses match. The information processing apparatus according to claim. 5. A first address holding unit is provided, and the first address holding unit is provided.
A plurality of bus utilization devices for transferring data via the bus according to the address indicating the access destination set in the address retention means, an address designating the first address retention means in the bus utilization device, and the first address. By outputting the address indicating the access destination as the data to be written to the address holding means to the bus together with the first write signal, the first address holding means indicates the access destination which is the write data on the bus. In an information processing apparatus having a data transfer instruction means for setting an address and instructing data transfer, for holding the same address as the address set in the first address holding means of each bus utilization device, respectively. Second provided corresponding to each of the bus utilization devices
Address holding means, and third address holding means provided corresponding to each bus using device for holding an address designating the first address holding device of each bus using device, respectively. At the time of data transfer by the bus using device, the address output from the bus using device on the bus is compared with the address held in the second address holding means corresponding to the bus using device, and both addresses match. First comparing means for detecting whether the address on the bus is correct or not, and for setting the address in the first address holding means in the bus utilization device by the data transfer instructing means. In order to compare the address that is output to the bus and specifies the first address holding means with the contents held in the third address holding means. Then, a second for writing the address indicating the access destination, which is the write data on the bus, to the second address holding means corresponding to the third address holding means having the held content that matches this address. Corresponding to the third comparing means for outputting the write signal, the address for designating the third address holding means, and the third address holding means as the data to be written in the third address holding means. Depending on the address setting means for outputting the address designating the first address holding means of the bus utilization device on the bus together with the third write signal, and the third write signal from the address setting means. , Decoding an address designating the third address holding means on the bus, and designating the third address designated by this address. Information processing, characterized in that the address holding means comprises a decoding means for outputting a fourth write signal for writing an address designating the third address holding means, which is the write data on the bus. apparatus. 6. An access control means for forcibly canceling an access from the bus utilization device as an error when it is detected that the address on the bus is incorrect. The information processing apparatus according to claim 5. 7. The bus utilization device has a DMA (direct memory access) transfer function, and the bus utilization device uses the address set in the first address register holding means by the data transfer instruction means. When the data having the transfer length instructed by the data transfer instructing means is transferred in plural times while updating the address as the head address of the DMA transfer, the transfer address may be correct for each transfer. 3. The method according to claim 1, further comprising update means for updating the address held in the second address holding means corresponding to the bus utilization device by the transfer size for each detected transfer. Item 7. The information processing device according to any one of items 6.