JP2000148658A - Dma transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the DMA transfer of data to a write-inhibited area in a main storage means and to prevent the data on the memory from being destroyed by providing a storage means stored with an area, to which DMA transfer can be carried out in the main storage means and performing the DMA transfer to only the area stored in the storage means of the main storage means. SOLUTION: This system is provided with a CPU 10, a main memory 30 as the main storage means, a memory controller 20 as a control means which controls the main memory 30, and a nonvolatile memory 40 as the storage means stored with the area which is usable in the main memory 30 for DMA transfer. In the storage means, the area to which the DMA transfer can be carried out in the main storage means 30 is stored, and the DMA transfer is performed to only the area stored in the storage means of the main storage means 30. Consequently, data will not be transferred by DMA to the write- inhibited area in the main storage means 30, and the data on the memory are prevented from being destroyed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
ct Memory Access) transfer method.

[0002]

2. Description of the Related Art FIGS. 5A and 5B show a memory access method in a general computer system. FIG. 5A shows a memory access in a memory mapped I / O method, and FIG. 5B shows an I / O address method. FIG. 6 is a diagram showing memory access in the embodiment.

As shown in FIG. 5, in general, in a memory access of a computer system, a CPU 110 is used.
There is an access from the peripheral device 120 and an access from the peripheral device 120. Of these, a DMA transfer is used in the access from the peripheral device 120, and the memory-mapped I / O method and the I / O
There are two methods, the / O address method.

[0004]

However, in the above-described memory access, when a write operation from a peripheral device to a main storage device is performed by DMA transfer, the memory is directly accessed, so that an MMU (Memory M) is used.
(Analysis Unit) cannot be performed. For this reason, due to a driver bug or the like, there is a possibility that data from a peripheral device is written to an address of a memory space that should not be accessed and data stored in the main storage device is destroyed. There is.

[0005] At this time, if the data to be destroyed is an OS or another driver program, it may cause a failure such as the occurrence of a PANIC and cause a system down.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a DMA transfer system capable of preventing data on a memory from being destroyed. I do.

[0007]

According to the present invention, a CPU, a main storage means and a plurality of peripheral devices are connected to each other via a bus, and data from the CPU and the plurality of peripheral devices are transmitted. In the DMA transfer method in which the DMA transfer is performed to the main storage unit, the DMA transfer method includes a storage unit in which the DMA transferable area in the main storage unit is stored, and the DMA transfer is performed in an area stored in the storage unit. It is performed only for

Further, when the data area for performing the DMA transfer does not match the area stored in the storage means, the setting of the DMA transfer is performed again.

Further, the storage means is a nonvolatile memory.

Also, CPs connected to each other via a bus
U, a main storage means, a plurality of peripheral devices, and a control means for controlling the main storage means, wherein the data from the CPU and the plurality of peripheral devices is DMA-transferred to the main storage means. The control means includes: a register storing a predetermined privileged area; an address register receiving an address DMA-transferred from the CPU and the plurality of peripheral devices; and a DMA transfer from the CPU and the plurality of peripheral devices. A data register to which the input data is input, a privileged area stored in the register, and an address input to the address register are compared, and the address input to the address register is compared to the privileged area stored in the register. Detecting means for outputting an address input to the address register only when the address is outside the Among the data input to the register, characterized in that only the data having the address output from said detection means is DMA transferred to the main memory unit.

When the address input to the address register is within a privileged area stored in the register, the detecting means stops the DMA transfer and outputs an error signal to the CPU. It is characterized by the following.

[0012] When the address input to the address register is within the privileged area stored in the register, the detecting means may change the data having the address out of the data input to the data register. It is characterized by being discarded.

(Operation) In the present invention configured as described above, in the storage means, the DMA in the main storage means is provided.
A transferable area is stored. At the time of DMA transfer,
Since the DMA transfer is performed only to the area of the main storage unit stored in the storage unit, the data is not DMA-transferred to the write-protected area in the main storage unit.
Destruction of data on the memory is prevented in advance.

In the detecting means provided in the control means for controlling the main storage means, the privilege area stored in the register is compared with the address inputted in the address register, and the address inputted in the address register is compared. Is transferred to the main storage means only when the address is outside the privileged area stored in the register, and when the address inputted in the address register is stored in the register. If it is within the range, the DMA transfer is stopped, so that the data is not DMA-transferred to an area where the OS and the driver are stored and are not likely to be destroyed.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG.
FIG. 2 is a diagram illustrating a first embodiment of an MA transfer method.

In this embodiment, as shown in FIG.
A main memory 30 serving as a main storage unit; and a memory controller 2 serving as a control unit for controlling the main memory 30.
0 and a non-volatile memory 4 which is a storage means for storing an area available for DMA transfer in the main memory 30.
0, a peripheral device 80a, 80b connected to each other via an I / O bus 70, and a CPU connecting the CPU 10, the memory controller 20, and the nonvolatile memory 40 to each other.
It comprises a memory bus 50, and a bus bridge 60 connecting the CPU-memory bus 50 and the I / O bus 70.

Hereinafter, a DMA transfer operation in the DMA transfer system configured as described above will be described.

FIG. 2 is a flowchart for explaining a DMA transfer operation in the DMA transfer system shown in FIG.

When the computer system is started, for example, when the power of the computer system is turned on, the ITF is first executed, and the hardware in the system is initialized (step S1).

Next, an OS (operating system)
Is loaded from a hard desk or the like and expanded on the main memory 30 (step S2).

When the OS is loaded on the main memory 30 in step S2, the driver used in the computer system is loaded on the main memory 30 (step S3).

Here, in the OS, an area permitted to be used at the time of DMA transfer is stored in the non-volatile memory 40 (step S4). Thus, the preparation of the computer system is completed, and the operation by the application can be started.

Next, consider a case where data is transferred from the peripheral device 80a by DMA transfer.

When the system is started (step S5) and the DMA transfer of the peripheral device 80a is started (step S5).
6) In the driver that starts the DMA transfer of the peripheral device 80a, the memory area used by the driver and the OS
And the area stored in the non-volatile memory 40 is checked before the DMA transfer (step S).
7).

As a result of the check in step S7, if the area used by the driver matches the area stored in the non-volatile memory 40, the DMA transfer from the peripheral device 80a starts (step S8). (Step S9).

On the other hand, as a result of the check in step S7, the area used by the driver and the nonvolatile memory 40
If the area stored in the area does not match, the area for DMA transfer is changed and reset (step S1).
0) Then, the process returns to step S6 again, and a check is performed.

(Second Embodiment) The present invention can be configured without using the nonvolatile memory 40 shown in FIG.

FIG. 3 is a diagram showing a second embodiment of the DMA transfer system according to the present invention, and shows a configuration example of the memory controller 20 when the nonvolatile memory 40 shown in FIG. 1 is not used.

As shown in FIG. 3, the memory controller 20 according to the present embodiment is provided with a register 21 in which a predetermined privileged area is stored, and a memory 21 via a CPU-memory bus 50.
Address register 22 to which MA transfer address is input
And the data register 23 to which the DMA transfer data is input via the CPU-memory bus 50, and compares the privileged area stored in the register 21 with the address input to the address register 22. If the address is outside the privileged area stored in the register 21, the address input to the address register 22 is output, and the address input to the address register 22 is within the privileged area stored in the register 21. A detection circuit 24 outputs an error signal in a case, and a memory address register 25 outputs an address output from the detection circuit 24 to the main memory 30. In the privileged area stored in the register 21, an area in which the OS and the driver are stored and which is difficult to be destroyed is set.

Hereinafter, a DMA transfer operation in the DMA transfer system configured as described above will be described with reference to FIGS.

FIG. 4 is a flowchart for explaining a DMA transfer operation in the DMA transfer system having the memory controller shown in FIG.

When the computer system is started, for example, when the power of the computer system is turned on, the ITF is executed first, and the hardware in the system is initialized (step S11).

Next, an OS (operating system)
Is loaded from a hard desk or the like and expanded on the main memory 30 (step S12).

In step S12, the main memory 30
When the OS is expanded on the upper side, the driver used in the computer system is expanded on the main memory 30 (step S13).

Here, in the CPU 10, an area in which the OS and the driver are stored and which is not likely to be destroyed is set in the register 21 as a privileged area (step S14).

Next, consider a case where data is transferred from the peripheral device 80a by DMA transfer.

When the system is started (step S15) and the DMA transfer of the peripheral device 80a is started (step S15).
16), the first DMA transfer address and data flow through the CPU-memory bus 50, and are input to the address register 22 and the data register 23, respectively.

Next, in the detection circuit 24, the DMA transfer address input to the address register 22 is compared with the privileged area set in step S14, whereby whether the DMA transfer is an access to the privileged area is determined. It is determined (step S17).

In step S17, if the address input to the address register 22 is outside the privileged area stored in the register 21, the address input to the address register 22 is transferred to the main memory 30 via the main address register 25. And the data input to the data register 23 is output to the main memory 30, whereby the DMA transfer data is written to the main memory 30 (step S18), and the process proceeds to the next processing (step S19). .

On the other hand, in step S17, if the address input to the address register 22 is within the privileged area stored in the register 21, it is recognized that a problem has occurred in the DMA transfer address, and the DMA transfer is stopped. At the same time (step S20), an error signal is output to the CPU 10 (step S21). At this time, the data write operation to the main memory 30 is not performed, and the data input to the data register 23 via the CPU-memory bus 50 is discarded.

The transfer sequence ends normally so that the next transfer can be performed, and the next DMA
It is in a state of waiting for transfer.

Thus, the OS and driver programs on the memory can be protected without stalling the computer system.

[0044]

As described above, in the present invention,
A storage unit in which a DMA transferable area is stored in the main storage unit is provided, and the DMA transfer is performed only to the area of the main storage unit stored in the storage unit during the DMA transfer. DMA transfer of data to the write-inhibited area in the means can be avoided, and thereby destruction of data on the memory can be prevented in advance.

In the control means for controlling the main storage means, detection means for comparing the privilege area stored in the register with the address inputted in the address register is provided, and the address inputted in the address register is stored in the register. The data having the address input to the address register is transferred to the main storage means only when the address is outside the privileged area stored in the address area, and the address input to the address register is stored in the privileged area stored in the register. In such a case, the DMA transfer is stopped, so that it is possible to avoid DMA transfer of data to an area where the OS or driver is stored and is not likely to be destroyed. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a DMA transfer system according to the present invention.

FIG. 2 is a flowchart for explaining a DMA transfer operation in the DMA transfer method shown in FIG.

FIG. 3 is a diagram showing a second embodiment of the DMA transfer system of the present invention.

4 is a DM having the memory controller shown in FIG.
5 is a flowchart for explaining a DMA transfer operation in the A transfer method.

5A and 5B are diagrams showing a memory access method in a general computer system, wherein FIG. 5A shows a memory access in a memory mapped I / O method, and FIG. 5B shows a memory access in an I / O address method; FIG.

[Explanation of symbols]

 10 CPU 20 Memory Controller 21 Register 22 Address Register 23 Data Register 24 Detection Circuit 25 Memory Address Register 30 Main Memory 40 Non-Volatile Memory 50 CPU-Memory Bus 60 Bus Bridge 70 I / O Bus 80a, 80b Peripheral Device

Claims (6)

[Claims] 1. A DMA transfer system in which a CPU, a main storage means, and a plurality of peripheral devices are connected to each other via a bus, and data from the CPU and the plurality of peripheral devices are DMA-transferred to the main storage means. A DMA transfer method, comprising: storage means for storing the DMA transferable area in a main storage means, wherein the DMA transfer is performed only for the area stored in the storage means. 2. The DMA transfer method according to claim 1, wherein the data area to be subjected to the DMA transfer does not match the area stored in the storage means.
A DMA transfer method characterized in that transfer settings are redone. 3. The DMA according to claim 1 or 2,
In the transfer method, the storage means is a nonvolatile memory. 4. A CPU connected to each other via a bus,
A main storage unit and a plurality of peripheral devices; and a control unit for controlling the main storage unit. Data from the CPU and the plurality of peripheral devices is DMA-transferred to the main storage unit.
In the MA transfer method, the control means includes: a register storing a predetermined privileged area; an address register receiving an address DMA-transferred from the CPU and a plurality of peripheral devices; A data register to which data transferred by DMA from the device is input, a privileged area stored in the register and an address input to the address register are compared, and an address input to the address register is stored in the register. Detecting means for outputting an address input to the address register only when the address is outside the privileged area, and having an address output from the detecting means among data input to the data register. DMA wherein only data is DMA-transferred to said main storage means. Transmission system. 5. The DMA transfer system according to claim 4, wherein said detecting means stops said DMA transfer when an address input to said address register is within a privileged area stored in said register. And outputting an error signal to the CPU. 6. The DMA transfer method according to claim 5, wherein the detecting unit is configured to input the address input to the data register when the address input to the address register is within a privileged area stored in the register. Of the data
A DMA transfer method for discarding data having the address.