JPH08263328A - Bus trace device and method - Google Patents

Abstract

PURPOSE: To provide a bus trace device of high performance which can eliminate the discontinuation of the system operation in a fault detection mode and the change of the circuit constitution that is required in response to the fault detection mode by using a bus trace function that is connected to the system and adaptive to the different fault detection modes. CONSTITUTION: A bus trace device is connected to a system bus 2 and traces the bus information necessary for detection of faults. Then the bus trace device is provided with a trace memory 13 of large capacity consisting of a DRAM of a double memory block system and a fast trace memory 14 which serve as the trace memories that store the trace data. A bus trace control circuit 15 controls the trace operations and also controls the write operations of both memories 13 and 14 in accordance with the trace start/stop conditions that are set by an SVP 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus trace device in a computer system, and more particularly to a bus trace device for connecting to a system bus and tracing data transferred on the bus.

[0002]

2. Description of the Related Art Conventionally, in a computer system, a plurality of devices are connected to a system bus and each device operates in a time division manner. When a failure occurs in such a system, it is necessary to have a failure detection function for identifying the apparatus in which failure has occurred and the details of the failure.

With the fault detection function, in the case of a relatively simple fault such as a parity error, it is easy to identify the device in which the fault has occurred. For example, by providing a parity error check function on the receiving device side,
The receiving device checks the information transmitted by the transmitting device, and notifies the transmitting device of the check result.

However, for example, in a memory device, when the storage content of a specific address is destroyed by a data write operation from a certain device (CPU etc.), a simple check function cannot deal with it.

Such a complicated fault detection function requires a bus trace device (or bus trap device) for monitoring data (bus information) transferred on the system bus. Conventionally, when a failure occurs, a bus trace device is connected to the system bus to monitor bus information,
Transfer to service processor. The service processor detects the device that causes the failure and the content of the failure according to the bus information transferred from the bus trace device.

With the fault detection function using the bus trace device, in addition to the fault detection of the memory device, for example, when the interrupt operation is activated by the device number (ID information), the device which outputs the illegal device number is specified. Such failure detection can also be realized.

[0007]

As described above, a bus trace device for monitoring bus information is indispensable for realizing a complicated fault detecting function. The bus trace device usually has a large-capacity trace memory for storing data (trace data) extracted from the bus. This trace memory is a DRA that can be easily increased in capacity.
M (dynamic RAM) is used.

However, since the DRAM requires a refresh operation, the access operation is relatively slow.
Since the frequency of the bus clock has recently become high, data that falls out of the bus data to be secured as trace data occurs in a single memory block composed of DRAM. It is possible to use a high-speed access SRAM (static RAM) instead of the DRAM, but it is difficult to increase the capacity of the SRAM in terms of cost and the like.

Further, when a failure occurs, it may be necessary to analyze the movement (change) of the signal before and after the failure in detail. For example, it is a case where it is desired to detect a signal change in a predetermined unit (10 ns) within one bus cycle (160 ns).

As described above, according to the failure detection mode,
It is necessary to change the function (connection condition) of the bus trace device. Conventionally, the circuit configuration of the bus trace device is changed according to the connection condition and incorporated in the system. Therefore, it is necessary to suspend the operation of the system for the failure detection operation.

An object of the present invention is to provide a bus trace function for connecting to a system and adapting to different failure detection modes, thereby eliminating system stoppage at the time of failure detection and circuit configuration change according to the failure detection mode. It is to provide a high-performance bus trace device that can realize the above.

[0012]

The present invention particularly relates to a bus trace device for connecting to a system bus and tracing bus information necessary for fault detection, and as memory means for storing trace data, a memory such as a DRAM is used. A memory means having two or more blocks is provided. Further, the apparatus has a trace control means for controlling the memory means and controlling the trace operation according to the start and stop conditions of the trace.

[0013]

According to the present invention, the memory means for storing the trace data is composed of two or more memory blocks.
A large capacity DRAM is used as each memory block, and D
Even during the RAM refreshing operation, the memory blocks can be alternately activated to reliably save the trace data. Further, the trace control means can change the conditions for starting and stopping the trace to realize a bus trace function adapted to different failure detection modes.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a main part of a bus trace device according to the present embodiment, FIG. 2 is a block diagram showing a main part of a system using the bus trace device according to the present embodiment, and FIG.
6 to 7 are conceptual diagrams for explaining the configuration of the trace memory used in the bus trace device of this embodiment, FIG. 7 is a timing chart for explaining the operation of the trace memory, and FIG. 8 is for this embodiment. FIG. 9 is a block diagram for explaining the configuration of the bus trace control circuit, and FIG. 9 is a flow chart for explaining the operation of this embodiment. (System Configuration) The bus trace device 1 of the present embodiment is
As shown in FIG. 2, it is connected to, for example, the system bus 2 of the information processing system. The system bus 2 is, for example, a bus that connects the central processing unit and the I / O device and transmits the input / output processing from the central processing unit to the I / O device.

The system bus 2 includes a central processing unit 3, which is a system main body, a service processor (SVP) 4, a distributed control processor 5 and a multi-linkage memory (M).
LM) 6 is connected.

The central processing unit 3 includes a bus controller 3a connected to the system bus 2 and a basic input / output processor (B).
It has an IOP) 3b, a system control unit (SCU) 3c, an arithmetic control unit (ACP) 3d, and a main memory 3e whose access is controlled by the SCU 3c.

The SVP 4 is a component of the fault detection function in this embodiment, and inputs a command necessary for fault detection processing and outputs a fault detection result (analysis result) via the input / output device 4a. Further, the SVP 4 is connected to the bus trace device 1 of the present embodiment via an interface (described later) to transmit the start and stop conditions of the trace operation,
The trace data transferred from the bus trace device 1 is received. (Structure of Bus Trace Device) As shown in FIG. 1, the bus trace device 1 of the present embodiment is connected to a system bus 2 and temporarily stores information for transferring the bus (hereinafter referred to as trace data). It has a register 10a and a high speed register 10b. The bus trace device 1 has a memory data bus (MD bus) 11 and a microprocessor bus (MPU bus) 12 as internal buses. Trace memories 13 and 14 and a bus trace control circuit 15 are connected to the MD bus 11.

The trace memory comprises a large capacity trace memory 13 composed of a large capacity DRAM and a high speed trace memory 14 composed of an SRAM. The large-capacity trace memory 13 includes, for example, a first DRAM 13a and a second DRAM 13b that form two memory blocks (two surfaces).
And stores the trace data from the system bus 2 via the register 10a. High speed trace memory 14
From the system bus 2 via the high speed register 10b,
Especially, the trace data transferred by the high speed bus clock is saved.

The memory control circuit 16 is a programmable logic array (PLA) that executes data write control of the large capacity trace memory 13 and the high speed trace memory 14.
The address signal, write enable signal, RA
It outputs various memory control signals such as S / CAS signals.

The bus trace control circuit 15 executes write control of the trace memories 13 and 14 via the memory control circuit 16 to control the start and stop of the trace operation.
It is LA. Because of PLA, bus trace control circuit 15
The control content of can be set arbitrarily. In this embodiment, the bus trace control circuit 15 uses the interface (RS2
32C controller) 18 and information TS indicating the conditions for starting and stopping the trace operation transferred from the SVP 4
To receive.

The MPU 17 is a control device for executing control of the entire bus trace device 1, and particularly controls data transfer via the RS232C controller 18 and the SCSI controller 19 which are interfaces.

The SCSI controller 19 is an interface for connecting the bus trace device 1 and the SVP 4, and has a large capacity trace memory 13 and a high speed trace memory 1.
The trace data stored in 4 is transferred to the SVP 4 under the control of the MPU 17. RS232C controller 18
Controls the trace data to SVP4 under the control of MPU17.
And the information TS indicating the conditions for starting and stopping the trace operation from the SVP4. (Structure of Trace Memory) As described above, the trace memory is composed of the small-capacity high-speed trace memory 14 and the low-speed large-capacity trace memory 13. Large capacity trace memory 1
3 is, for example, 4 Mbit DRA as one memory block
8 M are used, the first DRAM 13a and the second DRA
It is a two-memory block system of M13b.

In this embodiment, the large capacity trace memory 13 is used.
Is assumed to be written from the system bus 1 in a unit of 128 bits and read from the MPU 17 in a unit of 16 bits, as shown in FIG. Furthermore, the large-capacity trace memory 13 has a maximum capacity of 8 Mbytes in two memory blocks. Further, as shown in FIG. 5, the large-capacity trace memory 13 is divided into blocks of 64 Kbytes each, and the block switching register 23 executes block switching processing. The block switching register 23 is
The contents are updated by 7 I / O (input / output) accesses. Therefore, as shown in FIG. 4, the large-capacity trace memory 13 has a maximum of 128 blocks, and each block can store 4096 event trace data.

The event format of the trace memory as seen from the MPU 17 is, as shown in FIGS. 3A and 3B, a control signal, function / parity information, SID.
/ DID information, address information, and data. As shown in FIG. 3B, the event format is composed of 16-bit event information 1-8 in detail. That is, the control signal 1/2 means arbitration information, and a total of 32
Event information 1 and 2 consisting of bits. The function / parity information is the function information (Fun
c. ), Function / ID parity information (F, I
DP), address parity information (ADRS.P), and data parity information (DATA P), which is event information 3 consisting of 16 bits in total.

Further, the SID / DID information is the source I
The event information 4 means D information (transmission device number) and destination ID information (reception device number) and is 16 bits in total. The address information is upper information (ADR
S. UPPER) and lower information (ADRS.LOWER)
Event information 5 and 6 of 32 bits in total. The data is a total of 32 bits of event information 7 and 8 including upper information (DATA.UPPER) and lower information (DATA.LOWER).

As shown in FIG. 6, the large-capacity trace memory 13 temporarily latches the trace data in 128-bit units from the system bus 2 in the register 10a, and the data latched in the register 10a is registered in the register 10c.
It is stored in the memory data bus 11 after being received via.

Next, the high speed trace memory 14 and the large capacity trace memory 13 operate at the timing shown in FIG. The high-speed trace memory (SRAM) 14 writes the trace data transferred by the high-speed clock BCn having a frequency four times as high as that of the normal bus clock BC (160 ns / c).

On the other hand, the large-capacity trace memory 13 has the first
And the second DRAMs 13a and 13b alternately operate, and are controlled to perform refresh when they are not operating. As a result, the large-capacity trace memory 13 keeps the first and second DRAMs 13a, 13a even during the refresh period.
Trace data can be written by any of b. (Structure of Bus Trace Control Circuit) As shown in FIG. 8, the bus trace control circuit 15 of the present embodiment has a driver / receiver 15a and a trace data buffer (TD buffer).
15b, a control circuit 15c, a mask register 15d, a match register 15e, a comparison circuit 15f, and a logic gate circuit 15g.

The driver / receiver 15a is the MD bus 1
1 and the data bus 12b of the MPU bus 12 are connected to exchange data. The TD buffer 15b is a 128-bit buffer memory that stores event information of trace data transferred via the MD bus 11.

The control circuit 15c is composed of a PLA including an I / O decoder for decoding an address from the MPU 17 transferred via the address bus 12a of the MPU bus 12, and includes a TD buffer 15b, a mask register 15d, and a match register 15e. Control each operation.

The match register 15e is used for the data bus 12
A group of 8 registers for setting the trace condition (match condition) transferred from the MPU 17 via b (total 1
28-bit register). Similarly, the mask register 15d is composed of a group of 8 registers (total 128-bit registers) for setting the trace condition (mask condition) transferred from the MPU 17, and sets a check-unnecessary bit.

The comparison circuit 15f compares the respective data in the TD buffer 15b and the match register 15e and generates eight matching match signals M1-M8. Comparison circuit 15
The first input I1 of f is supplied to the mask register 15 via the AND circuit 15i in the data of the TD buffer 15b.
The data masked by the data of d is input. On the other hand, the second input I2 is supplied to the mask register 1 via the AND circuit 15e in the data of the match register 15e.
The data masked by the data of 5d is input.

The logic gate circuit 15g is composed of a PLA including an AND circuit and an OR circuit, and generates a trigger signal TR for controlling the start and stop of the trace based on the match signals M1-M8 output from the comparison circuit 15f. Output.

In summary, the bus trace control circuit 15 is
The conditions for starting and stopping the trace transferred from the outside (SVP4 in this embodiment) via the MPU 17 are set in the match register 15e and the mask register 15d, and stored in the TD buffer 15b via the MD bus 11 under these conditions. Control the start and stop of the trace by checking the trace data. The control of starting and stopping the trace specifically means control of writing the trace data to the trace memories 13 and 14. (Operation of Bus Trace Device) Next, the operation of this embodiment will be described with reference to the flowchart of FIG.

In the system as shown in FIG. 2, assuming that a failure such as the memory content of a specific address being destroyed by a data write operation has occurred in a memory device such as the MLM 6, the bus trace device 1 is used as a system. Or connect the bus trace device 1 which is always available to S
It is activated by VP4. The bus trace device 1 monitors the bus information of the system bus 2 and uses the trace memory 13,
The trace data stored in 14 is transferred to SVP4.
The SVP 4 executes the fault detection processing of the memory device or the like according to the trace data monitored (saved) by the bus trace device 1.

In such a failure detection operation, the SVP
4 first transfers the information TS indicating the conditions for starting and stopping the trace operation by the bus trace device 1 to the MPU 17 via the RS232C controller 18 (step S1).

The MPU 17 sets the transferred information TS in the bus trace control circuit 15 and also transfers it to the memory control circuit 16 (step S2). The bus trace control circuit 15 outputs a trigger signal TR according to the trace start condition to the memory control circuit 16 by the operation of the comparison circuit 15f and the logic gate circuit 15g shown in FIG. 8 (step S3).

The memory control circuit 16 instructs the high-speed trace memory 14 and the large-capacity trace memory 13 to trace data from the system bus 2 (128-bit bus information) in response to a trace start instruction from the bus trace control circuit 15. Is activated for tracing and writing (steps S4 and S5).

The trace data is stored in the system buses 2 to 1
The data is temporarily latched in 28-bit units in the register 10a and written in the large-capacity trace memory 13 (step S6). As shown in FIG. 7, the large-capacity trace memory 13 synchronizes with the bus clock BC and each of the first and second DRAs.
M13a and 13b are alternately activated to perform the write operation.

Similarly, the trace data is temporarily transferred from the system bus 2 in units of 128 bits to the high speed register 10b.
Latched in and written to the high speed trace memory 14. The high speed trace memory 14 writes the trace data in synchronization with the high speed clock BCn having a frequency higher than the normal bus clock BC, as shown in FIG. 7, according to the trace condition set in the bus trace control circuit 15. .

Here, the bus trace control circuit 15 fetches 128-bit trace data from the system bus 2 at the same time as the write operation of the trace memories 13 and 14,
It is determined whether or not the trace stop condition is met (step S7). That is, as shown in FIG. 8, the trace data is stored in the TD buffer 15b, and the comparison circuit 15f determines whether or not the trace stop condition is satisfied.

The bus trace control circuit 15 continues the trace data write operation to the trace memories 13 and 14 until the trace stop condition is satisfied (NO in step S8).

When the trace stop condition is satisfied, the bus trace control circuit 15 outputs a trigger signal TR according to the trace stop condition to the memory control circuit 16 (YES in step S8, S9). In response to this instruction, the memory control circuit 16 causes the high-speed trace memory 14 and the large-capacity trace memory 13 to stop the trace data write operation.

The SVP4 is an RS232C controller 1
The MPU 17 is instructed via 8 to transfer the trace data stored in the trace memory (step S10).
In response to this instruction, the MPU 17 reads the trace data stored in the high speed trace memory 14 and / or the large capacity trace memory 13 and transfers it to the SVP 4 via the SCSI controller 19 (step S1).
1).

Here, the MPU 17 can also transfer the trace data to the SVP 4 via the RS232C controller 18. The SVP 4 receives the transferred trace data and executes, for example, fault detection processing of the memory device based on the trace data.

As described above, according to this embodiment, since the high-speed trace memory 14 and the large-capacity trace memory 13 of the two-memory block type are provided, the trace data can be traced at high speed and stored, and the large-capacity storage memory can Trace data can be saved. Furthermore, since the large-capacity trace memory 13 is of the two-memory block type,
When a DRAM that requires refreshing is used, refreshing can be performed during the non-writing operation of the memory block. Therefore, DRA that can easily increase the capacity
Even when M is used as the trace memory, it is possible to reliably prevent a situation where data is lost when the trace data is fetched for refreshing. In other words, the large-capacity trace memory 13 using DRAM can surely save the trace data in synchronization with the bus clock BC.

Further, the bus trace control circuit 15 makes the S
Since the configuration is such that the start and stop conditions of the trace can be set from the VP 4, it is possible to realize the control operation in which the trace condition can be easily changed. Therefore, for example, when a failure occurs, in order to analyze the change in the signal before and after the occurrence in detail,
In the bus cycle (160 ns), the start and stop of the trace can be controlled according to the failure detection mode such as the case where it is desired to detect a signal change in a predetermined unit (10 ns). In other words, it is not necessary to change the circuit configuration of the bus trace device according to the fault detection mode as in the conventional case, and it is not necessary to suspend the system operation for the fault detection operation.

Here, as a condition for starting the trace, the specific device designated as the fault detection target is the system bus 2
Is used, or when an address when accessing a specific memory device is within the range of a predetermined area. The conditions for stopping the trace include the following individual conditions or any combination thereof. That is, when there is a device that accesses a specific memory address, when there is a device that accesses specific data, or when the fault detection function of a conventional bus controller operates, a stop instruction is issued from the outside (external trigger signal). There are conditions such as when there is a trace stop command by software.

It should be noted that the bus trace device 1 of the present embodiment may be always provided in the system, or may be used so as to be connected to the system for testing or evaluation of the system at the time of manufacturing.

[0050]

As described in detail above, according to the present invention, there is provided a bus trace device capable of storing high-speed or large-capacity trace data and easily setting the conditions for starting and stopping the trace from the outside. Can be provided. Therefore,
When a system failure is detected, a bus trace function that adapts to a different failure detection mode can be realized without stopping the system when a failure is detected or changing the circuit configuration according to the failure detection mode.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a bus trace device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of a system using the bus trace device according to the present embodiment.

FIG. 3 is a conceptual diagram for explaining a configuration of a trace memory used in the bus trace device of this embodiment.

FIG. 4 is a conceptual diagram for explaining the configuration of a trace memory used in the bus trace device of this embodiment.

FIG. 5 is a conceptual diagram for explaining the configuration of a trace memory used in the bus trace device of this embodiment.

FIG. 6 is a conceptual diagram for explaining the configuration of a trace memory used in the bus trace device of this embodiment.

FIG. 7 is a timing chart for explaining the operation of the trace memory of this embodiment.

FIG. 8 is a block diagram for explaining the configuration of a bus trace control circuit according to this embodiment.

FIG. 9 is a flowchart for explaining the operation of this embodiment.

[Explanation of symbols]

1 ... Bus trace device, 2 ... System bus, 3 ... Central processing unit, 4 ... Service processor, 10a ... Register, 1
0b ... High speed register, 11 ... Memory data bus, 12 ...
Microprocessor bus, 13 ... Large-capacity trace memory, 14 ... High-speed trace memory, 15 ... Bus trace control circuit, 16 ... Memory control circuit, 17 ... Microprocessor, 18, 19 ... Interface.

Claims (5)

[Claims] 1. A bus trace device for connecting to a bus of a computer system to trace data transferred via the bus, which is means for storing data to be traced, and which inputs a predetermined unit of the data. Memory means having two or more memory blocks, controlling start and stop of trace, starting the memory means at the start of the trace and executing the saving of the data, and saving the memory means when the trace is stopped A bus trace device comprising: a trace control means for stopping the operation and transferring the trace data stored in the memory means to the outside. 2. A bus trace device for connecting to a bus of a computer system to trace data transferred via the bus, which is means for storing data to be traced, and which inputs a predetermined unit of the data. Memory means having two or more memory blocks and configured to selectively execute the save operation in synchronization with the cycle of the bus clock for the memory blocks; controlling start and stop of trace; Trace control means for activating the memory means to start the storage of the data at the start, stopping the storage operation of the memory means at the time of stopping the trace, and transferring the trace data stored in the memory means to the outside; A bus trace device comprising: 3. A bus trace device, which is connected to a bus of a computer system and traces data transferred via the bus, is means for storing data to be traced, and a predetermined unit of the data is input. A high-speed memory block that has two or more memory blocks and inputs the data of the predetermined unit at a frequency that is a predetermined multiple of the bus clock in each memory block, and inputs the data of the predetermined unit at the cycle of the bus clock. Memory means including a large-capacity memory block, controlling start and stop of trace, starting the memory means at the start of the trace to save the data, and saving operation of the memory means when the trace is stopped And a trace control means for transferring the trace data stored in the memory means to the outside. Bus trace apparatus according to claim that it has. 4. A bus trace device, which is connected to a bus of a computer system and traces data transferred through the bus, is means for storing data to be traced, and inputs a predetermined unit of the data. Memory means having two or more memory blocks, controlling start and stop of trace, starting the memory means at the start of the trace and executing the saving of the data, and saving the memory means when the trace is stopped Trace control means having a condition setting means for stopping the operation, transferring the trace data stored in the memory means to the outside, and setting the condition for starting or stopping the trace according to the information inputted from the outside. A bus trace device characterized by the above. 5. A computer system comprising: a bus trace device for tracing data transferred by connecting to a bus; and a service processor for executing a fault detection process based on trace data transferred by the bus trace device, A step of setting conditions for starting and stopping a trace transferred from a service processor in the bus trace device; a memory having two or more memory blocks for inputting and storing a predetermined unit of the data at the start of the trace Storing the traced data in the means in synchronization with the cycle of the bus clock, and when the set stop condition of the trace is satisfied,
A bus trace method comprising: a step of stopping a data storage operation of the memory means; and a step of transferring trace data stored in the memory means to the service processor.