JPH0723334A - Digital recording and reproducing device - Google Patents

Abstract

PURPOSE:To prevent the generation of disturbance in the display of a signal display circuit by providing this digital recording and reproducing device with a reproducing/recording delay time control circuit for controlling reproducing or recording delay time for a period corresponding to a difference between delay time values required for recording and reproducing in signal processing circuit. CONSTITUTION:In the case of reproducing, a reproduced signal from a recording medium 6 is demodulated by a demodulating circuit 7 at processing time Do4, the demodulated signal is stored in a corrective decoding memory 9 and the signal stored in the memory 9 is corrected by a corrective decoding circuit 32 including an output delay time control circuit 31 based upon a correction code added by recording at processing time Do3. The signal corrected by the circuit 31 is stored in the memory 9 by the circuit 31 to delay it without directly sending it to a highly efficient decoding circuit 10, the delayed signal is decoded by the circuit 10 at processing time Do2 and the decoded signal is converted into the format of a signal inputted at processing time Do1 by an output signal converting circuit 11 to output the converted signal. Consequently a recording input signal, and a reproduced output signal are synchronized with each other.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recording / reproducing apparatus.

2. Description of the Related Art FIG. 5 is a diagram showing the configuration of a conventional digital recording / reproducing apparatus. In FIG. 5, 1 is an input signal conversion circuit, 2 is a high efficiency encoding circuit, 3 is a correction encoding circuit,
Reference numeral 4 is a correction coding memory, 5 is a modulation circuit, 6 is a recording medium, 7 is a demodulation circuit, 8 is a correction decoding circuit, 9 is a correction decoding memory, 10 is a high efficiency decoding circuit, and 11 is an output signal. A conversion circuit, 12 is an input / output signal changeover switch, and 13 is a signal display circuit. The recording medium 6 here may be magnetic or optical disk, magnetic tape, or memory. FIG. 6 is a timing chart showing the delay of each conventional signal processing circuit. In FIG. 6, 21 is the delay time Di1 of the input signal conversion circuit 1, and 22 is the delay time Di of the high efficiency encoding circuit 2.
2, 23 are delay times Di3 of the correction coding circuit 3, 24 are delay times Di4 of the modulation circuit 5, and 25 are delay times of the demodulation circuit 7.
Do4 and 26 are the delay time Do3 of the correction decoding circuit 8, 27 is the delay time Do2 of the high efficiency decoding circuit 10, 28 is the delay time Do1 of the output signal conversion circuit 11, 29 is the total recording delay time Diall, 30 Is the total playback delay time Doall.
At the time of recording, the recording input signal is input to the input signal conversion circuit 1
Input signal to the input signal conversion circuit 1
Processing time of the signal converted by
The signal coded by Di2 and coded by the high-efficiency coding circuit 2 is stored in the correction coding memory 4 by the correction coding circuit 3.
At the processing time Di3, the correction code is added, and the signal to which the correction code is added at the correction coding circuit 3 is modulated in the modulation circuit 5 at the processing time Di4 and recorded on the recording medium 6. Therefore, in order to record, there is only the time of Diall which is the total of the delay times of the respective signal processing circuits. The recording input signal can be displayed on the signal display circuit 13 by switching the input / output signal changeover switch 12.
During reproduction, the signal reproduced from the recording medium 6 is demodulated in the demodulation circuit 7 in the processing time Do4, the signal demodulated in the demodulation circuit 7 is stored in the correction decoding memory 9, and the processing time Do3 in the correction decoding circuit 8. Then, correction processing is performed by the correction code added at the time of recording, and the signal subjected to the correction processing in the correction decoding circuit 8 is decoded in the processing time Do2 in the high efficiency decoding circuit 10 and decoded in the high efficiency decoding circuit 10. The output signal conversion circuit 11 converts the signal into the signal input in the processing time Do1 and outputs the converted signal. Therefore, in order to reproduce, Dial which is the total delay time of each signal processing circuit
have only l time. The reproduction output signal can be displayed on the signal display circuit 13 by switching the input / output signal changeover switch 12.

However, the above-mentioned conventional structure has the following problems. In the conventional technique, since the delay time of each signal processing circuit is different, the time Diall for recording and the time Doall for reproducing are not the same, so the mode is switched from reproduction to recording and the input / output signal changeover switch is switched. At this time, the continuity of the reproduction output signal from the recording input signal cannot be maintained, and the display of the signal display circuit is disturbed. In view of the problems of the prior art, the present invention provides a delay time of a signal processing circuit required for recording and a signal required for reproduction in a digital recording / reproducing apparatus for recording / reproducing digital data obtained by digitizing a video signal and an audio signal on a recording medium. An object of the present invention is to provide a digital recording / reproducing apparatus including a reproduction or recording delay time control circuit for a time corresponding to a difference in delay time of a processing circuit.

In order to solve the above-mentioned problems, the present invention provides a signal processing required for recording in a digital recording / reproducing apparatus for recording / reproducing digital data obtained by digitizing a video signal and an audio signal on a recording medium. A digital recording / reproducing apparatus comprising a reproduction or recording delay time control circuit for a time corresponding to a difference between a circuit delay time and a signal processing circuit delay time required for reproduction.

According to the present invention, the delay time is controlled so as to maintain the continuity of the recording input signal and the reproduction output signal when the recording is changed to the reproduction and prevent the display of the signal display circuit from being disturbed. .

(Embodiment 1) An embodiment of the present invention will be described below with reference to the accompanying drawings. In the configuration diagram of the embodiment, the description of the blocks having the same numbers as the conventional ones will be omitted. FIG. 1 is a diagram showing the configuration of a digital recording / reproducing apparatus according to a first embodiment of the present invention. In FIG. 1, 3
Reference numeral 1 is an output delay time control circuit, and 32 is a correction decoding circuit having an output delay time control circuit 31. FIG. 2 is a timing chart showing the delay of each signal processing circuit of the first embodiment of the present invention. In FIG. 2, 33 is the delay time Dodela of the output delay time control circuit 31 in the correction decoding circuit 32.
y and 34 are the total delay times of the reproduction signal processing circuit having the correction decoding circuit 32 having the output delay time control circuit 31.
This is Doalla. Compared with the recording delay time Diall and the playback delay time Doall in the past, when the playback delay time Doall is shorter than the recording delay time Diall by Diall−Doall = Dodelay, the following is performed. When reproducing, the recording medium 6
The signal reproduced from the signal is demodulated in the demodulation circuit 7 in the processing time Do4, and the demodulated signal is stored in the correction decoding memory 9,
Correction decoding circuit 32 having output delay time control circuit 31
At the processing time Do3, the correction processing is performed by the correction code added at the time of recording. Here, the signal corrected by the correction decoding circuit 31 is not immediately sent to the high-efficiency decoding circuit 10, but the output delay time control circuit 31 stores the delay time Dodelay in the correction decoding memory 9 and delays or delays it. Signal is processed by the high-efficiency decoding circuit 10 after processing
2 and outputs the decoded signal to the output signal conversion circuit 11
At the processing time Do1, the signal is converted into the input signal form and output. By doing this, the playback delay time Doa11a
It becomes Doall + Dodelay and becomes the same as Diall, and the synchronization of the recording input signal and the reproduction output signal becomes the same. Therefore, by switching the input / output signal changeover switch 12, the signal display circuit 13
At the time of displaying, the continuity of the recording input signal and the reproduction output signal can be maintained, and the display of the signal display circuit 13 is not disturbed. (Embodiment 2) FIG. 3 is a diagram showing the configuration of a digital recording / reproducing apparatus according to a second embodiment of the present invention. In FIG.
Reference numeral 41 is an input delay time control circuit, and 42 is a correction coding circuit having the input delay time control circuit 41. FIG. 4 is a timing chart showing the delay of each signal processing circuit of the second embodiment of the present invention. In FIG. 4, 43 is the delay time Dide of the input delay time control circuit 41 in the correction coding circuit 42.
lay, 44 is the total delay time of the recording signal processing circuit having the correction coding circuit 42 having the input delay time control circuit 41
It's Dialla. Compared with the recording delay time Diall and the playback delay time Doall in the past, when the recording delay time Diall is shorter than the playback delay time Doall by Doall−Diall = Didelay, it is performed as follows. When recording, the recording input signal is input to the input signal conversion circuit 1 and converted in the processing time Di1, and the signal converted in the input signal conversion circuit 1 is encoded in the processing time Di2 in the high efficiency encoding circuit 2 to achieve high efficiency. The signal 4 coded by the coding circuit 2 is stored in the correction coding memory 4, and the correction coding circuit 42 having the input delay time control circuit 41 adds the correction code at the processing time Di3. Here, the signal corrected by the correction coding circuit 41 is not immediately sent to the modulation circuit 5, but the input delay time control circuit 41 stores the delay time Didelay in the correction coding memory 4 and delays it. Is modulated in the modulation circuit 5 for the processing time Di4 and recorded on the recording medium 6. By doing this, the recording delay time is Diall + Didel.
It becomes ay and becomes the same as Doall, and the synchronization of the recording input signal and the reproduction output signal becomes the same. Therefore, when the input / output signal changeover switch 12 is switched to display on the signal display circuit 13, the continuity of the recording input signal and the reproduction output signal can be maintained, and the display of the signal display circuit is not disturbed.

As described above, according to the present invention, the continuity of the recording input signal and the reproduction output signal is maintained at the time of the transition from the recording to the reproduction without increasing the memory, and the signal display circuit It is possible to prevent the display from being disturbed, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital recording / reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a delay of each signal processing circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a digital recording / reproducing apparatus according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing the delay of each signal processing circuit according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional digital recording / reproducing apparatus.

FIG. 6 is a timing chart showing a delay of each conventional signal processing circuit.

[Explanation of symbols]

 1 Input signal conversion circuit 2 High efficiency coding circuit 3 Correction coding circuit 4 Correction coding memory 5 Modulation circuit 6 Recording medium 7 Modulation circuit 8 Correction decoding circuit 9 Correction coding memory 10 High efficiency coding circuit 11 Output Signal conversion circuit 12 Input / output signal changeover switch 13 Signal display circuit 31 Output delay time control circuit 32 Correction decoding circuit 41 Input delay time control circuit 42 Correction coding circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 5/93

Claims (8)

[Claims] 1. A digital recording / reproducing apparatus for recording / reproducing digital data obtained by digitizing a video signal and an audio signal on a recording medium, the delay time of a signal processing circuit required for recording and the delay of a signal processing circuit required for reproduction. A digital recording / reproducing apparatus comprising a reproduction delay time control circuit for a time corresponding to a time difference. 2. A recording delay time control circuit for a time corresponding to the difference between the delay time of the signal processing circuit required for recording and the delay time of the signal processing circuit required for reproduction. Digital recording / reproducing device. 3. A signal processing circuit having a memory and a reproduction delay time adding means for a time corresponding to a difference between the delay time of the signal processing circuit required for recording and the delay time of the signal processing circuit required for reproduction. The digital recording / reproducing apparatus according to claim 1. 4. A signal processing circuit having a memory and a recording delay time adding means for a time corresponding to the difference between the delay time of the signal processing circuit required for recording and the delay time of the signal processing circuit required for reproduction. The digital recording / reproducing apparatus according to claim 1. 5. A delay time of the signal processing circuit from the reference signal of the video signal to the reference signal of the recording medium at the time of recording and the memory, and a signal processing circuit of the signal processing circuit from the reference signal of the recording medium to the reference signal of the video signal at the time of reproduction. 2. The digital recording / reproducing apparatus according to claim 1, further comprising a signal processing circuit having reproduction delay time adding means for a time corresponding to a difference in delay time. 6. A delay time of a signal processing circuit from a reference signal of a video signal to a reference signal of a recording medium at the time of recording in a memory and a signal processing circuit from a reference signal of the recording medium to a reference signal of a video signal at the time of reproduction. 2. The digital recording / reproducing apparatus according to claim 1, further comprising a signal processing circuit having reproduction delay time adding means for a time corresponding to a difference in delay time. 7. A helical scan type digital recording / reproducing apparatus for recording / reproducing digital data on / from a recording track inclined in the longitudinal direction on a magnetic tape by a rotary head, comprising a memory and a video signal at the time of recording. Playback for a time corresponding to the difference between the delay time of the signal processing circuit from the reference signal to the reference signal on the magnetic tape and the delay time of the signal processing circuit from the reference signal on the magnetic tape to the reference signal of the video signal during playback A digital recording / reproducing apparatus comprising a signal processing circuit having a delay time adding means. 8. A helical scan type digital recording / reproducing apparatus for recording / reproducing digital data on / from a recording track inclined in the longitudinal direction on a magnetic tape by a rotary head, comprising a memory and a video signal at the time of recording. Playback for a time corresponding to the difference between the delay time of the signal processing circuit from the reference signal to the reference signal on the magnetic tape and the delay time of the signal processing circuit from the reference signal on the magnetic tape to the reference signal of the video signal during playback A digital recording / reproducing apparatus comprising a signal processing circuit having a delay time adding means.