JP2962067B2 - Digital VTR signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device at the time of slow reproduction in a digital VTR for digitizing and recording and reproducing a video signal.

[0002]

2. Description of the Related Art Image signals and audio signals are digitized,
As a function of a digital VTR that records digital data on a tape, there are special reproduction such as high-speed reproduction and slow reproduction in addition to normal reproduction. In particular, 1 during slow playback
In order to correctly reproduce one screen, processing on the reproduction side is required. Hereinafter, a conventional digital VTR and its slow reproduction will be described.

FIG. 13 is a diagram showing a configuration of a conventional digital VTR reproducing process. In FIG. 13, 1 is a reproduction head, 2 is a reproduction processing circuit, and 3 is an I added at the time of recording.
In which performs error correction based on parity for nner correction
A ner correction decoding circuit 4, an ID detection circuit 4 for detecting identification information (ID) added for each recording block (synchronous block) at the time of recording, 5 is address information created based on the ID, and 6 is added at the time of recording. An outer correction decoding circuit for performing error correction based on the outer correction parity, a memory for performing rearrangement for outer correction, a memory control circuit for supplying an address and a control signal to the memory, Reference numeral 9 denotes a high-efficiency encoding circuit and an output terminal for reproduced data.

First, the operation during reproduction will be briefly described. After the signal reproduced from the reproduction head 1 is subjected to reproduction processing by the reproduction processing circuit 2, the reproduction data is input to the Inner correction decoding circuit 3 in units of synchronous blocks, and
An error correction process is performed based on the parity for correction. Next, the synchronous block subjected to the inner correction processing has the ID
Input to the detection circuit 4, the ID detection circuit 4 outputs address information to the memory from the reproduced ID of the synchronous block, and the memory control circuit 8 writes data to the memory 7 in units of synchronous blocks based on the address information. Synchronous block is the minimum unit when recording on tape,
As shown in FIG. 14, the synchronization pattern (SYNC), I
D, data, and parity for error correction. During normal playback, the synchronous blocks are played back in the order in which they were recorded. However, during special playback, they are not played back in the order in which they were recorded. number,
(Synchronous block number) is included in the ID.

Next, the memory 7 reads data written in units of synchronous blocks in the direction shown in FIG.
The ter correction decoding circuit 6 performs error correction in the Outer direction. Here, the error correction by the outer correction decoding circuit 6 is executed using a parity for outer correction added in a direction shown in FIG. 14 to a predetermined number of synchronous blocks. Finally, the high-efficiency encoded data is decoded by the high-efficiency decoding circuit 9 and output from the terminal 10.

[0006] In normal reproduction, the head traces on one track, whereas in slow reproduction, the head traces across a plurality of tracks and traces the same track a plurality of times. Therefore, slow reproduction can be realized by sequentially writing the reproduction data into the memory and switching the output field when the data for one field is written into the memory. Specifically, the memory 7 has three memories (memory 1, memory 1) each having a capacity of one field.
It has a memory 2 and a memory 3) and operates two for writing and one for reading. For example, when the data of two fields A and B are mixed in the reproduction data, the data of the A field is written to the memory 1, the data of the B field is written to the memory 2, and the remaining memory 3 is already 1 An operation of reading data of another field in which data of the field is written is performed. After that, 1
By sequentially reading from the field in which the data for the field has been written, a slow reproduction operation can be realized.

[0007]

However, the conventional configuration described above has the following problems.

In a digital VTR for broadcasting or business use, recording in fields is performed in consideration of dubbing and editing. On the other hand, in order to realize a long recording time on a small cassette in a home VTR, it is necessary to reduce the amount of information by high-efficiency coding. In order to efficiently reduce the amount of information without significant image quality degradation, it is essential to perform processing using a plurality of fields and perform recording in units of a plurality of fields as well as processing within a field. In this case, if the playback data is detected in units of a plurality of fields during slow playback and is output as it is, a plurality of fields are repeatedly output, and smooth slow playback cannot be realized on a moving screen.

SUMMARY OF THE INVENTION In view of the problems of the prior art, it is an object of the present invention to provide a digital VTR capable of realizing slow reproduction in a field unit in a digital VTR which is encoded and recorded in a plurality of fields at a high efficiency. And

[0010]

In order to solve the above-mentioned problems, a first aspect of the present invention is to divide data which has been subjected to high-efficiency encoding in units of one page into n tracks by setting m fields as one page. In a digital VTR recorded with
Page detection means for detecting that the reproduction of the data of one page has been completed, field detection means for detecting that the reproduction of data of one field of the one page has been completed, and storing the reproduced data. A first memory for performing error correction processing, high-efficiency decoding means for performing high-efficiency decoding on the output of the first memory, and A second memory that converts the data into field-based data and outputs the data, a page switching unit that switches between writing and reading pages of the second memory in accordance with a detection result of the page detection unit, and a detection result of the field detection unit Field switching means for controlling reading of the second memory and switching a field to be output according to It is.

In a second aspect of the present invention, a digital VTR in which data of high efficiency encoding is divided into n tracks and recorded in units of one page with m fields as one page.
, The tape feed is started at regular intervals, and the tape is fed at a slower speed than at the time of normal reproduction, and the tape feed is stopped when the reproduction of (2 / m) pages of the one page is completed. A tape feed control means for performing the data reproduction, a page detection means for detecting that the reproduction of the data of one page is completed, a first memory for storing the reproduced data and performing an error correction process, A high-efficiency decoding means for performing high-efficiency decoding on the output of the memory; a second memory for converting the high-efficiency decoded data in units of one page into data in units of fields and outputting the data; Page switching means for switching between writing and reading pages of the second memory in accordance with the detection result of the detecting means; and the second switching means in accordance with the tape speed by the tape speed control means. A signal processing apparatus in a digital VTR which is characterized in that a field switching means for switching the field to control the reading of the memory output.

Further, a third invention is a digital VT in which data of high efficiency coding is divided into n tracks and recorded in one page unit with m fields as one page.
R, a page detecting means for detecting that the reproduction of the one page of data has been completed, a field detecting means for detecting that the reproduction of one field of data of the one page has been completed, A first memory for storing data and performing error correction processing, a second memory for correcting data that cannot be corrected by the error correction processing, and a high-efficiency decoding for an output of the second memory High-efficiency decoding means for performing the conversion, a third memory for converting the high-efficiency decoded data in units of one page into data in units of fields, and outputting the data, and according to a detection result in the page detection means, First control means for controlling a second memory, and second control means for controlling the third memory and switching a field to be output according to a detection result of the field detection means; A signal processing apparatus in a digital VTR, characterized in that it includes.

According to a fourth aspect of the present invention, there is provided a digital VTR in which data of high efficiency encoding is divided into n tracks and recorded in units of one page with m fields as one page.
, The tape feed is started at regular intervals, and the tape is fed at a slower speed than at the time of normal reproduction, and the tape feed is stopped when the reproduction of (2 / m) pages of the one page is completed. Tape speed control means, a page detection means for detecting that the reproduction of the data for one page has been completed, a first memory for storing the reproduced data and performing an error correction process, and the error correction process. A second memory for modifying data that cannot be corrected by the first memory; a high-efficiency decoding means for performing high-efficiency decoding on the output of the first memory; A third memory for converting data into data in field units and outputting the data, a first control means for controlling the second memory according to a detection result of the page detection means, and a tape speed control means. That is a signal processing apparatus in a digital VTR which is characterized in that a second control means for switching the fields to be printed and controlling said third memory in accordance with the tape speed.

[0014]

According to the first aspect of the present invention, in a digital VTR which records and reproduces data which has been efficiently coded in units of a plurality of fields (one page), the reproduced data is recorded in one page units and one field unit in slow reproduction. And when it is detected that the reproduction of one page of data has been completed, one page is transferred from the first memory for error correction to the second memory for outputting data in frame units in field units. Switch the page for writing and outputting minute data. Next, when it is detected that the reproduction of the data for one field has been completed, the field output from the second memory is switched, thereby realizing a field-by-field throw.

According to the second aspect of the present invention, in the digital VTR which records and reproduces data encoded at high efficiency in units of a plurality of fields (one page), the tape is intermittently fed to realize slow reproduction. . First, the tape is fed slowly, and when it is detected that the reproduction of one page of data has been completed, a second memory for outputting data in frame units in field units from the first memory for error correction is provided. 1 page of data is written in the memory of, and the output page is switched. Next, the tape feed is stopped, and the field output from the second memory is switched at the time when the tape feed is started again, thereby realizing a throw in a field unit.

According to a third aspect of the present invention, there is provided a digital VTR which records and reproduces highly-efficient encoded data in units of a plurality of fields (one page) in the above-described configuration. And when it is detected that the reproduction of the data for one page has been completed, the data for one page is written from the first memory for error correction to the second memory for error correction.
At the same time, the field for writing and outputting one field of data in the third memory for outputting data in frame units in field units is switched. next,
When it is detected that the reproduction of the data for one field has been completed, the field for writing and outputting the data for one field from the second memory to the third memory is switched. By repeating the above processing, a throw in a field unit can be realized.

According to the fourth aspect of the present invention, in the digital VTR which records and reproduces data encoded at high efficiency in units of a plurality of fields (one page), the tape is intermittently fed to realize slow reproduction. . First, tape feeding is performed slowly, and when it is detected that reproduction of one page of data has been completed, one page of data is transferred from the first memory for error correction to the second memory for error correction. Write to. At this time, the field for writing and outputting one field of data to the third memory for simultaneously outputting data in frame units in field units is switched. Next, when the tape feeding is stopped and the tape feeding is started again, the field for writing and outputting one field of data from the second memory to the third memory is switched. By repeating the above processing, a throw in a field unit can be realized.

[0018]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the configuration diagram of the embodiment, the description of the blocks with the same numbers is omitted.

FIG. 1 is a diagram showing a configuration of a signal processing device of a digital VTR according to an embodiment of the present invention.
In FIG. 1, reference numeral 100 denotes a memory for performing rearrangement for Outer correction, 101 denotes a memory control circuit that supplies an address and a control signal to the memory 100, and 102 denotes data for one frame based on the address information 5. , A frame detection signal for detecting that the reproduction of one field is completed based on the address information 5, and a field detection circuit 105 for detecting that the reproduction of the data of one field is completed based on the address information 5. Switching signals 106 and 107 are memories for interlacing one frame of data reproduced in a non-interlace form and outputting the data in field units. 108 is a switch for selecting one of the inputs of the memories 106 and 107.
09 is a switch for selecting one of the outputs of the memories 106 and 107, and 110 and 111 are memory control circuits for supplying addresses and control signals to the memories 106 and 107, respectively. The operation of this embodiment will be described below.

In the digital VTR of this embodiment, two fields are combined into a frame, and high-efficiency encoding is performed in units of one frame. As a highly efficient encoding method,
The data amount is controlled in a predetermined unit, and the encoding control is performed so that the data amount obtained by encoding the data for one field is の of the data amount obtained by encoding the data for one frame. Is being done. Then, FIG. 2 (a),
As shown in (b), highly efficient encoded data is
The track is divided into 12 tracks (when the number of scanning lines is 525) and 12 tracks (when the number of scanning lines is 625) and recorded on the tape.

First, the processing of the reproduced data will be described with reference to FIG.
After performing the error correction processing, the data encoded by the high-efficiency decoding circuit 9 is decoded into the original data, and the data reproduced by the memory in units of frames is input in units of fields. Output. Writing and reading of the memories 106 and 107 are alternately performed in units of one frame by switches 108 and 109. Next, a description will be given of a method for implementing slow playback in the present embodiment.

For slow reproduction, a memory 100 for error correction and memories 106 and 107 for converting frames into fields.
Is realized as a throw in field units. The frame detection circuit 102 detects that the reproduction of one frame of data has been completed based on the address information 5 output from the ID detection circuit 4, and outputs a frame switching signal 103 for each frame. The field detection circuit 104 detects that the reproduction of the data of one field, that is, 1/2 frame, has been completed based on the address information 5 output from the ID detection circuit 4, and performs a field switching signal on a field basis. 105 is output. Hereinafter, a frame detection circuit 102 and a field detection circuit 104
Will be described. The reproduced data of the first half frame is fh, and the data of the latter half frame is s.
h, the 0th field is represented by 0, and the first field is represented by 1.

FIGS. 3 and 4 show the relationship between the reproduction data from the tape, the output of the error correction memory, and the fields output to the outside in the track unit during normal reproduction and 1/4 speed slow reproduction, respectively. It is. The reproduction data from the tape is reproduced in track units and output from the memory in frame units. The frame switching signal 103 is stored in the memory 10
6, 107 and the switches 108 and 109 are control signals for switching between writing and reading of the memories 106 and 107, and the field switching signal 105 is a control signal for switching output fields from the memories 106 and 107. is there. Frame switching signal 103,
Field switching signal 105 and memories 106 and 10
7. The relationship between the switches 108 and 109 is as follows.

Frame switching signal H: Memory 106 writing L: Memory 107 reading Field switching signal H: 0th field reading L: 1st field reading First, at the time of normal reproduction, data of each track is continuously reproduced. Therefore, as shown in FIG.
03 is switched every frame period, and 10
The writing and reading of 6, 107 are performed alternately in units of one frame. Also, by switching the field switching signal 105 every field period, A0, A1,.
Fields are continuously output in the order of B0, B1 ---.

Next, at the time of slow reproduction shown in FIG. 4, since the tape speed is slow and the head traces across a plurality of tracks, data for one frame is not reproduced in one frame period. Therefore, the ID of the reproduced synchronized block
It is detected whether or not the reproduction of the data of 1 frame and 1/2 frame has been completed. The frame detection circuit 102 detects from the address information 5 that the reproduction of one frame of data has been completed, and stores the data of one frame in the memory 1.
After writing to 06, the frame switching signal 103 is set, and the switches 108 and 109 are each set to “L”. With the above settings, by causing the memory 106 and the memory control circuit 110 to perform a read operation and the memory 107 and the memory control circuit 111 to perform a write operation, data is read from the memory 106 from the next frame period.
Write data to the memory 107. For field-by-field reading, the field switching signal is set to “H” and the 0th field is repeatedly read from the memory 106 at every field period.
After it is detected at 04 that the reproduction of the data of one field of the next frame has been completed, the field switching signal is set to “L” and the first field is repeatedly read from the memory 106. Thereafter, the output frame and field are switched by the same method.

The above operation will be specifically described with reference to FIG. After all the data of the B frame is written to the memory and output to the memory, the field switching signal 105 is set to “H” until the reproduction of the data of the first half frame (Cfh) of the C frame is completed. , Memory 11
, The 0th field (B0) of the B frame is repeatedly output. Next, the field detection circuit 104
When it is detected that the reproduction of the data of fh has been completed, the field switching signal is set to “L” and B
The first field (B1) of the frame is repeatedly output from the memory. Further, it is detected by the frame detection circuit 102 that the reproduction of the data of the C frame has been completed, and after all the data of the C frame has been written into the memory 106, the data of the 0th field (C0) of the C frame is read from the memory 106. read out. FIGS. 5A and 5B show Bf recorded on the tape in the case of 525 and 625, respectively.
h and Bsh are shown.

As described above, according to the present embodiment, 1
When slow-playing data that is highly efficient coded in frame units, by detecting that the playback of one frame and one field of data has been completed, the operation of the memory that converts the frame into fields is controlled. , A field-by-field throw can be realized.

FIG. 6 is a diagram showing a configuration of a signal processing device of a digital VTR according to an embodiment of the present invention.
6, reference numeral 200 denotes a tape speed control circuit for controlling the tape speed; 201, a tape feed stop signal for stopping tape feed according to the detection result of the frame detection circuit 102; 202, tape speed information; A detection circuit 204 is a field switching signal. The operation of this embodiment will be described below.

In this embodiment, by performing the tape feed intermittently at the time of the slow reproduction, the slow reproduction is performed at a slower speed than when the tape is continuously fed. FIG. 7 shows the tape speed at the time of slow playback at 1/8 speed, the playback data from the tape in track units, the output of the error correction memory,
FIG. 3 is a diagram illustrating a relationship between fields output to the outside.
The tape speed is controlled by the tape speed control circuit 200. The tape feed is started at regular time intervals T, and the tape is fed at a quarter speed.

First, while the tape is being fed at 1/4 speed, the frame switching signal 103 and the tape feed stop signal 201 are set to "H", and the memory 106 and the memory control circuit 110 perform the writing operation and the memory 107. , The memory control circuit 111 performs a read operation. Next, the frame detection circuit 102 detects that the reproduction of the data of one frame is completed from the address information 5, and after the data of one frame is written in the memory 106, sets the frame switching signal 103 to "L". And switch 10
8 and 109 are each set to “L”. With the above settings, from the next frame period, the memory 106 and the memory control circuit 110 perform a read operation, and the memory 107 and the memory control circuit 111 perform a write operation. Here, the frame switching signal 103 is set to “L” and the tape feed stop signal 201 is set to “L”, and the tape speed control circuit 200 stops the tape feed. As for the output field, while the tape is moving at 1 / 4x speed,
The first field of the A frame is repeatedly read from the memory 107 every field period. Next, until the tape feed stops and the tape starts moving again, the memory 1
From 06, the 0th field of the B frame is repeatedly read every field period. That is, the field to be output is switched according to the field switching signal 204 created from the tape speed information 202, the first field is read while the field switching signal 204 is "L", and the first field is read while the field switching signal 202 is "H". 1
Read a field. The 0th field and the 1st field are output by setting the time T for starting the tape feeding to be about twice as long as the time required to read one frame of data when the tape is fed at 1/4 speed. It is possible to equalize the time.

As described above, according to the present embodiment, 1
When slow-reproducing data that is highly efficient coded in frame units, it is detected that the reproduction of one frame of data has been completed, and the tape feed is stopped and the tape is being fed and the tape is stopped. By switching the fields to be output with and, a throw per field can be realized.

FIG. 8 is a diagram showing the configuration of a digital VTR signal processing device according to an embodiment of the third invention.
In FIG. 8, reference numeral 300 denotes a memory for error correction, 301 denotes a memory control circuit for supplying an address and a control signal to the memory 300, and 302 detects that reproduction of one frame of data has been completed based on the address information 5. A frame detection circuit 303; a frame write signal 303; a field detection circuit 304 for detecting the end of reproduction of data for one field based on the address information 5; a field write signal 305; And 307, a memory control circuit for supplying addresses and control signals to the memory 306. The operation of this embodiment will be described below.

In the present embodiment, in order to correct an error that cannot be corrected by the error correction processing in a state where the error has been efficiently coded, Ou is corrected.
An error correction memory 300 having a capacity of one frame is provided after the ter correction memory 100. Error correction processing is realized by replacing erroneous data with corresponding data one frame before, based on a flag indicating the presence of an error. Therefore, only correct data is stored in the memory 30.
It is possible to perform error correction by writing to 0 and not writing erroneous data to the memory 300. Further, in the above-described two embodiments, two 1-frame memories are used to convert a frame into a field, and the memory is switched on a frame-by-frame basis. In this embodiment, the conversion process is performed using only the one-frame memory 302. Do.

First, the relationship between the frame write signal 303, the field write signal 305, and the operations of the memories 300 and 306 will be briefly described. Frame write signal 3
Reference numeral 03 denotes a signal for controlling writing when the output data of the memory 100 is written to the memory 300. The frame write signal 303 is switched every frame period, and when “L”, the output data of the memory 100 is written into the memory 300, and when “H”, the memory 300 is output.
Prohibits writing to. One frame of data is read from the memory 300 in one frame period regardless of the frame write signal 303. Next, a field write signal 305 is a signal for controlling writing when data obtained by efficiently decoding output data of the memory 300 is written to the memory 306. The field write signal is switched every one field period. When "L", the highly efficient decoded data is written to the memory 306, and when "H", the write to the memory 306 is prohibited. Here, with respect to the field output from the memory 306, switching is performed after the field write signal 305 is set to “L” and data for one field is written to the memory 306. That is, field switching is performed after writing data for one field.
Hereinafter, operations during normal reproduction and slow reproduction will be specifically described.

Since the data of each track is continuously reproduced during normal reproduction, the frame write signal 303 is always set to "L" as shown in FIG. Write to. Also,
The field write signal 305 is always set to "L", and the output data of the memory 300 is written to the field memory 306 via the high-efficiency decoding circuit 9, and the field to be output at the same time is switched.

Slow reproduction is realized as a field-by-field slow using the memory 100 for error correction, the memory 300 for error correction, and the memory 306 for converting a frame into a field. The frame detection circuit 302 detects that the reproduction of one frame of data has been completed based on the address information 5 output from the ID detection circuit 4, and outputs a frame write signal 303 for each frame.
Further, the field detection circuit 304 detects that the reproduction of the data of the 終了 frame has been completed based on the address information 5 output from the ID detection circuit 4, and outputs the field write signal 305 in units of one field. Output.

FIG. 10 is a diagram showing the operation of slow reproduction at 1/4 speed according to the present embodiment. Frame detection circuit 3
02, when it is detected that the reproduction of the data of the B frame is completed, the frame write signal is set to “L”, and the data of the B frame is written from the memory 100 to the memory 300. After a predetermined amount of delay, the B-frame data written to the memory 300 is read out from the memory 300 and output.
05 is set to "L" for one field period, and data of the first half frame (Bfh) of the B frame is stored in the memory 306.
Write to. After the data of Bfh is written to the memory 306, the field output from the memory 306 is switched from the 0th field (A0) of the A frame to the 1st field (A1) of the A frame. A1 is repeatedly output until it is written to 306. Next, when it is detected by the field detection circuit 303 that the reproduction of the first half frame of the C frame (Cfh) is completed, the field write signal 305 is set to “L” for one field period,
The sh data is written to the memory 306. After the Bsh data is written to the memory 306, the field output from the memory 306 is changed to the 0th field (B
Switch to 0). By repeating the above processing, a throw in a field unit can be realized.

As described above, according to this embodiment, 1
In slow reproduction of data encoded at high efficiency in frame units, it is detected that reproduction of data for one frame and one field has been completed in a state of highly efficient encoding, and a memory for error correction and By controlling the operation of the memory that converts a frame into a field, a throw per field can be realized.

FIG. 11 is a diagram showing a configuration of a signal processing device of a digital VTR according to an embodiment of the fourth invention. The operation of this embodiment will be described below.

In this embodiment, as in the embodiment shown in FIG. 8, in order to correct an error that cannot be corrected by the error correction processing in a highly efficient coded state, the outer correction memory 10 is used.
An error correction memory 300 having a capacity of one frame after 0 is provided. Then, by performing tape feeding intermittently at the time of slow playback and controlling the memories 300 and 306, slow playback is realized at a lower speed as compared with continuous tape feeding. The relationship between the operations of the frame write signal 303, the field write signal 305, and the memories 300 and 306 is the same as described above.

FIG. 12 is a diagram showing the operation at the time of slow reproduction at 1/8 speed. Tape speed control circuit 2
00, the tape feeding is started at regular time intervals T, and the speed is 1/4 speed in a steady state. While the tape is being sent at 1/4 speed, the data of the latter half frame (Bsh) of the B frame is reproduced, and the frame write signal 303, the field write signal 305, and the tape feed stop signal 401 become "H". A is set, and the A frame data is repeatedly output from the memory 300. Next, in the frame detection circuit 302, the address information 5
It is detected that the reproduction of the sh data has been completed, that is, the reproduction of the data of the B frame has been completed, and the frame write signal 303 is set to “L”.
The frame data is written into the memory 300. Memory 3
After a predetermined amount of delay, the data of the B frame written in 00 is read out from the memory 300 and output.
L ”, and the first half of the B frame (Bf
Write the data of h) into the memory 306. Here, the frame write signal 303 is set to “L” and the tape feed stop signal 201 is set to “L” at the same time, and the tape feed is stopped by the tape speed control circuit 200. Therefore, during this time, the data (Cfh) of the first half frame of the C frame is reproduced from the tape. Regarding the fields to be output, the 0th field of the A frame is repeatedly read from the memory 306 every field period while the tape is moving at 1/4 speed. Next, the first field of the A frame is repeatedly read from the memory 306 every field period until the tape feeding stops and the tape starts moving again. That is, the field write signal 305 generated from the tape speed information 202
The field to be output is switched in response to the condition (1). Specifically, the field to be output is switched after the field write signal 305 is set to “L” and １ ／ frame data is written to the memory 306. The time T at which the tape feed is started is set to about 2 times the time required to read one frame of data when the tape is fed at 1/4 speed.
By setting it to twice, it is possible to equalize the time for outputting the 0th field and the first field.

As described above, according to the present embodiment, 1
In slow reproduction of high-efficiency coded data in frame units, it is detected that the reproduction of one frame of data has been completed, the tape feed is stopped, and the period during which the tape is being transmitted and the tape are stopped. By switching the fields to be output depending on the period, and simultaneously controlling the operations of the memory for error correction and the memory for converting the frames into fields, it is possible to realize a throw in units of fields. This embodiment is particularly effective when it is difficult to feed the tape at a low speed.

In the above embodiment, the tape feed is in the forward direction, and the fields are A0, A1, B0, and B1-.
---, but are output to the outside in the order of B1, B0, A1, A0 ---- in reverse reproduction. However, since data is written to the memories 107, 108, and 306 in units of one frame and output to the outside in units of fields, B0, B1, A0, and A1 despite reverse playback. -Data is played in the order of. Therefore, in order to change the output order of the field corresponding to one frame at the time of the reverse reproduction, the information of the tape feed direction is sent to the memory control circuits 110, 111, and 307 to change the reading order of the output field. It is also possible to output the fields in the correct order even during reverse reproduction.

Further, in the above-described embodiment, a configuration is described in which a frame is first formed from two-field data and then high-efficiency coding is performed.

[0045]

As described above, according to the present invention, it is possible to realize field slow reproduction in a digital VTR for recording and reproducing data which has been encoded with high efficiency in units of a plurality of fields. The effect is great.

[Brief description of the drawings]

FIG. 1 is a digital VTR according to an embodiment of the present invention;
Block diagram showing the configuration of the signal processing device of FIG.

FIG. 2 shows a method of dividing highly efficient coded data into 10 tracks (when the number of scanning lines is 525) and 12 tracks (when the number of scanning lines is 625) and recording the data on a tape. Illustrated illustration

FIG. 3 is an explanatory diagram showing a relationship between reproduction data from a tape in a track unit, output of an error correction memory, and fields output to the outside in a normal reproduction according to the first invention;

FIG. 4 is an explanatory diagram showing a relationship between reproduction data from a tape, an output of an error correction memory, and a field output to the outside in a track unit at the time of 1/4 speed slow reproduction according to the first invention;

FIG. 5 is an explanatory diagram showing data corresponding to Bfh and Bsh recorded on a tape when the number of scanning lines is 525 and 625;

FIG. 6 is a digital VTR of one embodiment according to the second invention;
Block diagram showing the configuration of the signal processing device of FIG.

FIG. 7 shows a tape speed at the time of 1/8 × speed slow reproduction according to the second invention, reproduction data from a tape in track units,
Explanatory diagram showing the relationship between the output of the error correction memory and the field output to the outside

FIG. 8 is a digital VTR according to an embodiment of the third invention;
Block diagram showing the configuration of the signal processing device of FIG.

FIG. 9 is an explanatory diagram showing a relationship between reproduction data from a tape in a track unit, an output of an error correction memory, and fields output to the outside in a normal reproduction according to the third invention.

FIG. 10 is an explanatory diagram showing a relationship between reproduction data from a tape, an output of an error correction memory, and a field output to the outside in a track unit at the time of 1/4 speed slow reproduction according to the third invention.

FIG. 11 is a digital VT of one embodiment according to the fourth invention;
The block diagram which showed the structure of the signal processing apparatus of R.

FIG. 12 is an explanatory diagram showing a relationship between reproduction data from a tape, an output of an error correction memory, and a field output to the outside in a track unit at the time of 1/8 speed slow reproduction according to the fourth invention.

FIG. 13 is a block diagram showing a configuration of a conventional digital VTR reproduction signal processing device.

FIG. 14 is an explanatory diagram showing the configuration of a synchronization block and the direction of Outer correction.

[Explanation of symbols]

100 Rearrangement memory for Outer 102 Frame detection circuit 103 Frame switching signal 104 Field detection circuit 105 204 Field switching signal 106, 107 Memory for converting frames into fields 108, 109 Switches 110, 111 Memory control circuit 200 Tape speed control circuit 202 Tape Speed information 300 Error correction memory 301 Memory control circuit 302 Frame detection circuit 303 Frame write signal 304 Field detection circuit 305 Field write signal 306 Memory for converting frame to field 307 Memory control circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/91-5/956 G11B 20/12 103 H04N 9/79-9/898

Claims (10)

(57) [Claims] 1. In a digital VTR in which data of high efficiency encoding is divided into n tracks and recorded in units of one page with m fields as one page, reproduction of the data of one page is completed. A page detecting means for detecting that the reproduction of the data of one field of the one page is completed, and a first detecting means for storing the reproduced data and performing the error correction processing. A memory, high-efficiency decoding means for performing high-efficiency decoding on the output of the first memory, and a second unit for converting the high-efficiency decoded data in units of one page into data in units of fields and outputting the data. A second memory, page switching means for switching between writing and reading pages of the second memory in accordance with a detection result of the page detecting means, and Detecting means for detecting result signal processing apparatus in a digital VTR which is characterized in that a field switching means for switching the fields to be output by controlling reading of the second memory in response to. 2. The digital VTR signal processing device according to claim 1, wherein the page detecting means detects that the reproduction of the data of the n tracks has been completed. 3. The digital VTR signal processing device according to claim 1, wherein the field detecting means detects that the reproduction of the data of (n / m) tracks has been completed. 4. In a digital VTR in which data of high efficiency coding is divided into n tracks and recorded in units of one page with m fields as one page, tape feeding is started at regular intervals and the tape is started. Speed control means for sending the tape at a speed slower than during normal reproduction, and stopping tape feeding when reproduction of (2 / m) pages of the one page is completed; and data for the one page. Page detection means for detecting that the reproduction of the data has been completed, a first memory for storing the reproduced data and performing an error correction process, and a high-performance decoder for performing high-efficiency decoding on the output of the first memory. Efficiency decoding means, a second memory for converting the high-efficiency decoded data in units of one page into data in units of fields, and outputting the data, and a previous memory according to a detection result in the page detection means. Page switching means for switching between writing and reading pages of the second memory, and field switching means for switching reading and outputting fields of the second memory in accordance with a tape speed by the tape speed control means. A signal processing device for a digital VTR. 5. The signal processing device of a digital VTR according to claim 4, wherein the page detecting means detects that the reproduction of the data of n tracks has been completed. 6. A digital VTR in which high-efficiency coded data is divided into n tracks and recorded in units of one page with m fields as one page, and reproduction of the data of one page is completed. A page detecting means for detecting that the reproduction of the data of one field of the one page is completed, and a first detecting means for storing the reproduced data and performing the error correction processing. A memory, a second memory for correcting data that cannot be corrected by the error correction processing, a high-efficiency decoding means for performing high-efficiency decoding on an output of the second memory, and the high-efficiency decoding A third memory for converting the converted data in units of one page into data in units of fields and outputting the data, and controlling the second memory in accordance with a detection result of the page detection means. And first control means, the detection result signal processing apparatus in a digital VTR which is characterized in that a second control means for switching the fields to be printed and controlling said third memory in response to said field detection means. 7. The digital VTR signal processing device according to claim 6, wherein the page detection means detects that the reproduction of the data of the n tracks has been completed. 8. The digital VTR signal processing apparatus according to claim 6, wherein the field detection means detects that the reproduction of the data of (n / m) tracks has been completed. 9. In a digital VTR in which data of high efficiency coding is divided into n tracks and recorded in units of one page with m fields as one page, tape feeding is started at regular intervals and the tape is started. Speed control means for sending the tape at a speed slower than during normal reproduction, and stopping tape feeding when reproduction of (2 / m) pages of the one page is completed; and data for the one page. Page detection means for detecting that the reproduction of the data has been completed, a first memory for storing the reproduced data and performing error correction processing, and a second memory for correcting data which cannot be corrected by the error correction processing. A memory, high-efficiency decoding means for performing high-efficiency decoding on the output of the first memory, and converting the high-efficiency decoded data in units of one page into data in fields and outputting the converted data A third memory, a first controller for controlling the second memory according to a detection result of the page detector, and a third memory for controlling the third memory according to a tape speed by the tape speed controller. And a second control means for switching a field to be output. 10. The digital VTR signal processing apparatus according to claim 9, wherein the page detection means detects that the reproduction of the data of the n tracks has been completed.