JPH0722938A - Bipolar cmos logic circuit - Google Patents

Abstract

PURPOSE:To provide a high speed and compact logic circuit whose noise margin is large by constituting a three-input NOR circuit of three bipolar transistors, P-channel type MOS transistor, N-channel type MOS transistor, and resistance. CONSTITUTION:A bipolar CMOS logic circuit is the three-input NOR circuit constituted of three bipolar transistors(TR) T1, T2, and T3, P-channel type MOSTRP1, N channel type MOSTRN1, and resistance, R1. An output block 2 is constituted of the CMOSTR, so that the voltage of an output terminal Y can full-swing to a power supply voltage. Also, even when the gate width of the MOSTRP1 and N1 of the output block 2 is increased in order to improve a load driving capability, an input capacitor is hardly increased. Moreover, the input capacity of an input block 1 being an emitter-follower is small, and the load capacity viewed from a gate at a preceding stage is small.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a bipolar CMOS (B
(ICMOS) logic circuit.

2. Description of the Related Art FIG. 6 shows a conventional CMOS logic circuit inverter. In such a CMOS logic circuit, the voltage of the output terminal Y fully swings to the power supply voltage, but in order to improve the load driving capability, the gate width W of the P-channel MOS transistor P and the N-channel MOS transistor N is increased. There is a need. However, there is a drawback that the input capacitance viewed from the input terminal A increases when the gate width is increased.

Therefore, as shown in FIG. 7, an inverter of a BICMOS logic circuit has been devised in which two bipolar transistors are connected after the CMOS inverter. In this conventional BICMOS logic circuit, the input block 13
Uses MOS transistors P and N for the output block 2
1 uses bipolar transistors T ₁₀ and T ₂₀ .

[0003]

DISCLOSURE OF THE INVENTION The conventional BIC described above
In the MOS logic circuit, the load driving capability is large, but the voltage at the output terminal Y is lowered by the base-emitter voltage V _BE of the bipolar transistor T ₁₀ and is vulnerable to noise.

[0004]

Bipolar CM of the present invention
The OS logic circuit has one or more NPN-type bipolar transistors, each base of the bipolar transistors is used as an input terminal, the collector of the bipolar transistor is connected to a power supply, and the emitters of the bipolar transistors are commonly used. An input block that is connected and connected to the ground via a resistor, and uses the commonly connected emitter as an output node,

The drains of a P-type MOS transistor and an N-type MOS transistor are connected to serve as an output terminal, and a P-type MO transistor is provided.
The source of the S transistor is connected to the power source, the source of the N-type MOS transistor is connected to the ground, and the gates of both MOS transistors are connected to each other to have an output block as an input node. It is configured by connecting to the input node of the block.

[0006]

Referring to Figure 1 showing a first embodiment of the embodiment of the present invention, this embodiment three bipolar transistors T _1, T
₂ and T ₃ and P-channel MOS transistor P ₁
, An N-channel type MOS transistor N ₁ and a resistor R ₁
It is a 3-input NOR circuit composed of and. A ₁ , A ₂ and A ₃ are input terminals, and Y is an output terminal.

In this embodiment, since the output block 2 is composed of CMOS, the voltage at the output terminal Y fully swings to the power supply voltage. In addition, in order to improve the load drive capacity,
Even if the gate width of the MOS transistors P ₁ and N ₁ of the output block 2 is increased, the input capacitance hardly increases. Moreover, since the input block 1 is an emitter follower, the input capacitance is small and the load capacitance seen from the gate in the previous stage is small.

FIG. 2 shows a second embodiment of the present invention. In the 3-input NOR circuit shown in FIG. 1, a P-channel type MOS transistor P ₂ and an N-channel type MOS transistor N _{2 are provided.}
Is added with a CMOS inverter 3.
In order to improve the additional drive capability, the gate width W of the MOS transistors P ₁ and N ₁ forming the output block 2 may be increased.

FIG. 3 shows a third embodiment of the present invention, in which a latch circuit 4 is provided between two input blocks 10 and 11 each consisting of one bipolar transistor and an output block 2. Has become. As in the circuits of FIGS. 1 and 2, NPN type bipolar transistors are used for the input blocks 10 and 11 to reduce the input capacitance, and MOS transistors are used for the output block 2 so that the voltage at the output terminal Y reaches the power supply voltage. It is designed to swing.

FIG. 4 shows a NOR-N according to the fourth embodiment of the present invention.
It is an AND circuit, and its equivalent circuit is as shown in FIG.
In this circuit, the output block 20 also serves as a logic block, and a 2-input NAND is used instead of an inverter as shown in FIGS.
Has become.

[0011]

As described above, in the bipolar MOS logic circuit of the present invention, even if the load driving capability is improved, the input capacitance does not increase, and the output voltage fully swings to the power supply voltage. As a result, there is an effect that a high-speed, small-sized logic circuit having a large noise margin can be configured.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a fourth embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of FIG.

FIG. 6 is a circuit diagram of a conventional CMOS inverter circuit.

FIG. 7 is a circuit diagram of a conventional BICMOS inverter circuit.

[Explanation of symbols]

1, 11, 12, 13 Input block ₂ , ₂₀ , 21 Output block 3 CMOS inverter 4 Latch circuit T ₁ , T ₂ , T ₃ , T ₁₀ , T ₂₀ Bipolar transistor A, A ₁ , A ₂ , A ₃ , A Input terminals P ₁ , P ₂ , P P channel type MOS transistors N ₁ , N ₂ , N N channel type MOS transistors Y Output terminals R ₁ , R resistance

Claims (2)

[Claims] 1. A bipolar transistor of one or more NPN type, each base of the bipolar transistor is used as an input terminal, a collector of the bipolar transistor is connected to a power source, and an emitter of each of the bipolar transistors is commonly used. Connect and connect to the ground through a resistor,
The input block having the commonly connected emitter as an output node, the drains of the P-type MOS transistor and the N-type MOS transistor are connected as an output terminal, and the source of the P-type MOS transistor serves as a power source and the source of the N-type MOS transistor. Is connected to the ground and the gates of both MOS transistors are connected to each other to serve as an input node, and the output node of the input block and the input node of the output block are connected to each other. Logic circuit. 2. One or more P-type MOS transistors and N-type MOs between the input block and the output block.
2. A bipolar CO according to claim 1, wherein a logic block constituted by S transistors is interposed.
MS logic circuit.