JP2783464B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit using bipolar CMOS circuit technology, and more particularly to a semiconductor integrated circuit for realizing a reduced delay time.

[0002]

2. Description of the Related Art FIG. 6 shows an example of an exclusive OR circuit constituted by a conventional CMOS circuit technology. In FIG. 6, reference numerals 601 to 603 denote P-channel MOSFETs and 604 to 60
6 is an N-channel MOSFET, 607 is a first input point,
608 is a second input point and 609 is an output point.

The operation of the conventional exclusive OR circuit will be described below. First, when both the first input point 607 and the second input point 608 are at "L" level, all the P-channel MOSFETs 601 to 603 are turned on, while all the N-channel MOSFETs 604 to 606 are turned off. Therefore, the “L” level signal at the first input point 607 is simultaneously passed through the P-channel MOSFET 602 to the second
"L" level signal at input point 608 of P channel MO
The output point 609 is set to the “L” level through the SFET 603. Next, when the first input point 607 is at “L” level and the second input point 608 is at “H” level, the P-channel MO
Since the SFET 603 and the N-channel MOSFET 604 are conducting, while the P-channel MOSFETs 601 and 602 and the N-channel MOSFETs 605 and 606 are non-conducting, the "H" level signal at the second input point 608 is output through the P-channel MOSFET 603. 609 to “H” level. Also, the first input point 607 is "H".
Level, when the second input point 608 is at the “L” level,
P-channel MOSFETs 601 and 602 and N-channel MOSFETs 605 and 606 become conductive, while P-channel MOSFET 603 and N-channel MOSFET
Since the 604 is turned off, the "H" level signal of the first input point 607 is output through the P-channel MOSFET 602 and the N-channel MOSFET 605 to the output point 609.
To the “H” level. At this time, the current flowing when the P-channel MOSFET 601 is turned on at the same time also outputs the output point 60 through the N-channel MOSFET 606.
9 works to the “H” level. Further, when both the first input point 607 and the second input point 608 are at "H" level, the N-channel MOSFETs 604 and 606 become conductive, while all the P-channel MOSFETs 60
1 to 603 and the N-channel MOSFET 605 are turned off, so that the output point 609 becomes the N-channel MOSFET.
Conduction with the ground line through T606 and further through N-channel MOSFET 604 brings the level to "L" level.

As described above, the exclusive OR circuit of the conventional configuration requires a minimum of 6 transistors, thereby reducing the delay time. However, since the configuration of the output section is connected to the output via the MOSFET, or the input is directly connected to the output via the MOSFET, sufficient driving cannot be performed when the load on the output section is heavy. . Therefore, the configuration of the logic circuit requires a driving circuit unit in addition to the logic forming circuit unit in order to obtain sufficient driving capability. For this reason, an extra delay time is added, and the conventional circuit cannot always be said to be a circuit that has achieved a reduction in the delay time.

[0005]

As described above, in the conventional circuit, the configuration of the output section is connected to the output via the MOSFET, or the input is directly connected to the output via the MOSFET. When the load of the output unit is heavy, sufficient driving capability cannot be obtained. In order to obtain sufficient driving capability, the configuration of the logic circuit requires a driving circuit unit in addition to the logic forming circuit unit, so an extra delay time is added and a large delay time is required. Would.

The present invention solves the above problems,
It is an object of the present invention to provide a semiconductor integrated circuit which has a sufficient driving capability and does not require a driving circuit portion, so that an extra delay time is not added and a high-speed exclusive OR circuit can be formed. It is.

[0007]

In order to solve the above-mentioned problems, a first semiconductor integrated circuit according to the present invention comprises first and second P-type integrated circuits.
Channel MOSFET and first and second N-channel M
An OSFET, first and second NPN bipolar transistors and a resistor, wherein the second P-channel MOSF
The gate of the ET, the gate of the second N-channel MOSFET, and the source of the first P-channel MOSFET are commonly connected and used as a first input point, while the gate of the first P-channel MOSFET and the The gate of one N-channel MOSFET and the second P-channel MOSFET
The sources of the channel MOSFETs are commonly connected to each other and used as a second input point.
FET drain and the first N-channel MOSFET
The drain of T and the base of the first NPN bipolar transistor are commonly connected, and the drain of the second P-channel MOSFET is connected to the second N-channel MOSFET.
The drain of the SFET and the base of the second NPN bipolar transistor are commonly connected, the sources of the first and second N-channel MOSFETs are connected to a ground line, and both the first and second NPN bipolar transistors are connected. A collector is connected to a power supply line, and the first and second NPNs are connected.
Both emitters of the bipolar transistor are commonly connected to one end of the resistor, and this is used as an output point, and the other end of the resistor is connected to a ground line.

Further, a second semiconductor integrated circuit according to the present invention comprises:
The first semiconductor integrated circuit and the inverter circuit;
And an input point of the inverter circuit and an output point of the third semiconductor integrated circuit.
And the drain of the P-channel MOSFET is connected in common, the output point of the inverter circuit is connected to the gate of the third P-channel MOSFET, and the source of the third P-channel MOSFET is connected to a power supply line. It is a thing.

Further, a third semiconductor integrated circuit of the present invention comprises:
A first P-channel MOSFET having first to fourth P-channel MOSFETs, first to fourth N-channel MOSFETs, NPN bipolar transistors and resistors;
FET gate and first N-channel MOSFET
Is commonly connected to the source of the second N-channel MOSFET and used as a first input point. The gate of the second P-channel MOSFET and the gate of the second N-channel MOSFET are connected to the first N-channel MOSFET. The source of the N-channel MOSFET is connected in common and used as a second input point, and the drain of the first P-channel MOSFET, the drain of the first N-channel MOSFET, the gate of the third P-channel MOSFET and The gates of the third N-channel MOSFET are commonly connected, and the drain of the second P-channel MOSFET, the drain of the second N-channel MOSFET, the gate of the fourth P-channel MOSFET, and the fourth N-channel MOSFET The gates of the MOSFETs are commonly connected, and the first to The source of the P-channel MOSFET and the collector of the NPN bipolar transistor are commonly connected to a power supply line, and the drains of the third and fourth P-channel MOSFETs are connected to the base of the bipolar transistor and one end of the resistor. The other end of the resistor, the drain of the third N-channel MOSFET and the emitter of the NPN bipolar transistor are connected in common and set as an output point, and the source of the third N-channel MOSFET and the fourth N-channel MOSFET are connected.
It has a configuration in which the drain of the SFET is connected and the source of the fourth N-channel MOSFET is connected to a ground line.

Further, a fourth semiconductor integrated circuit of the present invention has first to fourth P-channel MOSFETs, first to fourth N-channel MOSFETs, first to third NPN bipolar transistors, and resistors. , The first P
The source of the channel MOSFET, the gate of the second P-channel MOSFET, and the gate of the second N-channel MOSFET are commonly connected and used as a first input point, and the source of the second P-channel MOSFET and the second A gate of the first P-channel MOSFET and a gate of the first N-channel MOSFET which are commonly connected to each other as a second input point, and a drain of the first P-channel MOSFET and a drain of the first N-channel MOSFET are connected to each other. A drain, a gate of the third P-channel MOSFET, and a third N-channel MOS
The gate of the FET and the base of the first NPN bipolar transistor are commonly connected, and the drain of the second P-channel MOSFET and the second N-channel M
OSFET drain and the fourth P-channel MOS
FET gate and fourth N-channel MOSFET
And the base of the second NPN bipolar transistor are connected in common, and the first and second NP
Both emitters of the N bipolar transistor and the third P
The source of the channel MOSFET is connected to the collector of the third NPN bipolar transistor and one end of the resistor to serve as an output point. The drain of the third P-channel MOSFET and the source of the fourth P-channel MOSFET are connected. And the drains of the fourth P-channel MOSFET, the drains of the third and fourth N-channel MOSFETs, and the third NPN
A common connection with a base of the bipolar transistor, a collector of the first and second NPN bipolar transistors connected to a power supply line, and a first to a fourth N-channel MOS
A structure is provided in which the source of the FET and the other end of the resistor are commonly connected to a ground line.

A fifth semiconductor integrated circuit according to the present invention comprises:
The fourth semiconductor integrated circuit, the inverter circuit, and the fifth
The input point of the inverter circuit and the drain of the fifth P-channel MOSFET are commonly connected to the output point of the fourth semiconductor integrated circuit, and the output point of the inverter circuit is connected to the The fifth P-channel MOSFET is connected to the gate thereof, and the source of the fifth P-channel MOSFET is connected to a power supply line.

[0012]

As described above, a bipolar CMO comprising both a CMOSFET and a bipolar transistor capable of obtaining a large amount of output current by supplying a small amount of current.
Using S circuit technology, exclusive OR logic is MOSFET
And a bipolar transistor, and the output section is driven by the bipolar transistor used to form the logic.This eliminates the need for an extra drive circuit section and allows the conventional circuit to be used even when the load on the output section is heavy. It is possible to reduce the delay time as compared with Further, in the second semiconductor integrated circuit, the third semiconductor integrated circuit, and the fifth semiconductor integrated circuit, when the power supply potential is 5 V, the logical amplitude can swing from 0 V to 5 V in full swing. Hard to receive.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention (corresponding to claim 1).
3 is a circuit diagram of the semiconductor integrated circuit of FIG. In FIG. 1, 101
, 102 are P-channel MOSFETs and 103, 104 are N-channel MOSFETs.
Channel MOSFETs, 105 and 106 are NPN bipolar transistors, 107 is a resistor, 108 is a first input point, 10
Reference numeral 9 denotes a second input point, 110 denotes an output point, and the source of the first P-channel MOSFET 101, the gate of the second P-channel MOSFET 102, and the second N-channel MOSFET
The gate of the FET 104 is commonly connected to a first input point 108, and the source of the second P-channel MOSFET 102, the gate of the first P-channel MOSFET 101 and the first N
The gate of the channel MOSFET 103 is commonly connected to the second input point 109, and the first P-channel MOSFET
101 drain and first N-channel MOSFET 103
Are connected to the base of a first NPN bipolar transistor 105, and a second P-channel MOS
FET 102 drain and second N-channel MOSFET
The drain of T104 is connected to the base of a second NPN bipolar transistor 106, the sources of the first and second N-channel MOSFETs 103 and 104 are both grounded, and the first and second NPN bipolar transistors 105 and
The collector of the transistor 106 is connected to the power supply line, and the emitters of the first and second NPN bipolar transistors 105 and 106 are both connected to the output point 110 and grounded via the resistor 107. Here, the first and second input points 108 and 109 are both positive logic input points.

The operation of the semiconductor integrated circuit shown in FIG. 1 will be described below. When both the first input point 108 and the second input point 109 are at "L" level, the P-channel MOSF
ET101 and 102 are both conductive, while N-channel MOSFETs 103 and 104 are both nonconductive. However, since the first input point 108 is at "L" level, NPN
No current is supplied to the base of the bipolar transistor 105 through the P-channel MOSFET 101. Also, since the second input point 109 is also at the “L” level, NPN
No current is supplied to the base of the bipolar transistor 106 through the P-channel MOSFET 102. Therefore, the emitter current does not flow through both NPN bipolar transistors 105 and 106, and the potential at output point 110 becomes "L" level through resistor 107.

Next, when the first input point 108 is at the "L" level,
When the second input point 109 is at "H" level, the P-channel MOSFET 102 and the N-channel MOSFET 1
03 is conducting, while P-channel MOSFET1
Since the 01 and the N-channel MOSFET 104 are turned off, the base potential of the NPN bipolar transistor 105 becomes "L" level through the N-channel MOSFET 103, and no current is supplied. On the other hand, since the second input point 109 is at "H" level, the P-channel MOSFET 102 is connected to the base of the NPN bipolar transistor 106.
Current is supplied through the transistor, the emitter current flows, and the output point
110 is set to “H” level.

When the first input point 108 is at "H" level,
When the second input point 109 is at "L" level, the P-channel MOSFET 101 and the N-channel MOSFET 1
04 is conducting, while P-channel MOSFET1
Since the N.sub.02 and the N-channel MOSFET 103 are turned off, the base potential of the NPN bipolar transistor 106 becomes "L" level through the N-channel MOSFET 104, and no current is supplied. On the other hand, the P-channel MOSFET 101 is connected to the base of the NPN bipolar transistor 105 because the first input point 109 is at "H" level.
Current is supplied through the transistor, the emitter current flows, and the output point
110 is set to “H” level.

Further, a first input point 108 and a second input point
109 are both at “H” level, N channel M
OSFETs 103 and 104 are both conducting, while PFET
Since the channel MOSFETs 101 and 102 are both turned off, the base potential of the NPN bipolar transistor 105 is set to “L” through the N-channel MOSFET 103.
Level and no current is supplied. Similarly, the base potential of NPN bipolar transistor 106 is N-channel MO
It goes to "L" level through SFET 104, and no current is supplied. Therefore, the NPN bipolar transistor 105,
The emitter current does not flow in either case, and the potential at the output point 110 becomes “L” level through the resistor 107.

By using one of the first input point and the second input point shown in FIG. 1 as a negative logic input point, the negation of the exclusive OR can be indicated.
Also, in FIG. 1, a first P-channel MOSFET
A third input point is connected by using a third N-channel MOSFET in place of 101, and the gate of the third N-channel MOSFET is used alone as an input of an inverted signal of the signal input to the second input point 109. And a fourth N-channel MO instead of the second P-channel MOSFET 102.
This fourth N-channel MO is connected using an SFET.
The same result can be obtained even when the gate of the SFET is used alone as the fourth input point which receives the inverted signal of the signal input to the first input point 108. Also, at this time, by using either the first input point or the second input point as a negative logic input point, it is possible to indicate the negation of the exclusive OR.

As described above, in the semiconductor integrated circuit of the first embodiment, the exclusive OR logic is constituted by the MOSFET and the bipolar transistor by using the bipolar CMOS circuit technology, and the output section is driven by the bipolar transistor. With this configuration, the delay time can be reduced as compared with a conventional circuit even when the load on the output unit is heavy.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment (corresponding to claim 3) of the present invention. In FIG. 2, 101 to 110 are the same as those described in the first embodiment. Therefore, detailed description is omitted. In FIG. 2, 201
Is an inverter circuit, 202 is a P-channel MOSFET, and the output point 110 is connected to the input point of the
The output point of the inverter circuit 201 is connected to the gate of the third P-channel MOSFET 202, and the source of the third P-channel MOSFET 202 is connected to the power supply line.

The operation of the semiconductor integrated circuit shown in FIG. 2 will be described below. The operation principle of the present embodiment is basically the same as the operation of the semiconductor integrated circuit of FIG. 1 already described in the first embodiment, and therefore only its features will be described.

When the first input point 108 is at the "L" level and the second input point 109 is at the "H" level, or the first input point 108 is at the "H" level and the second input point 109 is at the "H" level. Is at the "L" level, the output point 110 is at the "H" level as described above. However, in the semiconductor integrated circuit of the first embodiment, the "H" level potential in this case rises only to a level lower than the power supply potential by the potential difference between the base and the emitter in the NPN bipolar transistor. On the other hand, in the semiconductor integrated circuit of the second embodiment, the output point
When the level of the signal 110 becomes "H" to some extent, the inverter circuit 20
1 is a P-channel MOS
P-channel MOSFET given to the gate of FET202
Since 202 is conductive, the output point 110 rises to a potential equal to the power supply potential.

As described above, the semiconductor integrated circuit of the second embodiment uses the bipolar CMOS circuit technology to form logic with a very small number of transistors, so that the delay time inside the circuit can be reduced. In addition, when the power supply potential is 5 V, the logical amplitude can swing from 0 V to 5 V in full swing, so that it is hardly affected by noise or the like.

It is to be noted that the second embodiment can be applied to the modification described in the first embodiment. FIG.
FIG. 9 is a circuit diagram of a semiconductor integrated circuit according to a third embodiment (corresponding to claim 4) of the present invention. In FIG. 3, 301 to 304 are P
Channel MOSFETs 305 to 308 are N-channel M
OSFET, 309 is NPN bipolar transistor, 31
0 is a resistor for extracting the base charge of the NPN bipolar transistor 309, 311 is a first input point, 312 is a second input point, 313 is an output point, and a first P-channel MOS
The gate of FET301 and the first N-channel MOSFET
The gate of the second N-channel MOSFET 306 and the source of the second N-channel MOSFET 306 are commonly connected to the first input point 311, and the gate of the second P-channel MOSFET 302 and the second N-channel MOSFET
The gate of the channel MOSFET 306 and the source of the first N-channel MOSFET 305 are commonly connected to the second input point 31.
2 and a first P-channel MOSFET
301 drain and first N-channel MOSFET 305
, The gate of the third P-channel MOSFET 303 and the gate of the third N-channel MOSFET 307 are connected in common, and the second P-channel MOSFET 302
, The drain of the second N-channel MOSFET 306, the gate of the fourth P-channel MOSFET 304, and the gate of the fourth N-channel MOSFET 308 are commonly connected.
1 to 304 source and NPN bipolar transistor 309
Is connected to the power supply line, and the drains of the third and fourth P-channel MOSFETs 303 and 304 and NP
The base of the N bipolar transistor 309 and one end of the resistor 310 are connected together, and the other end of the resistor 310 and the third N
The drain of the channel MOSFET 307 and the emitter of the NPN bipolar transistor are commonly connected to the output point 313, the source of the third N-channel NOSFET 307 and the drain of the fourth N-channel MOSFET 308 are connected, and the source of the fourth N-channel MOSFET 308 is Grounded.

The operation of the semiconductor integrated circuit shown in FIG. 3 will be described below. When both the first input point 311 and the second input point 312 are at "L" level, the P-channel MOSF
ET301,302 and N-channel MOSFET307,
308 is conducting while the P-channel MOSFET
303 and 304 and N-channel MOSFETs 305 and 306
Becomes non-conductive. Therefore, the base of the NPN bipolar transistor 309 is a P-channel MOSFET.
No current is supplied through either 303 or 304. Therefore, the base potential of NPN bipolar transistor 309 is equal to resistance 310 and N-channel MOSFET 307,
It goes to the “L” level through 308. At the same time, the potential of the output point 313 also becomes "L" level through the N-channel MOSFETs 307 and 308, so that no emitter current flows and the output point 31
3 is kept at “L” level.

Next, when the first input point 311 is at the "L" level,
When the second input point 312 is at the "H" level, the P-channel MOSFETs 301 and 304 and the N-channel M
OSFETs 306 and 307 become conductive, while P-channel MOSFETs 302 and 303 and N-channel MOS
FETs 305 and 308 are turned off. Therefore, NPN
Since current is supplied to the base of the bipolar transistor 309 through the P-channel MOSFET 304, an emitter current flows, and the output point 313 is set to "H" level. At this time, the output point 313 is a P-channel MOSFET
It goes up to the supply voltage through 304 and resistor 310. The base potential is in a non-conductive state with the ground line by the N-channel MOSFET 308.

When the first input point 311 is at "H" level,
When the second input point 312 is at "L" level, the P-channel MOSFETs 302 and 303 and the N-channel M
OSFETs 305 and 308 become conductive while P-channel MOSFETs 301 and 304 and N-channel MOS
The FETs 306 and 307 are turned off. Therefore, NPN
Since current is supplied to the base of the bipolar transistor 309 through the P-channel MOSFET 303, an emitter current flows, and the output point 313 is set to "H" level. At this time, the output point 313 is a P-channel MOSFET
It rises to the supply voltage through 303 and resistor 310. The base potential is in a non-conductive state with the ground line by the N-channel MOSFET 307.

Further, a first input point 311 and a second input point 311
When both 312 are at "H" level, all N-channel MOSFETs 305 to 308 are conductive, while all P-channel MOSFETs 301 to 304 are non-conductive. Therefore, no current is supplied to the base of the NPN bipolar transistor 309 through any of the P-channel MOSFETs 303 and 304. Therefore, the base potential of the NPN bipolar transistor 309 becomes "L" through the resistor 310 and the N-channel MOSFETs 307 and 308.
Level. At the same time, the potential at the output point 313 also goes to "L" level through the N-channel MOSFETs 307 and 308, so that no emitter current flows and the output point 313 is kept at "L" level.

The use of either the first input point 311 or the second input point 312 shown in FIG. 3 as a negative logic input point can indicate the negation of the exclusive OR.

As described above, in the semiconductor integrated circuit according to the third embodiment, the logic of the exclusive OR is constituted by the MOSFET and the bipolar transistor using the bipolar CMOS circuit technology, and the output section is driven by the bipolar transistor. By adopting the configuration, even when the load of the output unit is heavy, the delay time can be reduced compared to the conventional circuit,
In addition, when the power supply potential is 5 V, the logical amplitude can fully swing from 0 V to 5 V, so that it is hardly affected by noise or the like.

FIG. 4 is a circuit diagram of a semiconductor integrated circuit according to a fourth embodiment (corresponding to claim 5) of the present invention. 4, 401 to 404 are P-channel MOSFETs, and 405 to 40
8 is an N-channel MOSFET 409 to 411 is an NPN bipolar transistor, 412 is a resistor, 413 is a first input point, 414 is a second input point, 415 is an output point, and the source of the first P-channel MOSFET 401 and the second The gate of the P-channel MOSFET 402 and the gate of the second N-channel MOSFET 406 are commonly used as the first input point 413.
, The source of the second P-channel MOSFET 402, the gate of the first P-channel MOSFET 401, and the gate of the first N-channel MOSFET 405 are commonly connected to the second input point 414, and the first P-channel MOSFET
Drain of SFET 401 and first N-channel MOSF
ET405 drain and third P-channel MOSFET
Both the gate of 403 and the gate of the third N-channel MOSFET 407 are connected to the base of the first NPN bipolar transistor 409, and the second P-channel MOSFET
OSFET 402 drain and second N-channel MOS
The drain of the FET 406 and the fourth P-channel MOSFET
The gate of T404 and the fourth N-channel MOSFET 408
Are both second NPN bipolar transistors
410, and the emitters of the first and second NPN bipolar transistors 409 and 410 and the third PPN transistor.
The source of the channel MOSFET 403, the collector of the third NPN bipolar transistor 411, and one end of the resistor 412 are commonly connected to the output point 415, and the drain of the third P-channel MOSFET 403 is connected to the source of the fourth P-channel MOSFET 404. The drain of the fourth P-channel MOSFET 404 and the drains of the third and fourth N-channel MOSFETs 407 and 408 are both the third.
Of the first and second NPN bipolar transistors 409, 409,
The collectors of 410 are both connected to the power supply line,
And resistance of N-channel MOSFETs 405 to 408
The other ends of 412 are both grounded. Here, both the first input point 413 and the second input point 414 are positive logic input points.

The operation of the semiconductor integrated circuit shown in FIG. 4 will be described below. When both the first input point 413 and the second input point 414 are at "L" level, all P-channel MOS
FETs 401-404 are conductive, while all N-channel MOSFETs 405-408 are non-conductive. Therefore, since the first input point 413 is at the “L” level,
No current is supplied through the P-channel MOSFET 401 to the base of the bipolar transistor 409. Also, since the second input point 414 is also at the “L” level, NPN
No current is supplied to the base of the bipolar transistor 410 through the P-channel MOSFET 402, and the NPN
No emitter current flows in bipolar transistors 409 and 410. At this time, if there is a potential at the output point 415, NP through the P-channel MOSFETs 403 and 404
Since a current is supplied to the base of the N bipolar transistor 411, the potential at the output point 415 becomes "L" level by the NPN bipolar transistor 411. At this time,
Due to 412, the potential of the output point 415 drops to the potential of the ground line. Next, when the first input point 413 is at "L" level and the second input point 414 is at "H" level, the P-channel MO
SFETs 402 and 403 and N-channel MOSFET 40
5 and 408 become conductive while the P-channel MOSF
ET401, 404 and N-channel MOSFET 406,
407 is turned off. Therefore, since the second input point 414 is at "H" level, a current is supplied to the base of the NPN bipolar transistor 410 through the P-channel MOSFET 402, an emitter current flows, and the potential of the output point 415 is set at "H" level. And At this time,
The base of the NPN bipolar transistor 411 is cut off from the potential at the output point 415 by the P-channel MOSFET 404, and is in a conductive state with the ground line by the N-channel MOSFET 408, so that no current is supplied and the output of the NPN bipolar transistor 411 is not supplied. Point 41
5 is not dropped.

When the first input point 413 is at "H" level,
When the second input point 414 is at "L" level, the P-channel MOSFETs 401 and 404 and the channel MOSF
ET406 and 407 are conducting, while the P channel M
OSFETs 402 and 403 and N-channel MOSFET
405 and 408 are turned off. Therefore, the first input point
Since 413 is at “H” level, a P-channel MOSFET 401 is connected to the base of NPN bipolar transistor 409.
, An emitter current flows and the potential at the output point 415 is set to the "H" level. At this time, the base of the NPN bipolar transistor 411 is cut off from the potential of the output point 415 by the P-channel MOSFET 403, and the N-channel MOSFET 407 is in a conductive state with the ground line. Output point by transistor 411
415 potential is not dropped.

Further, a first input point 413 and a second input point
When both 414 are at "H" level, all N-channel MOSFETs 405 to 408 are conductive, while all P-channel MOSFETs 401 to 404 are non-conductive.
Therefore, the base of the NPN bipolar transistor 409 is connected to the first input point 413 by the P-channel MOSFET 401.
N-channel MOSFE
The current is not supplied because it is electrically connected to the ground line by T405. Further, the base of the NPN bipolar transistor 410 is also cut off from the potential of the second input point 414 by the P-channel MOSFET 402, and is electrically connected to the ground line by the N-channel MOSFET 406, so that no current is supplied. Therefore NPN
No emitter current flows in both bipolar transistors 409 and 410. At this time, if there is a potential at the output point 415, NP through the P-channel MOSFETs 403 and 404
Since a current is supplied to the base of the N bipolar transistor 411, the potential at the output point 415 becomes "L" level by the NPN bipolar transistor 411. At this time,
Due to 412, the potential of the output point 415 drops to the potential of the ground line.

Note that the exclusive OR can be negated by using either the first input point or the second input point shown in FIG. 4 as a negative logic input point. In FIG. 4, a first P-channel MOSF
A connection is made by using a fifth N-channel MOSFET in place of the ET401, and the gate of the fifth N-channel MOSFET is used alone as a third input point which receives an inverted signal of the signal input to the second input point 414 as an input. A sixth N-channel MOSFET is connected in place of the second P-channel MOSFET 402, and the gate of the sixth N-channel MOSFET is used alone to input an inverted signal of the signal input to the first input point. A similar result can be obtained by using as the fourth input point. Also, at this time, by using either the first input point or the second input point as a negative logic input point, it is possible to indicate the negation of the exclusive OR.

As described above, the semiconductor integrated circuit according to the fourth embodiment uses the bipolar CMOS circuit technology to configure the exclusive OR logic with the MOSFET and the bipolar transistor, and outputs the output section at the "H" level. Time and "L"
By adopting a configuration in which the transistor is driven by the bipolar transistor at the time of the level output, the delay time can be reduced as compared with the conventional circuit even when the load of the output unit is heavy.

FIG. 5 is a circuit diagram of a semiconductor integrated circuit according to a fifth embodiment (corresponding to claim 7) of the present invention. In FIG. 5, reference numerals 401 to 405 denote the same as those described in the fourth embodiment. Therefore, detailed description is omitted. In FIG. 5, 501
Is an inverter circuit, 502 is a P-channel MOSFET, and the output point 415 is connected to the input point of the inverter circuit 501 and the fifth point.
The output point of the inverter circuit 501 is connected to the gate of the fifth P-channel MOSFET 502, and the source of the fifth P-channel MOSFET 502 is connected to the power supply line.

The operation of the semiconductor integrated circuit shown in FIG. 5 will be described below. The operation principle of the present embodiment is basically the same as the operation of the semiconductor integrated circuit of FIG. 4 already described in the fourth embodiment, and therefore only its features will be described. When the first input point 413 is at the “L” level and the second input point 414 is at the “H” level, or
When the signal 413 is at "H" level and the second input point 414 is at "L" level, the output point 415 is at "H" level as described above. However, in the semiconductor integrated circuit of the fourth embodiment,
In this case, the “H” level potential changes from the power supply potential to NPN.
It rises only to the level lowered by the potential difference between the base and the emitter in the bipolar transistor. on the other hand,
In the semiconductor integrated circuit according to the fifth embodiment, when the output point 415 goes to a high level to some extent, the inverter circuit 501 switches the output of the low level to the P-channel MOSFET 502.
And the P-channel MOSFET 502 is rendered conductive, whereby the output point 415 rises to a potential equal to the power supply potential.

As described above, in the semiconductor integrated circuit of the fifth embodiment, the logic of the exclusive OR is constituted by the MOSFET and the bipolar transistor by using the bipolar CMOS circuit technology, and the output section is set to the "H" level output. Time and "L"
By adopting a configuration in which the transistor is driven by a bipolar transistor at the time of level output, the delay time can be reduced as compared with the conventional circuit even when the load of the output section is heavy, and the logic amplitude becomes 0 V when the power supply potential is 5 V. From 5
Since it is possible to make a full swing to V, it is hardly affected by noise or the like.

The fifth embodiment can be applied to the above-described modification described in the fourth embodiment.

[0041]

As described above, the bipolar CM of the present invention is used.
According to the semiconductor integrated circuit using the OS circuit technology, the logic is constituted by MOSFETs and bipolar transistors and the output portion is traced compared to the exclusive OR circuit constituted only by the conventional CMOS circuit technology. By employing a configuration in which a bipolar transistor that can obtain a large amount of output current by supplying a current is used, the delay time can be reduced as compared with a conventional circuit even when the load on the output unit is heavy. A second semiconductor integrated circuit;
According to the third semiconductor integrated circuit and the fifth semiconductor integrated circuit, when the power supply potential is 5 V, the logical amplitude can fully swing from 0 V to 5 V, so that the influence of noise or the like can be reduced. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional semiconductor integrated circuit.

[Explanation of symbols]

101,102,202,301 to 304,401 to 404,502 P-channel MOSFET 103,104,305 to 308,405 to 408 N-channel M
OSFET 105,106,309,409 to 411 NPN bipolar transistor 107,310,412 Resistance 108,311,413 First input point 109,312,414 Second input point 110,313,415 Output point

Claims (7)

(57) [Claims] 1. First and second P-channel MOSFETs
And first and second N-channel MOSFETs and first and second N-channel MOSFETs.
And a gate of the second P-channel MOSFET and the second P-channel MOSFET.
The gate of the N-channel MOSFET and the source of the first P-channel MOSFET are connected in common and used as a first input point, while the first P-channel MOSFET is
The gate of the SFET and the first N-channel MOSFET
The gate of T and the second P-channel MOSFET
And the drain of the first P-channel MOSFET, the drain of the first N-channel MOSFET, and the base of the first NPN bipolar transistor are connected in common. The drain of the second P-channel MOSFET, the drain of the second N-channel MOSFET and the base of the second NPN bipolar transistor are commonly connected, and the first and second N-channel MOSFETs are connected.
T are connected to the ground line, and the first and second NPs are connected.
Both collectors of the N bipolar transistor are connected to a power supply line, both emitters of the first and second NPN bipolar transistors are commonly connected to one end of the resistor, and this is set as an output point, and the other end of the resistor is connected to a ground line. And a semiconductor integrated circuit connected to the semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein a third N-channel MOSFET is connected in place of said first P-channel MOSFET, and a gate of said third N-channel MOSFET is solely connected to said third N-channel MOSFET. A third in which the inverted signal of the signal input to the second input point is input.
And the second P-channel MOSFET
A fourth input point which is connected by using a fourth N-channel MOSFET instead of T, and which has the gate of the fourth N-channel MOSFET alone as an input to an inverted signal of a signal input to the first input point. A semiconductor integrated circuit, characterized in that: 3. A semiconductor integrated circuit, an inverter circuit and a third P-channel MOSFET according to claim 1 or 2.
3. An output point of the semiconductor integrated circuit according to claim 1 or 2, and an input point of the inverter circuit and the third P
The drain of the channel MOSFET is commonly connected, and the output point of the inverter circuit is connected to the third P-channel M
A semiconductor integrated circuit connected to a gate of an OSFET and a source of the third P-channel MOSFET connected to a power supply line. 4. First to fourth P-channel MOSFETs
And a first to fourth N-channel MOSFET, an NPN bipolar transistor, and a resistor. The gate of the first P-channel MOSFET and the gate of the first N-channel MOSFET are connected to the second N-channel MOSFET.
The source of the SFET is connected in common and used as a first input point. The gate of the second P-channel MOSFET and the gate of the second N-channel MOSFET are connected to the first
Connected to the source of the N-channel MOSFET as a second input point.
OSFET drain and the first N-channel MOS
FET drain and the third P-channel MOSFET
Gate of T and said third N-channel MOSFET
Of the second P-channel MOS
FET drain and the second N-channel MOSFET
The drain of T, the gate of the fourth P-channel MOSFET and the gate of the fourth N-channel MOSFET are commonly connected, and the first to fourth P-channel MOSFETs are connected.
The source of the SFET and the collector of the NPN bipolar transistor are commonly connected to a power supply line, and the drains of the third and fourth P-channel MOSFETs and the NPN
The other end of the resistor is connected to the base of the bipolar transistor and one end of the resistor.
Commonly connected to the drain of the OSFET and the emitter of the NPN bipolar transistor, and use this as an output point;
A semiconductor integrated circuit, wherein a source of the third N-channel MOSFET is connected to a drain of the fourth N-channel MOSFET, and a source of the fourth N-channel MOSFET is connected to a ground line. 5. First to fourth P-channel MOSFETs
And first to fourth N-channel MOSFETs and first to third N-channel MOSFETs.
NPN bipolar transistor and a resistor, the source of the first P-channel MOSFET and the second
Of the second P-channel MOSFET and the gate of the second channel MOSFET, which are commonly used as a first input point.
The source of T, the gate of the first P-channel MOSFET, and the gate of the first N-channel MOSFET are commonly connected and used as a second input point, and the drain of the first P-channel MOSFET is connected to the drain of the first P-channel MOSFET. The drain of the first N-channel MOSFET, the gate of the third P-channel MOSFET, the gate of the third N-channel MOSFET, and the base of the first NPN bipolar transistor are commonly connected, and the second P-channel MOSFET is connected to the second P-channel MOSFET.
A drain of the channel MOSFET, a drain of the second N-channel MOSFET, a gate of the fourth P-channel MOSFET, and the fourth N-channel MOSFET.
The gate of the SFET and the base of the second NPN bipolar transistor are commonly connected, and both emitters of the first and second NPN bipolar transistors, the source of the third P-channel MOSFET, and the third NPN bipolar transistor Connected to one end of the resistor and one end of the resistor as an output point.
Drain of the P-channel MOSFET and the fourth P-channel MOSFET.
A drain of the fourth P-channel MOSFET and the third and fourth P-channel MOSFETs;
Drain of the N-channel MOSFET and the third
And the collectors of the first and second NPN bipolar transistors are connected to a power supply line. The sources of the first to fourth N-channel MOSFETs and the other end of the resistor are grounded. A semiconductor integrated circuit characterized by being commonly connected to a line. 6. The semiconductor integrated circuit according to claim 5, wherein a fifth N-channel MOSFET is connected instead of said first P-channel MOSFET, and a gate of said fifth N-channel MOSFET is independently provided. A third in which the inverted signal of the signal input to the second input point is input.
And the second P-channel MOSFET
A fourth input point which is connected by using a sixth N-channel MOSFET instead of T, and which receives the inverted signal of the signal input to the first input point by using the gate of the sixth N-channel MOSFET alone A semiconductor integrated circuit, characterized in that: 7. A semiconductor integrated circuit, an inverter circuit and a fifth P-channel MOSFET according to claim 5 or 6.
7. An output point of the semiconductor integrated circuit according to claim 5 or 6, which is commonly connected to an input point of the inverter circuit and a drain of the fifth P-channel MOSFET, and connects an output point of the inverter circuit to the fifth point. P-channel MOS
The fifth P-channel MO is connected to the gate of the FET.
A semiconductor integrated circuit, wherein a source of an SFET is connected to a power supply line.