JPH0527284B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular,
The present invention relates to a high speed, low power consumption semiconductor integrated circuit device comprising CMOS transistors and bipolar transistors. [Prior Art] FIG. 1 shows a conventional logic circuit using only CMOS transistors. Here, 2 input NAND
Show about. This two-input NAND circuit consists of two PMOS transistors 200, 201 connected in parallel and two NMOS transistors 202, 2 connected in series.
03. When inputs 204 and 205 are both at “1” level, NMOS transistor 2
02 and 203 are turned on, and the PMOS transistors 200 and 201 are turned off. Therefore, the output 206 is at the "0" level. input 20
When either 4 or 205 is at the “0” level, the PMOS transistor 201 or 2
Either one of 00 is turned on and NMOS
Either transistor 202 or 203 is turned off. Therefore, the output 206 is at the "1" level. As you can see from this operation, when the input level is determined to be “1” or “0” level, the power supply 2
No conductive path is created from 07 to ground.
Therefore, CMOS circuits have the advantage of low power consumption. However, the transfer conductance of MOS transistors is smaller than that of bipolar transistors, so if the load capacitance is large, charging and discharging takes time, resulting in a slow speed. FIG. 2 shows a conventional two-input NAND circuit using only bipolar transistors. This 2-input NAND circuit is a multi-emitter
NPN transistor (hereinafter abbreviated as NPN) 300,
NPN301, 302, 303, diode 30
4, and resistors 305, 306, 307, 308
It consists of When the inputs 309 and 310 are both at the "1" level, the base and emitter junctions of the NPN 300 are reverse biased, so the base current flowing through the resistor 305 becomes the base current of the NPN 301. Therefore, NPN301 is turned on, and the non-grounded terminal potential of resistor 307 rises, and NPN303
is turned on, so the output 311 becomes "0" level. Note that at this time, the potential of the terminal of the resistor 306 on the side opposite to the power supply 312 decreases, so the NPN 302 is turned off. On the other hand, when either input 309 or 310 is at the "0" level, the base of NPN300,
The emitter junction is forward biased and the base current flowing through resistor 305 is mostly at input 309 or 310.
, the NPN 300 becomes saturated.
Therefore, input 309 to the base of NPN301
Or, since the “0” level of 310 is transmitted almost as is and NPN301 is turned off, NPN30
3 is off. On the other hand, the potential of the terminal opposite to the power supply 312 of the resistor 306 increases, so the NPN302
is turned on, the emitter current of the NPN 302 charges the load, and the output 311 becomes "1" level. Bipolar transistor circuits like this allow large currents to flow into low impedance circuits,
The drawback is that it consumes a lot of power because it drains water out. Bipolar transistor circuits are also considerably inferior to CMOS circuits in terms of integration. On the other hand, it is characterized by high speed due to high transfer conductance characteristics. [Problems to be Solved by the Invention] In order to compensate for the drawbacks of the CMOS circuit and bipolar circuit described above, an inverter circuit as shown in FIG. 3 is known. This inverter is
It consists of a PMOS 50, an NMOS 51, an NPN 53, and a PNP transistor (hereinafter abbreviated as PNP) 54. When the input 55 is at the "0" level, the PMOS 50 is turned on and the NMOS 51 is turned off. Therefore
The base potential of NPN53 and PNP54 increases,
NPN53 is on and PNP54 is off,
The output 56 becomes "1" level. When input 55 is at “1” level, PMOS50 is turned off.
NMOS51 is turned on. Therefore, NPN53
The base potential of the PNP 54 decreases, the NPN 53 turns off, the PNP 54 turns on, and the output 56 becomes the "0" level. However, one of the bipolar transistors
Since the PNP 54 is used, there is a drawback that the output signal 56 falls slowly. this is,
This is because PNP has lower performance such as current amplification factor than NPN. Also, IEEE Trans Electron, Devices vol.
In Fig. 8 of ED-16, No. 11, Nov. 1969, p945-951, an inverter circuit as shown in Fig. 14 is described. This inverter circuit has 4 PMOS transistors
01, MNOS transistor 402, first NPN
It is composed of a transistor 501 and a second NPN transistor 502. In this inverter circuit, the first and second NPN
When 501 and 502 are turned off, there is no way to forcibly remove the parasitic charge accumulated in the base, so
The time it takes for the NPNs 501, 502 to switch off becomes longer. Therefore, the first and second NPN501,5
02 remain on for a long time, which not only increases power consumption but also slows down the switching time. Further, FIG. 10 of the above-mentioned document describes an inverter circuit as shown in FIG. 15. The inverter circuit of FIG. 15 has a configuration in which an NMOS transistor 403 and a PMOS transistor 404 are added to the inverter circuit of FIG. 14.
NMOS 403 is a means for forcibly extracting the parasitic charge accumulated in the base when the first NPN 501 turns from on to off, and PMOS 404 is the means for forcibly extracting the parasitic charge accumulated in the base.
This is a means for forcibly extracting the parasitic charges accumulated in the base when the NPN502 turns from on to off.Thus, it is slightly faster than the inverter circuit shown in Figure 14, but the NMOS402
Since the gates of PMOS 404 and PMOS 404 are both connected to the input IN, the input capacitance becomes large and there is a problem that the high speed of the circuit cannot be achieved. Also, PMOS
The transistor 404 is turned on when the input level is “0”, but the potential between the gate and source of the PMOS 404 at this time is equal to that of the second NPN 502.
Since it is only 1V _BE (for example, about 0.7V in the case of Si), the drain current I _D of the PMOS 404 hardly flows, and the parasitic charge accumulated in the base of the second NPN 502 is not discharged and is used in the circuit. Another problem is that high speed cannot be achieved. Further, US Pat. No. 4,301,383 describes a buffer circuit as shown in FIG. 16.
PMOS601, 603, 605, NMOS602,
604, NPN701, 702, but a PMOS
There is a second inverter circuit composed of 603 and NMOS604, and the NPN702 is driven through a two-stage inverter circuit, causing a delay and the problem that the high speed of the entire circuit cannot be achieved. has. The purpose of the present invention is to provide the above-mentioned CMOS circuit,
It is an object of the present invention to provide a high-speed, low-power semiconductor integrated circuit device comprising field effect transistors and bipolar transistors, which compensates for the drawbacks of bipolar transistor circuits. [Means for Solving the Problems] The present invention focuses on the low power consumption characteristics of CMOS circuits and the high speed characteristics of bipolar circuits, and attempts to obtain a high speed and low power consumption circuit using a composite circuit that combines both gates. That is. Therefore, it consists of a so-called totem-pole output stage in which two NPN transistors are connected in series between a power supply terminal and a ground terminal, similar to that used in TTL gates, a logic circuit consisting of a CMOS circuit, and a circuit that drives a bipolar transistor. By supplying the complementary outputs of the drive circuit to the base of the bipolar transistor of the output stage, a high input impedance, low output impedance circuit is realized.
In this case, the MOS transistor and the NPN transistor are connected in Darlington, and a large transfer conductance can be obtained. The present invention is characterized by: a first bipolar transistor having a collector, a base, and an emitter, the collector-emitter current path being connected to a first power supply terminal and an output terminal; a second bipolar transistor having a collector-emitter current path connected to the output terminal and a second power supply terminal; from the power terminal of
at least one conductivity field effect transistor forming a current path from the first power supply terminal to the base of the bipolar transistor; and at least one field effect transistor of the other conductivity type forming a current path to the base of the transistor. [Example] Hereinafter, the present invention will be explained in detail with reference to Examples. FIG. 4 shows a totem pole output type inverter circuit. In FIG. 4, 14 is a first terminal whose collector is connected to the power supply terminal 1 and whose emitter is connected to the output terminal 17.
NPN bipolar transistor (hereinafter simply referred to as the first
(referred to as NPN), 15, the collector is output terminal 1
7, a second NPN bipolar transistor (hereinafter simply referred to as second NPN) whose emitter is connected to a fixed potential terminal whose emitter is at ground potential GND; 10
is a P-type insulated gate field effect transistor (hereinafter simply referred to as PMOS) whose gate is connected to the input terminal 16 and whose source and drain are respectively connected to the collector and base of the first NPN. 11, the gate is connected to the input terminal 16, and the drain and source are connected to the second terminal
N-type insulated gate field effect transistor (hereinafter simply referred to as NPN) connected to the collector and base of NPN
NMOS), 12 and 13 are the first and second
This is a resistor installed between the base and emitter of the NPN. Table 1 shows the logical operation of FIG.

[Table] When the input 16 is at the "0" level, the PMOS 10 is turned on and the NMOS 11 is turned off. Therefore, the base potential of the first NPN 14 increases, and the base potential of the first NPN 14 increases.
NPN14 is turned on. At this time, NMOS1
1 is turned off, the current supply to the base 15 of the second NPN is stopped, and the second NPN 1 is turned off.
Since the accumulated charge accumulated in the base of NPN 5 and the NMOS 11 is extracted to the ground potential GND via the resistor 13, the second NPN 15 is rapidly turned off. Therefore, the emitter current of the first NPN 14 charges a capacitive load (not shown), and the output 17 quickly becomes the "1" level. When the input 16 is at the "1" level, the PMOS 10 is turned off and the NMOS 11 is turned on. At this time,
Since the PMOS 10 is turned off, the current supply to the base of the first NPM 14 is stopped, and the first
The accumulated charges accumulated in the base B of NPN14 and PMOS10 are transferred to the resistor 12, NMOS11, and NPN1.
5. Since it is extracted to the ground potential GND via the resistor 13, the first NPN 14 is rapidly turned off.
Also, since NMOS11 is turned on and the drain and source are short-circuited, the second NPN15
The base of the first NPN 14 is supplied with both the current from the output 17 and the current of the accumulated charges accumulated in the base of the first NPN 14 and the PMOS 10 as described above, and the second
NPN15 turns on rapidly. Therefore,
The output 17 quickly becomes the "0" level. Here, the function of the resistor 12 will be further described. As mentioned above, when the PMOS 10 and the first NPN 14 are switched from on to off, the resistor 12
The function is to extract the accumulated charge accumulated in the base of the PMOS 10 and the first NPN 14, to rapidly turn off the first NPN 14, and to supply this extracted charge to the base of the second NPN via the NMOS 11 which is turned on. It has the function of rapidly turning on the second NPN. Furthermore, resistor 12 is connected to the drain of PMOS10.
Since it is provided between the drain of the NMOS 11 and the drain of the NMOS 11, low power consumption can be achieved without creating a conductive path between the power supply terminal 1 and the ground potential GND. In other words, if the resistor 12 is provided to connect the drain of the PMOS 10 and GND,
When input 16 is at “0” level, power supply terminal 1 and
A conductive path is created between it and GND, and current always flows.
Although the power consumption increases, the configuration shown in FIG. 4 does not create a conductive path. In addition, in FIG. 4, since the resistor 12 is also connected to the output terminal 17, the input 16
When is at “0” level, PMOS10 and resistor 12
Through this, the potential of the output 17 can be raised to near the potential of the power supply terminal 1, the full amplitude of the output can be achieved, and a sufficient noise margin can be secured. Next, the function of the resistor 13 will be further described. As mentioned above, the resistor 13 connects the NMOS 11 and the second
When NPN15 switches from on to off, NMOS
11 and the base of the second NPN 15, and has the function of rapidly turning off the second NPN 15. Furthermore, in the configuration shown in FIG. 4, when the input 16 is at the "1" level, the resistor 13 and
Through the NMOS 11, the output 17 can be lowered to near the "0" level, the full amplitude of the output can be achieved, and a sufficient noise margin can be secured. Also, in Figure 4, only NPN transistors are used as bipolar transistors, so
Easy to match switching characteristics. Furthermore, in FIG. 4, since a PNP transistor with a low current amplification factor is not used, the fall of the output signal is not delayed, and high-speed operation is possible. FIG. 5 shows a 2-input NAND circuit. In FIG. 5, 26 is the first terminal whose collector is connected to the power supply terminal 1 and whose emitter is connected to the output terminal 29.
NPN, 27, the collector is connected to the output terminal 29,
A second NPN whose emitter is connected to a fixed potential terminal whose emitter is ground potential GND, 28 are two input terminals,
20 and 21, each gate is connected to a different input terminal 28, each source and each drain are connected to a first
The PMOSs 22 and 23, which are connected in parallel between the collector and base of the NPN 26, each have their gates connected to different input terminals 28, and their respective drains and sources connected between the collector and base of the second NPN 27. each connected in series
NMOS, 24 is the drain of PMOS20, 21,
A resistor 25 connects the base of the first NPN 26, the drain of the NMOS 22, and the output terminal.
This is a resistor that connects the base and emitter of NPN27. Table 2 shows the logical operation of FIG.

[Table] First, when either input 28 is at the “0” level,
Either PMOS20 or 21 turns on,
Either NMOS 22 or 23 is turned off. Therefore, the base potential of the first NPN 26 increases,
The first NPN 26 is turned on. At this time,
Since either NMOS 22 or 23 is turned off, the supply of current to the base of the second NPN 27 is stopped, and the base of the second NPN 27 and
Since the accumulated charges accumulated in the NMOS 22 and 23 are extracted, the second NPN 27 is rapidly turned off. Therefore, the emitter current of the first NPN 26 charges a capacitive load (not shown), and the output 29 quickly becomes the "1" level. When both inputs 28 are at “0” level, PMOS
Both 20 and 21 are turned on, and NMOS22,
23 are both turned off. Therefore, the operation is the same as above, and the output 29 is at the "1" level. On the other hand, when both inputs 28 are at "1" level,
Both PMOS20 and 21 are turned off, and NMOS
Both 22 and 23 are turned on. At this time,
Since PMOS20 and 21 are both turned off, the first
At the same time, the supply of current to the base of the NPN 26 is stopped, and the base of the first NPN 26 and the PMOS 20,
Since the accumulated charge accumulated in NPN 21 is extracted, first NPN 26 is rapidly turned off. Also,
Since NMOS22 and 23 are turned on and the drain and source are short-circuited, the second NPN27
The base of the current from the output 29, the base of the first NPN 26 as described above and the PMOS 20, 2
The second NPN 27 is rapidly turned on by being supplied with the current of the accumulated charges accumulated in the second NPN 27. Therefore, the output 29 quickly becomes the "0" level. Also in FIG. 5, the same effect as in FIG. 4 can be achieved. In addition, in FIG. 5, the description has been made using a 2-input NAND circuit as an example, but it can also be extended to general k-input NAND circuits (k≧2) such as 3-input NAND and 4-input NAND. Figure 6 shows a 2-input NOR circuit. In FIG. 6, 36 is a first terminal whose collector is connected to the power supply terminal 1 and whose emitter is connected to the output terminal 39.
NPN, 37, the collector is connected to the output terminal 39,
The second emitter is connected to the ground potential GND.
NPN, 38 is two input terminals, 30 and 31 are
Each gate is connected to a different input terminal 38, each source and each drain are connected in series between the collector and base of the first NPN 36.
PMOS, 32 and 33, each gate is connected to a different input terminal 38, each drain and each source is connected in parallel between the collector and base of the second NPN 37, NMOS, 34
A resistor 35 connects the drain of the PMOS 31, the drains of the NMOS 32 and 33, and the output terminal 39, and a resistor 35 connects the base and emitter of the second NPN 37. Table 3 shows the logical operation of FIG.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to configure a circuit having the high driving ability of a bipolar transistor and the low power consumption characteristic of a field effect transistor with a minimum number of stages, thereby obtaining a high speed, low power consumption semiconductor integrated circuit device. I can do it.

[Brief explanation of the drawing]

Figure 1 is a conventional CMOS circuit diagram, Figure 2 is a conventional TTL circuit diagram, Figure 3 is a conventional inverter circuit diagram, Figure 4 is an inverter circuit, and Figure 5 is a conventional TTL circuit diagram.
Input NAND circuit, Fig. 6 shows a two-input NOR circuit, Fig. 7 shows a latch circuit, Fig. 8 shows an inverter circuit, Fig. 9 shows an inverter circuit, Fig. 10 shows an inverter circuit, and Fig. 11 shows the first embodiment of the present invention. FIG. 12 shows an inverted output circuit which is a second embodiment of the present invention, FIG. 13 shows an inverted output circuit which is a third embodiment of the present invention, and FIGS. 15 and 16 show conventional inverter circuits. 10...PMOS transistor, 11,90,1
10,123...NMOS transistor, 12,1
3...Resistor, 14,15...NPN transistor, 1
00...P channel JFET, 125,126...NPN transistor with shot key barrier diode.

Claims (1)

[Claims] 1. A first bipolar transistor having a collector, a base, and an emitter, the collector being connected to a first power supply terminal, and the emitter being connected to an output terminal; a second bipolar transistor having a collector connected to the output terminal and an emitter connected to the second power supply terminal; 1 power supply terminal to the above-mentioned 1st power terminal.
at least one other conductivity type field effect transistor forming a current path from the first power supply terminal to the base of the second bipolar transistor in response to the input signal applied to the input terminal; A semiconductor integrated circuit device comprising: at least one one-side conductivity type field effect transistor forming a current path to the base of the transistor. 2. Claim 1, wherein at least one other transistor forms a current path from the output terminal to the base of the second bipolar transistor in response to the input signal applied to the input terminal. A semiconductor integrated circuit device comprising a conductive field effect transistor. 3. In claim 1, a first charge extraction element connected to the base of the first bipolar transistor and extracts accumulated charge from the base of the first bipolar transistor; A semiconductor integrated circuit device comprising: a second charge extraction element connected to a base and extracting accumulated charge from the base of the second bipolar transistor.