JPH01125022A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To execute the operation at high speed, and also, to realize low power consumption by forming a composite circuit by combining the gates of a CMOS circuit and a bipolar circuit. CONSTITUTION:The title device is formed by a totem pole type output stage in which two pieces of NPN transistors TR 14, 15 are connected in series between a power source terminal and a ground terminal, a logic circuit consisting of a CMOS circuit, and a circuit for driving TRs 10, 11 of this logic circuit. In this state, the complementary output of this driving circuit is supplied to the bases of the bipolar TRs 10, 11 of this output stage. Between an output terminal 17 and said input terminal 16, a transfer gate is formed. When the input 16 is in a '1' level, the MOSTR 10 become OFF, and same 11 becomes ON. In this case, since the MOSTR 10 becomes OFF, the supply of a current to the base of the TR 14 stops, and also, the accumulated charge accumulated in the base B of the TR 14 and the MOSTR 10 is sampled to a ground potential GND through a resistance 12, the MOSTR 11, the TR 15 and a resistance 13. Therefore, the TR 14 becomes OFF quickly, the TR 15 becomes ON quickly, and the output 17 becomes a '0' level quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to a high speed, low power consumption semiconductor integrated circuit comprising a CMOS transistor and a bipolar transistor. Regarding equipment.

[Conventional technology]

Figure 1 shows a logic circuit using only conventional CMOS transistors. Here, we show a two-man NAND circuit. This two-man NAND circuit consists of two PMOs connected in parallel.
It is composed of S transistors 200 and 201 and two NMOS transistors 202 and 203 connected in series. When both inputs 204 and 205 are at “1” level, NM
OS transistors 202 and 203 are turned on and P
MOS transistors 260 and 201 are turned off.

Therefore, the output 206 will be at the "0" level, such as 0 people or 20 people.
4 or 205 is at the "O" level, either the PMOS transistor 201 or 200 is turned on, and the NMOS transistor 202 is turned on.
Alternatively, either one of 203 is turned off. Therefore, the output 206 will be "1" level. As can be seen from this operation, if the input is determined and the bell is at the "1" or "0" level, no conductive path will be created from the power supply 207 to the ground.

Therefore, the 0M08 circuit has the feature of low power consumption. However, since the transfer conductance of MoS transistors is smaller than that of bipolar transistors, when the load capacitance is large, charging and discharging takes time, resulting in a slow speed.

FIG. 2 shows a conventional two-person NAND circuit using only bipolar transistors.

This two-person NAND circuit uses a multi-emitter NPN transistor (hereinafter abbreviated as NPN) >300°NPN301,
302, 303, diode 304, and resistor 305
, 306', 307, and 308. input 30
When both 9 and 310 are at "1" level, the base and emitter junctions of NPN300 are reverse biased, so resistor 3
The base current flowing through NPN 05 becomes the base current of NPN 301. Therefore, NPN301 is turned on and resistor 301 is turned on.
Since the non-grounded terminal potential of NPN 7 rises and the NPN 303 turns on, the output 311 becomes the "0" level. Note that at this time, the potential of the terminal of the resistor 306 on the side opposite to the power supply 312 decreases, so the NPN 302 is turned off. On the other hand, input 309,
When either of 310 is at “0” level, NPN30
0 base, emitter junction forward biased, resistor 3
The base current flowing through 05 is mostly human power 309 or 31
0, the NPN 300 becomes saturated. Therefore, input 309 or 31 to the base of NPN 301
The "ago" level of 0 is transmitted almost as is, and the NPN3
Since the signal 01 is turned off, the NPN 303 is turned off. On the other hand, since the potential of the terminal of the resistor 306 opposite to the power source 312 rises, the NPN 302 is turned on, the emitter current of the NPN 302 charges the load, and the output 311 becomes the "1" level.

Such bipolar transistor circuits have the disadvantage of high power consumption because a large current is passed into and out of the low impedance circuit. Bipolar transistor circuits are also considerably inferior to 0M08 circuits in terms of integration. On the other hand, it is characterized by high speed due to high transfer conductance characteristics.

[Problems to be Solved by the Invention] In order to compensate for the drawbacks of the 0M08 circuit and bipolar circuit described above, an inverter circuit as shown in FIG. 3 is known. This inverter is PMO350, NPN53. P
It consists of an NP transistor (hereinafter abbreviated as PN, P) 54. When the input 55 is at the "0" level, the PMO 850 is turned on and the NMO 551 is turned off. Therefore, NPN53
The base potential of the PNP 54 rises, the NPN 53 turns on, the PNP 54 turns off, and the output 56 goes to the "1" level. When input 55 is at “1” level, PMOS50
is turned off and NMOS 51 is turned on. Therefore, the base potential of PNP54 in NPN53 decreases, and NPN53
53 is turned off, PNP 54 is turned on, and the output 56 becomes "0" level. -However, since a PNP 54 is used as one of the bipolar transistors, there is a drawback that the output signal 56 falls slowly. This is because PNP has lower performance such as current amplification factor than NPN.

Also, IEf'E Trans Electron,
Devicas vol.

ED-16, &11. Nov. 1969. p945-9
In Fig. 8 of 51, an inverter circuit as shown in Fig. 14 is described.

This inverter circuit consists of PMOS transistors 401, N
MOS transistor 402. First NPN transistor 501. It is composed of a second NPN transistor 502.

In this inverter circuit, first and second NPN 501.
When the NPN 502 is turned off, there is no means to forcibly remove the parasitic charge accumulated in the base, so the NPN 501, 502
takes longer to switch off. Therefore, the first. Second
The state in which both the NPNs 501 and 502 continue to be on continues, which not only increases power consumption but also slows down the switching time.

Furthermore, in FIG. 10 of the above document, an inverter circuit as shown in FIG. 15 is described. The inverter circuit in FIG. 15 is an NMOS inverter circuit in FIG.
The configuration includes a transistor 403 and a PMOS transistor 404.

The NMO 5403 is a means for forcibly extracting the parasitic charge accumulated in the base when the first NPN 501 is turned from on to off, and the PMO 8404 is a means for removing the parasitic charge accumulated in the base when the second NPN 502 is turned from on to off. This is a means of forcibly extracting the NM
Since the gates of O3403 and PMO5404 are both connected to input 2N, the input capacitance becomes large, and there is a problem that high speed performance of the circuit cannot be obtained. Further, the PMOS transistor 404 is turned on when the input level is ((0), but the potential between the gate and source of the PMO 8404 at this time is IVaa (for example, 5i(
7) In the case of about 0.7V) (7) There is 1', so PMO
The drain current ID of 5404 hardly flows, and the drain current ID of the second N
There is also the problem that the parasitic charges accumulated on the base of the PN 502 are not discharged, making it impossible to achieve high speed circuitry.

Further, US Pat. No. 4,301,383 describes a buffer circuit as shown in FIG. 16.

PMO8601, 603, 605, NMO8602゜6
04, the circuit is composed of NPN701 and 702, but the PMOS603 and NMO86 are installed after the first inverter circuit composed of PMO8601 and NMO8602.
The second inverter circuit is composed of NPN
Since the circuit 702 is driven through a two-stage inverter circuit, a delay occurs and the high-speed performance of the entire circuit cannot be achieved.

An object of the present invention is to compensate for the drawbacks of the 0M08 circuit and the bipolar transistor circuit described above, and to provide a high-speed, low power consumption semiconductor integrated circuit device comprising a field effect transistor and a bipolar transistor.

[Means to solve the problem]

The present invention focuses on the low power consumption characteristics of the 0M08 circuit and the high speed characteristics of the bipolar circuit, and attempts to obtain a high speed and low power consumption circuit using a composite circuit that combines both gates.

Therefore, two N
It consists of a so-called totem pole type output stage in which PN transistors are connected in series between the power supply terminal and the ground terminal, a logic circuit consisting of an 0M08 circuit, and a circuit for driving a bipolar transistor, and the complementary output of the drive circuit is connected to the output stage of the bipolar transistor in the output stage. By supplying it to the base, a high input impedance, low output impedance circuit is realized.

In this case, the MOS transistor and the NPN transistor are connected in Darlington, and a large transfer conductance can be obtained.

The present invention is characterized in that a first bipolar transistor has a collector, a base, and an emitter, and a collector-emitter current path is connected to a first power supply terminal and an output terminal; a second bipolar transistor having a collector-emitter current path connected to the output terminal and a second power supply terminal; at least one conductivity type field effect transistor forming a current path from the first power supply terminal to the base of the first bipolar transistor;

at least one other conductivity type field effect transistor forming a current path from the first power supply terminal to the base of the second bipolar transistor in response to the input signal applied to the input terminal. It's about doing.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

(Embodiment 1) FIG. 4 shows a totem pole output type inverter circuit.

In FIG. 4, 14 is a first NPN bipolar transistor (hereinafter simply referred to as first NPN) whose collector is connected to the power supply terminal 1 and whose emitter is connected to the output terminal 17;
5 is a second NPN bipolar transistor (hereinafter simply referred to as the second NPN) whose collector is connected to the output terminal 17 and whose emitter is connected to a fixed potential terminal having the ground potential GND; 10 is a gate connected to the input terminal 16; , a P-type insulated gate field effect transistor (hereinafter simply referred to as PMO8) whose source and drain are respectively connected to the collector and base of the first NPN; N-type insulated gate field effect transistors (hereinafter simply referred to as NMO8), 12 and 13, connected to the collector and base of the NPN of the first.
This is a resistor provided between the base and emitter of the second NPN.

Table 1 shows the logical operation of this embodiment.

Table 1 When the human power 16 is at the 0” level, PMO3IO is turned on and NMOSII is turned off. Therefore, the first NPN1
The base potential of NPN 4 rises, and the first NPN 14 turns on. At this time, since NNO 311 is turned off, the second N
As the current supply to the base 15 of the PN is stopped, the second
Since the accumulated charge accumulated in the base of the second NPN 15 and NMOSII is extracted to the ground potential CND via the resistor 13, the second NPN 15 is quickly turned off.

Therefore, the emitter current of the first NPN 14 charges a capacitive load (not shown), and the output 17 quickly reaches the 111'' level.

When the input 16 is at the "1" level, PMO8IO is turned off and NMOSII is turned on. At this time, PMO310
is turned off, the current supply to the base of the first NPN 14 is stopped, and the accumulated charge accumulated in the base B of the first NPN 14 and PMO8IO is transferred to the resistor 12. N.M.
Ground potential GN via OSII, NPN15, and resistor 13
D, the first NPN 14 is rapidly turned off.

Also, since NMOS II is turned on and the drain and source are short-circuited, the base of the second NPN 15 receives the current from the output 17 and the first NPN 14 as described above.
The base of PMO8IO and the current of the accumulated charge accumulated in PMO8IO are both supplied, and the second NPN15 is rapidly turned on. Therefore, the output 17 quickly becomes the "O" level.

Here, the function of the resistor 12 will be further described.

As mentioned above, the resistor 12 connects PMO8IO and the first NP
When N14 switches from on to off, it extracts the charge accumulated in the base of the PMO 510 and the first NPN 14, rapidly turns off the first NPN 14, and transfers this extracted charge to the NMOS II that is turned on. through the second
It has the function of supplying the base of the second NPN to the base of the second NPN and rapidly turning on the second NPN.

Furthermore, the resistor 12 connects the drain of PMO8IO and the NMOS
Since a conductive bus is not generated between the power supply terminal 1 and the ground potential GND, low power consumption can be achieved.

In other words, if the resistor 12 is connected to the drain of PMO5IO and GN
When connected to D, input 16 is “0”
At the level, a conductive bus is created between the power supply terminal 1 and GND, and current always flows, increasing power consumption, but in this embodiment, no conductive path is created.

Further, in this embodiment, since the resistor 12 is also connected to the output terminal 17, when the input 16 is at the "0" level, the output 1 is connected via the PMO 810 and the resistor 12.
7 can be raised to near the potential of power supply terminal 1, the full amplitude of the output can be achieved, and a sufficient noise margin can be ensured.

Next, the function of the resistor 13 will be further described. As mentioned above, when NMO8II and the second NPN15 switch from on to off, the resistor 13
The resistor 13 has the function of extracting the accumulated charge accumulated at the base of the NPN 15 and rapidly turning off the second NPN 15. Further improving this embodiment, when the input 16 is at the "1" level, the resistor 13
and NMO3II, it is possible to lower the output 17 to near the at-on level, making it possible to achieve full amplitude of the output and ensure a sufficient noise margin.

Furthermore, in the fifth embodiment, since only NPN transistors are used as bipolar transistors, it is easy to match the switching characteristics.

Further, according to this embodiment, since a PNP transistor with a low current amplification factor is not used, the fall of the output signal is not delayed, and high-speed operation is possible.

(Embodiment 2) FIG. 5 shows a two-man powered NAND circuit as a second embodiment of the present invention.

In FIG. 5, 26 is a first NPN whose collector is connected to the power supply terminal 1 and whose emitter is connected to the output terminal 29;
The collector is connected to the output terminal 29, and the emitter is connected to the ground potential G.
A second NPN connected to a fixed potential terminal which is ND, 2
8 is two input terminals, 20 and 21 are PMOs 8 whose gates are respectively connected to different input terminals 28, and whose sources and drains are respectively connected in parallel between the collector and base of the first NPN 26; 22 and 23 are NMO3, 24 are PMO82, each gate is connected to a different input terminal 28, and each drain and each source are connected in series between the collector and base of the second NPN 27.
0,21 drain, first NPN26 base and NM
A resistor connecting the drain of OS 22 and the output terminal, 2
5 is a resistor connecting the base and emitter of the second NPN 27.

Table 2 shows the logical operation of this embodiment.

Table 2 First, when either input 28 is at “0” level, PMO3
Either 20 or 21 turns on, and NMO322, 2
Either one of 3 is turned off. Therefore the first NPN2
The base potential of 6 increases.

The first NPN 26 is turned on. At this time, NMO52
Since either 2 or 23 is off, the second NPN
As the current supply to the base of 27 is stopped, the second N
The second NPN 27 is quickly turned off as the accumulated charge accumulated in the base of PN 27 and NMOS 22.23 is extracted.

Therefore, the emitter current of the first NPN 26 charges a capacitive load (not shown), and the output 29 quickly becomes the "1" level.

When both inputs 28 are at “0” level, PMO820,2
1 (7) are both turned on, and both NMOs 822 and 23 are turned off. Therefore, the operation is the same as above and the output is 29
becomes “1”.

On the other hand, when both inputs 28 are at “1” level, PMO320
, 21 are both turned off, and both NMOs 822 and 23 are turned on. At this time, since both PMOs 320 and 21 are turned off, the current supply to the base of the first NPN 26 is stopped, and the base of the first NPN 26 and the PMO
Since the accumulated charges accumulated in 820 and 21 are extracted,
The first NPN 26 turns off quickly. Also, NMO8
22 and 23 are turned on, and the drain and source are short-circuited, so the output 29 is connected to the base of the second NPN 27.
The second NPN 27 is rapidly turned on by supplying both the current from the base of the first NPN 26 and the current of the accumulated charges accumulated in the PMOs 820 and 21 as described above.

Therefore, the output 29 quickly becomes the "0" level.

In this embodiment as well, the same effects as in the first embodiment can be achieved.

Although this embodiment has been described using a two-manpower NAND circuit as an example, the present invention can be applied to general input NAND circuits (k≧2) such as three-manpower NAND and four-manpower NAND.

(Embodiment 3) FIG. 6 shows a two-man power NOR circuit as a third embodiment of the present invention.

In FIG. 6, 36 is a first NPN whose collector is connected to the power supply terminal 1 and whose emitter is connected to the output terminal 39;
The collector is connected to the output terminal 39, and the emitter is connected to the ground potential G.
The second NPN 38 is connected to ND, 30 and 31 are two input terminals, each gate is connected to a different input terminal 38, each source and each drain are connected to the first NPN 36.
The PMOSs 32 and 33 connected in series between the collector and base of
NMO8 and 34, which are connected in parallel between the collector and base of N37, are connected to the drain of PMO531 and NM
A resistor connects the drains of O832, 33 and the output terminal 39, and 35 is a resistor that connects the base and emitter of the second NPN 37.

Table 3 shows the logical operation of this embodiment.

Table 3 First, when both inputs 38 are at "0" level.

Both PMO830 and 31 are turned on, and NMO332
.

33 are both turned off. Therefore, the first NPN36
The base potential of the NPN increases, and the first NPN 36 turns on. At this time, both the NMOs 832 and 33 are turned off, so the supply of current to the base of the second NPN 37 is stopped, and the base of the second NPN 37 and the NMOs 832 and 33 are turned off.
Since the accumulated charge accumulated in the second NPN
37 turns off quickly.

Therefore, the emitter current of the first NPN 36 charges a capacitive load (not shown), and the output 39 quickly becomes the "1" level.

When either input 38 is at “1” level, PMO 330
, 31 is turned off, and NMO332.

33 is turned on. At this time, PMO330
, 31 is turned off, so the first NPN3
6 stops supplying current to the base of the first N
Since the accumulated charge accumulated in either the base of PN36 or PMO830, 31 is extracted, the first NP
N36 turns off quickly. Also, NMO832,33
is turned on, and the respective drains and sources are short-circuited, so that the output 39 is connected to the base of the second NPN 37.
The second NPN 37 is rapidly turned on by supplying both the current from the base of the first NPN 36 and the current of the accumulated charge accumulated in either of the PMOs 830 and 31 as described above. Therefore, the output 39 rapidly becomes "0"
level.

When both inputs 38 are at P1'' level, PMO330,
31(7) are both turned off, and both NMO832 and 33 are turned on. Therefore, the operation is the same as above and output 3
9 becomes the 110” level.

In this embodiment as well, the same effects as in the first embodiment can be achieved.

Although this embodiment has been explained using a two-man powered NOR circuit as an example, input NOR circuits such as three-man powered NOR, four-man powered NOR, etc.
The present invention can be applied to an OR circuit (k≧2).

(Embodiment 4) FIG. 7 shows a fourth embodiment of the present invention. A latch using the inverter circuit shown in FIG. 4 in the output section is shown.

In FIG. 7, 42 is a CMOS inverter that inverts the latch pulse 401, 40 is a transfer gate that transmits the data input 400, and 43 is a CM constituting a storage section.
The OS inverter 41 is a transfer gate, and the same reference numerals as in FIG. 4 indicate the same or equivalent parts.

When latching data force 400, latch pulse 40
1 to “1”, then the transfer gate 40 becomes
It turns on, transfer gate 41 turns off, and data is written. Thereafter, when the latch pulse 401 is set to "0", the transfer gate 4o is turned off and the transfer gate 41 is turned on. Therefore, the inverter 43
Data is held by the totem pole output type inverter and transfer gate 41.

According to this embodiment, the CMO3 collapsing stage and the bipolar output stage 2
A latch circuit with the minimum stage configuration can be realized.

High speed, low power consumption, and highly integrated LSI can be realized without using a buffer circuit.

(Embodiment 5) FIG. 8 shows an inverter circuit according to a fifth embodiment of the present invention.

This embodiment is based on the resistor 12 in the first embodiment shown in FIG.
The second N-type t! This is an embodiment in which an i-edge gate field effect transistor (hereinafter simply referred to as a second NMOS; hereafter, NMO3II is referred to as a first NMo5) is replaced by 904:1. The gate of the second NMOS 90 is connected to the input terminal 16, and its drain and source are connected to the drain and source of the PMOSIO, respectively.
It is connected to the base of the second NpN'rs. The same reference numerals as in FIG. 4 indicate the same or equivalent parts. The operation is almost the same as in FIG. 4.

The difference from the first embodiment in FIG. 4 is that when the first NPNI 4 is turned off, that is, when the input 16 is at "1" level, the second
This is the point at which the NMOS 90 turns on and extracts the stored charge in the first NPNI4 and PMOSIO. In Fig. 4, the resistor 12 has this function, but in this embodiment, the resistor 12
By connecting the source of the NMOS 90 to the base of the second NPNI 5, the base current is further increased to speed up the turn-on of the second NPNI 5 from off to on.

Furthermore, in the first embodiment shown in FIG.
When switching from off to on, a current also flows through the resistor 12 and is shunted, causing a delay in the rise of the base potential of the first NPNI 4 and a slight delay in switching the first NPNI 4 from off to on. In this embodiment, when the PMOSIO is switched from off to on, the second NMOS 90 is switched from on to off, and no current flows between the drain and source of the second NMOS 90, so no current flows. , the first NPN
The base potential of I4 rises faster than in the first embodiment, and the base potential of I4 increases faster than in the first embodiment.
NPNI4 can turn on from off more quickly.

According to this embodiment, by replacing the resistor 12 with the second NMOS 90, it is possible to improve the degree of integration and increase the speed.
Higher speeds can be achieved by connecting to the base of

(Embodiment 6) FIG. 9 shows an inverter circuit according to a sixth embodiment of the present invention.

This embodiment is based on the resistor 13 in the fifth embodiment shown in FIG.
is a second P-type field-effect transistor, a P-type channel junction field-effect transistor (hereinafter abbreviated as PJFET) 1
This is an example of replacing it with 00.

The gate of PJFETloo is connected to the input terminal 16, and the source and drain are connected to the base and emitter of the second NPN, respectively.

In FIG. 9, the same reference numerals as in FIGS. 4 and 8 indicate the same or equivalent parts.

The difference from Embodiment 5 in FIG. 8 is that when the second NPNI 5 turns from on to off, that is, when the input 16 changes from LL 171 to the ``O'' level, the accumulated charge of the second NPNI 5 is transferred through PJFETloo. When the accumulated charge is extracted, the on-resistance of PJFETloo becomes small, and the second NPNI 5 is quickly turned off.

Also, when the input 16 changes from "O" to "1" level, PJFETloo turns from on to off, and the second NPN
Since the base supply current to 15 is not shunted, the second NP
NI5 goes from off to on quickly.

This embodiment has the effect of further increasing speed.

(Embodiment 7) FIG. 10 shows an inverter circuit according to a seventh embodiment of the present invention.

This example is an example in which the resistor 13 in Example 5 shown in FIG.
The same reference numerals as in FIG. 8 and FIG. 8 indicate the same or equivalent parts.
connected to the base and emitter of.

The difference from Embodiment 5 in FIG.
level, the second NPN15 and the first NMO8II
This is the point where the accumulated charge is extracted through the third NMOS IIO. When the input 16 is at “0” level, the first NPN
14 is applied to the gate of the third NMOS II in response to this base signal.
O is turned on, a current flows between the drain and source of NMOSIIO, short-circuits between the base and emitter of the second NPN 15, and extracts the accumulated charge at a higher speed.

According to this embodiment, since no resistor is used, there is an effect that higher integration can be achieved.

Further, unlike the conventional example shown in FIG. 15, the gate of NMOS IIO is not connected to the input, so the input capacitance is small and the speed of one circuit can be increased.

In FIGS. 8, 9, and 10, the inverter circuit was explained as a modification of FIG. 4, but the large-power N
Application to AND, multi-input NOR circuits such as those shown in FIG. 6, latch circuits shown in FIG. 7, etc. is also possible.

Although the logic circuit used in the LSI has been described above, the present invention can also be applied to an output circuit that outputs the output of the LSI to the outside. The three examples shown in FIG. 11, FIG. 12, and FIG. 13 are inverter circuits, but the present invention can also be applied to a large-power NAND circuit or a large-power NOR circuit.

(Embodiment 8) FIG. 11 has almost the same configuration as FIG. 8, and operates in the same way.

In Fig. 11, the same reference numerals as in Fig. 8 indicate the same or equivalent parts, and 125 is a Schottky barrier diode provided between the base and collector of the first NPH as shown in Fig. 8, etc. , 126 is the one in which a Schottky barrier diode is provided between the base and collector of the second NPN, 12
3 is a fourth N-type field effect transistor (hereinafter simply ↓;
(referred to as the fourth NMO8).

The first difference from Example 5 in FIG. 8 is that NPN125 and 12
6 is equipped with a Schottky barrier diode. This is to shorten the time required to draw out the accumulated charge generated when the NPN transistor becomes saturated.

The second difference is that the fourth NMO 512'3 is connected to the power source and the second
Install between the bases of NPN126 and connect the gate to input 16
It is to connect with.

In the case of an output circuit, this is the output low level voltage Vob
Since it is necessary to input a sink current Io at input 1
This is because it is necessary to keep current flowing through the base of the second NPN 126 when NPN 6 is at the 1'' level.

According to this embodiment, a high speed, low power consumption output circuit can be realized.

(Embodiment 9) FIG. 12 has almost the same configuration and operation as Embodiment 6 shown in FIG. In FIG. 12, the same reference numerals as in FIGS. 9 and 11 indicate the same or equivalent parts, and the resistor 13 in FIG.
is replaced with PJFETloo as in FIG. 9. The difference from FIG. 9 is that the first and second NPNs 125 and 126 are equipped with Schottky barrier diodes, and a fourth NMO 8123 is installed to supply the base current of the second NPN 126, as in Example 8. According to this embodiment, an even faster output circuit can be realized.

(Embodiment 10) FIG. 13 has almost the same configuration and operation as FIG. 10. In FIG. 13, the same reference numerals as in FIGS. 10 and 11 indicate the same or equivalent parts, and the resistor 13 in FIG.
It was replaced with MO8110. The difference from FIG. 10 is that the first and second NPN 125,
126 with a Schottky barrier diode,
Fourth NMO for base current supply of second NPN 126
5123 was installed. According to this embodiment, an even more highly integrated output circuit can be realized.

〔Effect of the invention〕

As described above, according to the present invention, a circuit having the high driving ability of a bipolar transistor and the low power consumption characteristic of a field effect transistor is constructed with a minimum number of stages, and a high speed, low power consumption semi-sensor integrated circuit device can be realized. Obtainable.

[Brief explanation of the drawing]

Figure 1 is the conventional CMO3 circuit diagram, Figure 2 is the conventional TTL
Circuit diagram, Figure 3 is a conventional inverter circuit diagram, Figure 4
The figure shows an inverter circuit according to the first embodiment of the present invention, and a fifth embodiment of the inverter circuit.
The figure shows a two-person NAND circuit which is a second embodiment of the present invention.
FIG. 6 shows a two-man NOR circuit according to the third embodiment of the invention, FIG. 7 shows a latch circuit according to the fourth embodiment of the invention, and FIG. 8 shows a fifth embodiment of the invention. An inverter circuit, FIG. 9 shows an inverter circuit according to a sixth embodiment of the present invention, and FIG. 10 shows an inverter circuit according to a seventh embodiment of the present invention.
FIG. 11 shows an inverting output circuit according to an eighth embodiment of the present invention,
FIG. 12 shows an inverting output circuit according to a ninth embodiment of the present invention,
FIG. 13 shows an inverting output circuit according to a tenth embodiment of the present invention, and FIGS. 14, 15, and 16 show conventional inverter circuits. 10...PMOS transistor, 11, 90, 110
゜123...NMo5 transistor, 12.13...
・Resistance, 14.15...NPN)-ransistor, 10
0...P-channel JFET, 125,126...NPN transistor with Schottky barrier diode. 1st mouth 3rd (21st mouth 4th mouth 5th mouth 7th mouth 81st!] ? Secret 10th /I mouth. 12 mouth 74th mouth 75th!!1 early /6 mouth

Claims (1)

[Claims] 1. It has a collector, a base, and an emitter;
a first bipolar transistor having an emitter current path connected to a first power supply terminal and an output terminal; a collector, a base, and an emitter; and a collector-emitter current path connected to the output terminal and a second power supply terminal. a second bipolar transistor connected to the base of the first bipolar transistor; one conductivity type field effect transistor; and at least one other conductivity type forming a current path from the output terminal to the base of the second bipolar transistor in response to the input signal applied to the input terminal. a field effect transistor; a first charge extraction element connected to the base of the first bipolar transistor and extracting accumulated charge from the base of the first bipolar transistor; connected to the base of the second bipolar transistor; A semiconductor integrated circuit device comprising: a second charge extraction element that extracts accumulated charge from the base of the second bipolar transistor; and a transfer gate connected between the output terminal and the input terminal. . 2. The semiconductor integrated circuit device according to claim 1, further comprising a CMOS logic circuit connected between the transfer gate and the input terminal.