JPH0722720Y2 - Data storage time switching device for digital recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a digital recording apparatus for recording an audio signal by converting an analog signal into a digital signal and storing the digital signal in a memory. The present invention relates to a data storage time switching device for a digital recording device, which is configured to switch the time of voice signal data that can be stored in a memory by changing the frequency.

(B) Conventional Technology A digital recording apparatus is known which records an audio signal by converting an analog signal into a digital signal and storing the digital signal in a memory. As the digital recording device, one using an AD conversion circuit of a pulse code modulation (PCM) system or a delta modulation (DM) system is known. The PCM method is expensive but has excellent characteristics. The DM method sacrifices the characteristics to some extent, but the cost can be significantly reduced compared to the PCM method.

By the way, as a digital recording device, for example, the magazine "Nikkei Electronics June 2, 1986, P.94-P.95"
There is known a tape recorder such as the one shown in FIG. 1 which is provided with a data storage time switching device configured to change the sampling frequency and switch the time of audio signal data which can be stored in the RAM. The adaptive delta modulation (ADM) method shown in the above-mentioned magazine sufficiently shortens the sampling period so that the change width of the signal level becomes small, and keeps the quantization width constant, and outputs a 1-bit signal "0" only in the change direction. It is a modification of the DM method represented by "1" or "1". The value of the quantization width is increased when "0" or "1" is continuously changed rapidly, and "0" and "1" are alternated. The noise is reduced by making the quantization width smaller on the contrary when there is a gradual change.

As the A / D / D-A conversion circuit, there is known an IC conversion circuit as shown in the above-mentioned magazine. The IC of the A / D / D-A conversion circuit has a terminal for controlling the switching of the sampling frequency, and a single frequency generated from the clock generation circuit by changing the signal level applied to the terminal. There is a method in which the sampling frequency is switched by the clock signal and the time of the audio signal data that can be stored in the RAM is switched.

(C) Problems to be Solved by the Invention By the way, recently, a sound field reproducing device called a surround, which seeks to have a realistic sound in a movie theater or a concert hall at home, has become popular. The sound field reproducing device is provided with a delay circuit for delaying an audio signal to obtain a realistic sensation. As the delay circuit, there are about five kinds of sound fields so that sound fields in various halls can be reproduced. Although the delay time can be set, the digital recording apparatus described above can be switched to only a few kinds of audio signal data time which can be stored in the RAM, so that the digital recording apparatus can be used. It was insufficient for use as the delay circuit.

The present invention is intended to provide a digital recording apparatus made in view of the above points.

(D) Means for solving the problem The present invention is a reset in which a clock signal generated by a clock generation circuit is used as a clock input. D with set input
type. A flip-flop and an analog signal are converted into a digital signal to temporarily store the voice signal data in the memory, and the voice signal data stored in the memory is read to convert the voice signal data into the analog signal again,
And the D type. An A / D / D-A conversion circuit in which a sampling frequency is switched according to the frequency of a pulse signal output from a flip-flop; A first conversion circuit for converting the flip-flop to operate as an inverter or a buffer; Toggle flip-flop. And a second conversion circuit for converting so as to operate as a flip-flop.

(E) Operation The present invention selectively operates the first and second conversion circuits to operate the D type. Flip-flops as inverters or buffers, or toggles. By operating as a flip-flop, the D type. The frequency of the pulse signal output from the flip-flop is changed to change the sampling frequency of the A / D / D-A conversion circuit, and the time of the audio signal data that can be stored in the memory is switched.

(F) Embodiment FIG. 1 shows an embodiment of the present invention in which a digital recording device is used as a delay circuit. ( 1 ) is a crystal oscillator (2), an inverter (3), and the inverter (3). A clock generation circuit comprising a bias resistor (4), an overtone oscillation preventing capacitor (5) and (6), wherein the crystal oscillator (2) positively feeds back an output of a predetermined frequency of the inverter (3), It is composed of a crystal oscillation circuit that oscillates a crystal.

(7) is a D type with a reset set (RS) input which uses a clock signal generated from the clock generation circuit ( 1 ) via a buffer (8) as a clock (CK) input.
It is a flip-flop (D-FF), and the output is input to the D input terminal.

(9) converts the analog audio signal input to the input terminal (10) into digital audio signal data and RA
A composed of an ADM IC that stores the audio signal data in M (11) and reads the audio signal data stored in the RAM (11), converts it again into an analog audio signal and outputs it to the output terminal (12) A D / D-A conversion circuit, which centrally controls the A-D / D-A conversion circuit (9) and sets the sampling frequency according to the frequency of the pulse signal input to the control terminal (9a). Bits of audio signal data which are provided with a control means (13) and which are stored in the RAM (11) according to the terminals to which the "H" level signals of the first to third switching terminals (9b) to (9d) are input. When the clock signal of a predetermined frequency generated from the clock generation circuit ( 1 ) is input to the control terminal (9a) as it is by switching the number or the cycle to switch the time, "H" is input to the first switching terminal (9b). The shortest time is the first when a level signal is input. When the "H" level signal is input to the second switching terminal (9c) for the audio signal data for the time, the audio signal data for the second time of the intermediate time is input to the third switching terminal (9d). Storage time switching for giving a control signal to the control means (13) to instruct the RAM (11) to store the audio signal data for the third time, which is the longest time when the "H" level signal is input. Means (14) are provided.

(15) to (19) are first to fifth LEDs for displaying the delay time, and (20) to (24) are first to fifth LEDs for driving the first to fifth LEDs (15) to (19), respectively. The first to fifth driving transistors, (25) to (29) are first to fifth switches for controlling the first to fifth driving transistors (20) to (24) and setting a delay time, respectively.
One end of the first switch (25) is connected to the first switching terminal (9b) of the AD / DA conversion circuit (9) through the diode (30), and the second and fourth switches (26) ) And (28)
Has one end connected to the second switching terminal (9c) of the A / D / D-A conversion circuit (9) via the diodes (31) and (32), respectively, and the third and fifth switches (27) and One end of (29) is connected to diode A through diodes (32) and (34), respectively.
It is connected to the third switching terminal (9d) of the -D / DA conversion circuit (9).

( 35 ) is the first resistor (3 for inputting the clock signal output from the buffer (8) to the R input terminal of D-FF (7).
6) and the power supply voltage (+ B) to the S-input terminal of D-FF (7)
A first conversion circuit composed of a second resistor (37) for applying a voltage, ( 38 ) is a first diode (39) whose anode is connected to the R input terminal of D-FF (7), and D -The second diode (4
0) and the first and second diodes (39) and (40)
A grounded-emitter control transistor (41) having a collector connected to each cathode of, and a cathode connected to the base of the control transistor (41) through a base resistor (42) and a fourth and Fifth
It is a second conversion circuit composed of third and fourth diodes (43) and (44) having anodes connected to one ends of switches (28) and (29).

When any one of the first to fifth switches (25) to (29) is operated, A-
First to third switching terminals (9b) of the D / D-A conversion circuit (9)
Since the "H" level signal is applied to any one of (9d) to (9d), the storage time switching means (14) of the AD / D-A conversion circuit (9) is applied with the "H" level signal. The time of the audio signal data stored in the RAM (11) is switched by the control means (13) according to the terminal.

By the way, the time of the audio signal data stored in the RAM (11) also changes depending on the sampling frequency of the A / D / D-A conversion circuit (9), and the sampling frequency is input to the control terminal (9a). The frequency of the pulse signal is changed according to the frequency of the pulse signal to be generated. The frequency of the pulse signal is the same as when the first to third switches (25) to (27) are operated and the fourth and fifth switches (28) and (29). It is different when you operate.

That is, the clock signal generated from the clock generation circuit ( 1 ) is passed through the buffer (8) to the CK of the D-FF (7).
Input to the input terminal or R input terminal, the first, second or third switch (25), (26) or (27)
When is operated, since the control transistor (41) is off, the S-input terminal of D-FF (7) is set to "H" level. Therefore, the D-FF (7) operates as an inverter in which the clock signal input to the R input terminal is inverted and directly output from the output.

On the other hand, the fourth or fifth switch (28) or (29)
Is operated, the power supply voltage (+ B) is applied to one end of the base resistor (42) through the operated switch and the third or fourth diode (43) or (44). 41) turns on. Therefore, D-
Both the R and S input terminals of FF (7) become "L" level. Since the output is input to the D input terminal of the D-FF (7), the D-FF (7) is
It operates as a toggle flip-flop (T-FF) whose output is alternately inverted at the rising (or falling) of the clock signal input to the CK input terminal.

Therefore, when the D-FF (7) operates as an inverter, the clock signal of the predetermined frequency generated from the clock generation circuit ( 1 ) is used as a pulse signal of the same frequency as the A-D / D-A conversion circuit (9). When the D-FF (7) operates as T-FF, the clock signal of a predetermined frequency generated from the clock generation circuit ( 1 ) is divided into 1/2. The generated pulse signal is input to the control terminal (9a).

Next, a specific description will be given.

Now, for example, when the second switch (26) is closed, the power supply voltage (+ B) passes through the second switch (26) and the diode (31), and the power of the A-D / D-A conversion circuit (9) Since it is applied to the two switching terminals (9c), the storage time switching means (14) operates in response to it, and the control means (13) causes the A-
The D / D-A conversion circuit (9) stores the audio signal data for a predetermined time in the RAM (11). On the other hand, when the second switch (26) is operated, the control transistor (41) is off, so the D-FF (7) operates as an inverter. Therefore, the control terminal (9a) of the A / D / D-A conversion circuit (9) receives the clock signal of a predetermined frequency generated from the clock generation circuit ( 1 ) at the same frequency as the control signal. By the means (13), the AD / DA conversion circuit (9) sequentially converts the audio signal input to the input terminal (10) into digital audio signal data, and the audio signal data is converted in the order of conversion. RAM (11) for the second time sequentially
Then, the analog voice signal is restored and output from the output terminal (12). Therefore, the output terminal (1
The audio signal output from 2) is output later than the audio signal not passing through the A / D / D-A conversion circuit (9) by the second time. When the second switch (26) is operated, the second drive transistor (21) is turned on, so that the second LED (1
6) lights up, and it is displayed that the delay for the second time is being performed.

In addition, for example, when the fourth switch (28) is closed, the power supply voltage (+ B) passes through the fourth switch (28) and the diode (33), and the power of the A-D / D-A conversion circuit (9) Since it is applied to the two switching terminals (9c), the storage time switching means (14) operates in response to it, and the control means (13) causes the A-
The D / D-A conversion circuit (9) stores the audio signal data for a predetermined time in the RAM (11). On the other hand, when the fourth switch (28) is operated, the power supply voltage (+ B) changes the fourth switch (28), the third diode (43) and the base resistance (4).
Since it is applied to the base of the control transistor (41) via 2), the control transistor (41) is turned on and the D-FF
(7) operates as T-FF. Therefore, A-D / D-A
At the control terminal (9a) of the conversion circuit (9), a clock signal of a predetermined frequency generated from the clock generation circuit ( 1 ) is halved.
Since the frequency is divided and input, the control means (13) outputs the A-
The D / D-A conversion circuit (9) stores in the RAM (11) the audio signal data for the fourth time which is twice the second time described above. Therefore, the audio signal output from the output terminal (12) is output after a delay of the fourth time from the audio signal that does not pass through the AD / DA conversion circuit (9). Also,
When the fourth switch (28) is operated, the fourth drive transistor (23) is turned on, so that the fourth LED (18) is turned on and it is displayed that the delay of the fourth time is being performed.

When the fifth switch (29) is closed, A-D / D-
The third switching terminal (9d) of the A conversion circuit (9) becomes "H" level, and the storage time switching means (14) operates as the third switch (27).
Performs the same operation as when the switch is closed, but when the fifth switch (29) is closed, a clock is generated at the control terminal (9a) in the same way as when the fourth switch (28) is closed. Since the clock signal of the predetermined frequency generated from the circuit ( 1 ) is frequency-divided by half and input, the control means (13) adds A-D / D
The -A conversion circuit (9) delays the audio signal by a fifth time which is twice the third time set when the third switch (27) is closed.

In the figure, D-FF (7) is an inverter or T
The time of the audio signal data stored in the RAM (11) is switched by using it as -FF.
Even if (7) is used as a buffer or T-FF, the same effect can be obtained. In that case, the D-FF
Connect the Q output terminal of (7) to the control terminal (9a) and leave other connections as they are, or buffer (8)
You may use an inverter instead of.

(G) Effect of the Invention As described above, according to the present invention, the sampling frequency of the AD / DA conversion circuit is changed, so that the time of the audio signal data that can be stored in the memory can be switched. Yes, in that case, reset to change the sampling frequency. D type with set input. Since a flip-flop is used to change the clock signal generated from a single clock generation circuit, a single oscillator is sufficient,
Beats do not occur and adversely affect peripheral circuits.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. Description of main figure numbers ( 1 ) …… Clock generator, (7) …… D type flip-flop, (9) …… AD / DA converter, (1
1) RAM, (13) control means, (14) storage time switching means, ( 35 ) first conversion circuit, ( 38 ) second conversion circuit.

Claims (1)

[Scope of utility model registration request] 1. In a digital recording apparatus for recording a voice signal by using a memory by converting an analog signal into a digital signal, a clock generating circuit for generating a clock signal and a clock signal generated by the clock generating circuit are provided. A D-type flip-flop with a reset set input, which is used as a clock input and selectively uses the clock signal as a reset input, and whose output is connected to the D input terminal, and an analog signal into a digital signal. The converted voice signal data is once stored in the memory, the voice signal data stored in the memory is read, and the voice data is converted into an analog signal again.
An A-D / D-A conversion circuit whose sampling frequency is switched according to the frequency of the pulse signal output from the D-type flip-flop and a set input of the D-type flip-flop are set to "H" level. A first conversion circuit for converting the D-type flip-flop so that it operates as an inverter or a buffer by setting a clock signal generated from the clock generation circuit to a reset input, and the D-type flip-flop. Second, converting the D-type flip-flop to operate as a toggle flip-flop by setting the set input of the above to "L" level and setting the reset input so that the clock signal generated from the clock generating circuit is not input. A conversion circuit for selectively operating the first and second conversion circuits. Data storage time switching apparatus in a digital recording device, characterized in that the manner switching the time of the audio signal data can be stored in the memory by switching the frequency of the allowed by the pulse signal outputted from the D-type flip-flop.