JPH0722415B2 - Burst phase comparison circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst phase comparison circuit, and more particularly to a burst phase comparison circuit suitable for use as an IC for use in a time base collector of a video disc player.

[Prior Art] Conventionally, there is a burst phase comparison circuit used in a time base collector of a video disc player as shown in FIG.

The composite video signal is input to the horizontal sync separation circuit 10 to separate the horizontal sync signal, and the horizontal sync signal is input to the burst gate timer 12 to output the timer signal for a predetermined fixed period in the burst signal ( (See FIG. 6).

Further, this timer signal is input to the sample & hold timer 14 and a sampling pulse is output at a predetermined timing near the end of the timer signal output.

The timer signal is output to the burst gate circuit 16 so that the gate is closed only while the timer signal is being input, and the burst signal is extracted from the composite video signal.

This burst signal is amplified by the burst amplifier 18 and then phase-compared by the phase comparator 20 (EX-OR or the like) with the ref signal which is the reference pulse signal.

The phase difference pulse output from the phase difference comparator 20 is the capacitor C.
After being integrated by, the sampling and holding circuit 22 samples and holds in accordance with the sampling pulse and outputs as a phase difference detection signal.

[Problems to be Solved by the Invention]

However, in such a conventional technique, when the timer signal output ends and the burst signal is not input to the phase comparator 20, the phase comparator 20 no longer outputs an accurate phase difference pulse.

Therefore, in order to obtain a sufficient comparison gain, the integrating capacitor C
Is required to be sampled and held, and another holding capacitor C'is required.

Capacitors are difficult to build in ICs, and external connection terminals must be provided to form an external structure, which increases the manufacturing cost of ICs and the assembly cost of parts including ICs, and also makes it difficult to increase the degree of integration of ICs. there were.

The present invention has been made in view of the above-described problems of the conventional art, and an object thereof is to provide a burst phase comparison circuit which can be formed by reducing analog elements.

[Means for Solving the Problems]

The burst phase comparison circuit according to the present invention compares the phase of a binarized burst signal with a reference pulse signal and outputs a phase difference pulse signal whose duty ratio changes according to the phase difference, and a horizontal synchronization signal. A first timer circuit that outputs a first timer signal for a certain period from a predetermined time point after the start of the horizontal synchronization signal to a predetermined time point in the middle of the burst signal, and the first timer circuit based on the first timer signal. A second timer signal is output for a certain period from the end time of the timer signal of 1 to a predetermined time before the end of the burst signal
Of the phase difference pulse signal from the timer circuit and the phase comparator, and the first timer circuit outputs the first timer signal in the phase difference pulse signal, the H level (or the L level) And keep at least the second period for other periods.
Gate circuit that outputs a pulse signal in which the phase difference pulse signal input from the phase comparator remains unchanged during the period in which the second timer signal is outputting the second timer signal, and the first timer circuit is the first timer signal. Is output, and while the second timer circuit is outputting the second timer signal, the phase difference pulse signal input from the gate circuit is output as it is, and the output is in a high impedance state during other periods. While the first tri-state buffer circuit and the first timer circuit are outputting the first timer signal, the L level (or H level) input from the outside is output as it is, and the output is high during the other period. The output of the second tri-state buffer circuit that is in the impedance state, the outputs of the first tri-state buffer circuit and the second tri-state buffer circuit are added, then integrated, and the phase ratio It is characterized in that an addition-integrating circuit for outputting a signal.

Further, in another burst phase comparison circuit according to the present invention,
A phase comparator that compares the phase of the binarized burst signal and the reference pulse signal, and outputs a phase difference pulse signal whose duty ratio changes according to the phase difference, and a predetermined value after the horizontal synchronization signal starts based on the horizontal synchronization signal. A first timer circuit that outputs a first timer signal for a certain period from a time point to a predetermined time point in the middle of the burst signal, and a burst signal from the end time point of the first timer signal based on the first timer signal. The second timer circuit that outputs the second timer signal and the phase difference pulse signal from the phase comparator are input for a certain period until a predetermined time point before the end, and the first timer circuit outputs the first timer signal. The second timer circuit is in the second
Other than the period during which the timer signal is being output is held at H level (or L level), and is kept at L level (or H level) during the period when the first timer circuit is outputting the first timer signal. , A phase comparison with a first gate circuit that outputs a first pulse signal that remains the phase difference pulse signal input from the phase comparator while the second timer circuit is outputting the second timer signal, Input the phase difference pulse signal from the device, and set H during periods other than the period during which the first timer circuit is outputting the first timer signal and the period during which the second timer circuit is outputting the second timer signal. Level (or L level)
And is held at L level (or H level) while the first timer circuit is outputting the first timer signal,
A second gate circuit which outputs a second pulse signal which is an inversion signal of the phase difference pulse signal input from the phase comparator during a period in which the second timer circuit outputs the second timer signal; According to the first pulse signal output from the gate circuit of, while the first pulse signal is L level (or H level), outputs the first power supply potential input from the outside,
While the first pulse signal is at H level (or L level),
According to the second pulse signal output from the first tri-state buffer circuit that sets the output to the high impedance state and the second gate circuit, while the second pulse signal is at the L level (or H level), the external A second tri-state buffer that outputs a second power supply potential different from the first power supply potential input from the device and outputs the high impedance state while the second pulse signal is at the H level (or the L level) A circuit, a first tristate buffer circuit and a second
The output of the tri-state buffer circuit is added and then integrated, and an addition / integration circuit for outputting a phase comparison signal is provided.

〔Example〕

One embodiment of the present invention will be described with reference to FIG.

FIG. 1 shows a circuit diagram of a burst phase comparison circuit according to the present invention.

A bandpass filter 32 is connected to an input terminal IN to which a composite video signal is input, and the bandpass filter 32 extracts a burst signal component of 3.58 MHz.

A waveform shaping circuit 34 is connected to the bandpass filter 32, and the burst signal is converted into a square wave at the zero cross point.

A horizontal sync separation circuit 30 is also connected to the input terminal IN to separate the horizontal sync signal from the composite video signal.

The above-mentioned components have been conventionally performed.

The output side of the horizontal sync separation circuit 30 is connected to a first timer circuit 35 including a timer 1 and a timer 2 connected in series. The timer 1 outputs a timer signal which is at "H" level for a predetermined fixed time from the start time of the horizontal synchronizing signal to the start time of the burst signal.

The timer 2 outputs the first timer signal which is at the “H” level for a predetermined constant time from the end of the timer signal output from the timer 1.

A second timer circuit 37 including the timer 3 is connected to the output side of the first timer circuit 35. The timer 3 outputs the second timer signal which is at the “H” level for a predetermined fixed time from the end of the first timer signal.

The output period of the second timer signal is in the period in which the composite video signal is a burst signal. Of course, the end time of the first timer signal is before the end time of the burst signal.

The output side of the first timer circuit 35 is a NOR circuit 36 and an inverting circuit 38.
The second timer circuit 37 connected to each input side of
The output side of is connected to the input side of the NOR circuit 36.

The output sides of the NOR circuit 36 and the inverting circuit 38 are connected to the power supply terminals of the tri-state buffers 40 and 42 by negative logic.

These tri-state buffers 40 and 42 have a function as switches, and when the output of the NOR circuit 36 or the inverting circuit 38 becomes "L" and power is applied, the input signal is output as it is, and conversely, the NOR circuit 36. Alternatively, when the output of the inverting circuit 38 becomes "H" and the power is turned off, the output side becomes a high impedance state.

The input side of the tri-state buffer 42 is grounded to the second
0V is supplied as the power supply potential.

The input side of the tri-state buffer 40 will be described later.

On the other hand, the output side of the waveform shaping circuit 34 is an EX-
It is connected to one input terminal of the OR circuit 46.

In addition, the R terminal to which the ref signal is input is connected to the other input terminal of the EX-OR circuit 46.
The phase difference pulse of the burst signal with respect to the f signal is output. Both the burst signal and the ref signal after waveform shaping are square waves with a duty ratio of 50%, and the frequency of the ref signal is set to 3.58 MHz, which is the same as the burst signal.

On the other hand, the phase difference pulse output from the EX-OR circuit 46 has twice the frequency of the burst signal during the burst signal period, and the duty ratio is 50% when the burst signal is delayed by π / 2 from the ref signal. When the phase of the burst signal lags behind that, the duty ratio increases, and when it advances, the duty ratio decreases.

Except during the burst signal period, the ref signal remains EX-OR
It is output from the circuit 46.

The output side of the EX-OR circuit 46 is connected to one input terminal of the NOR circuit 48. The other input terminal of the NOR circuit 48 is connected to the output side of the first timer circuit 35.

Therefore, the output of the NOR circuit 48 becomes "L" only while the signal of the first timer is being input, and then becomes the inversion pulse of the phase difference pulse.

The output side of the NOR circuit 48 is connected to the input side of the tristate buffer 40 via the inverting circuit 50.

Therefore, the input signal of the tri-state buffer 40 becomes "H" only during the input of the first timer signal, and thereafter becomes the same as the phase difference pulse output from the EX-OR circuit 46.

A gate circuit 51 is configured by the NOR circuit 48 and the inverting circuit 50, and is held at the H level while the first timer circuit 35 is outputting the first timer signal from the gate circuit 51, and is kept at the other level. Outputs a pulse signal in which at least the period during which the second timer circuit 37 is outputting the second timer signal remains the phase difference pulse signal input from the EX-OR circuit 46.

In addition, here, the logic "H" is + Vc as the first power supply potential.
It corresponds to c, and the logic "L" is 0 as the second power supply potential.
It corresponds to V.

The output side of the tri-state buffer 40 is connected to the PU terminal, and the PU signal is output from this terminal.

The output side of the tri-state buffer 42 is connected to the PD terminal, and the PD signal is output from this terminal.

The terminals PU and PD are connected to the integrating capacitor C via the adding resistors R1 and R2, respectively, and the PU signal and the PD signal are added by the resistors R1 and R2 and then integrated by the capacitor C.

The charging voltage of this capacitor C is an amplifier 52 for gain compensation.
Is output as a phase difference detection signal.

Here, the resistors R1 and R2 have the same resistance value, and the PU signal and the PD signal are added one to one.

Next, the operation of the above embodiment will be described with reference to the time chart of FIG.

When the horizontal sync signal of the composite video signal is input to the input terminal IN, the horizontal sync separation circuit 30 separates the horizontal sync signal and inputs it to the timer 1.

The timer 1 outputs a timer signal that becomes "H" level from the start time of the horizontal synchronizing signal to the start time of the burst signal, and the timer 2 is a first timer that continues for a predetermined fixed time from the end time of this timer signal. Output a signal.

On the other hand, the composite video signal is bandpass filtered 32
The burst signal component is separated by, and the waveform is shaped by the waveform shaping circuit 34 and output to the EX-OR circuit 46.

The EX-OR circuit 46 outputs a phase difference pulse.

Before the first timer signal is output, the second timer signal is also not output. Therefore, the output of the NOR circuit 36 and the output of the inverting circuit 40 are both at the “H” level, and the tristate Both the buffers 40 and 42 are in a high impedance state.

Therefore, before the first timer signal is output, the PU signal, PD
Both signals are in a high impedance state, and in this case, the voltage of the capacitor C does not change.

After that, when the first timer signal is output, the NOR circuit 48
Output becomes "L" and the output of the inverting circuit 50 becomes "H".
It becomes a state.

The outputs of the NOR circuit 36 and the inverting circuit 38 become "L", the tristate buffers 40 and 42 are switched on, and + Vcc and 0V on the input side are output, respectively.

Therefore, the PU signal is + Vcc and the PD signal is 0V, and the capacitor C is charged with 1/2 · Vcc with the RC time constant.

This charging continues while the first timer signal is output,
If this period is sufficiently secured, the charging voltage of the capacitor C is clamped at 1/2 Vcc.

After that, when the output of the first timer signal ends, the timer 3 outputs the second timer signal for a predetermined fixed time.

The tri-state buffer 42 becomes a high impedance state when the first timer signal ends.

On the other hand, the tri-state buffer 40 is turned on while the second timer signal is being output and outputs a binary input signal according to the phase difference pulse.

Therefore, while the PD signal is in the high impedance state,
The PU signal changes to + Vcc and 0V according to the H / L change of the phase difference pulse.

Here, when the burst signal is delayed by π / 2 with respect to the ref signal as shown in FIG. 2, the duty ratio of the phase difference pulse is
Since it is 50%, the output of tri-state buffer 40 is also + Vcc
And 0V are alternately changed at equal time intervals, and the charging voltage of the capacitor C does not change from 1 / 2Vcc.

After that, when the second timer signal ends, the output of the NOR circuit 36 becomes "H" and the tri-state buffer 40 goes into a high impedance state.

This high-impedance state continues until the first timer signal is output next, so that the charging voltage of the capacitor C is held for the same horizontal scanning period from the end of the burst signal.

The amplifier 52 outputs a phase difference detection signal corresponding to the charging voltage of the capacitor C.

In other words, it means that there is a phase difference of π / 2 when the phase difference detection signal corresponding to 1/2 Vcc is output.

If the burst signal lags behind the ref signal by π / 2 or more, the duty ratio of the phase difference pulse increases.

At this time, the ratio of the period during which the PU signal is + Vcc while the second timer signal is being output is higher than 0V, and the charging voltage of the capacitor C is clamped up.

Therefore, the capacitor C when the second timer signal ends
Is higher than 1/2 Vcc, and the amplifier 52 outputs a phase difference detection signal corresponding to this voltage.

Conversely, when the burst signal leads the ref signal by a delay of π / 2, the duty ratio of the phase difference pulse decreases.

At this time, the ratio of the period during which the PU signal is + Vcc while the second timer signal is being output becomes lower than 0V, and the charging voltage of the capacitor C decreases after being clamped.

Therefore, the capacitor C when the second timer signal ends
The charging voltage becomes lower than 1/2 Vcc, and the amplifier 52 outputs a phase difference detection signal corresponding to this voltage.

In this way, the integrated voltage of the capacitor C changes according to the phase change of the burst signal with respect to the ref signal, and the detection signal output corresponding to the phase difference is obtained from the amplifier 52.

According to this embodiment, the capacitor C is set to 1/2 V during the first timer signal output period before the phase comparison of each cycle is started.
Clamped to cc, and during the subsequent second timer signal output period, the capacitor C is + Vc according to the duty ratio of the phase difference pulse.
By alternately charging with c and 0V, and releasing the capacitor C from the power supply voltage after the end of the second timer signal, it is possible to perform both integration and sampling & hold of the phase difference pulse with one capacitor C. Since the number of capacitors required for the configuration can be reduced and the rest can be formed by digital gates to form a gate array, the IC manufacturing and IC assembly costs can be reduced and high integration can be achieved.

In the above embodiment, the PU signal side outputs + Vcc and the PD side outputs 0V during the output of the first timer signal.
On the contrary, the PU signal side may output 0V and the PD side may output + Vcc.

Next, a second embodiment of the present invention will be described with reference to FIG.

The square-wave burst signal and the ref signal are input to the EX-OR circuit 46.

The output side of the EX-OR circuit 46 is divided into two systems, one of which is connected to the AND circuit 62 via the inverting circuit 60 and the other of which is directly ANDed.
It is connected to the circuit 64.

The output side of the second timer circuit 37 is connected to the AND circuits 62 and 64.

Therefore, the AND circuit 62 outputs the inverted signal of the phase difference pulse while the second timer signal is being output, and the AND circuit 64
Outputs a phase difference pulse while the second timer signal is being output.

The output side of the AND circuit 62 is connected to the NOR circuit 66 together with the output side of the first timer circuit 35, and the output side of the NOR circuit 66 is connected to the power supply terminal of the tri-state buffer 40 in negative logic.

The output side of the AND circuit 64 is connected to the NOR circuit 68 together with the output side of the first timer circuit 35, and the output side of the NOR circuit 68 is connected to the power supply terminal of the tri-state buffer 42 in negative logic. The NOR circuit 66 outputs "L" while the first timer signal is being output, and outputs a phase difference pulse while the second timer signal is being output.

The NOR circuit 68 outputs "L" while the first timer signal is being output, and outputs the inversion signal of the phase difference pulse while the second timer signal is being output.

The inverting circuit 60, the AND circuit 62, and the NOR circuit 66 form a first gate circuit 54, and the NOR circuit 66 outputs a first pulse signal. The AND circuit 64 and the NOR circuit 68 form a second gate circuit 56, and the NOR circuit 68 outputs a second pulse signal.

The input side of the tri-state buffer 40 is connected to + Vcc as the first power supply potential, and the tri-state buffer 4
The input side of 2 is connected to the ground (0V) as the second power supply voltage.

Therefore, in the tri-state buffer 40, when the output of the NOR circuit 66 is “L” and the power is applied, it becomes + Vcc output, and conversely, when the output of the NOR circuit 66 is “H” and the power is turned off, the output side has high impedance. It becomes a state.

The output side of the tri-state buffer 40 is connected to the PU terminal, and the PU signal is output from this terminal.

Further, the tri-state buffer 42 outputs 0V when the output of the NOR circuit 68 becomes “L” and power is applied, and conversely NO
When the output of the R circuit 66 becomes "H" and the power is turned off, the output side becomes a high impedance state.

The output side of the tri-state buffer 42 is connected to the PU terminal, and the PU signal is output from this terminal.

The terminals PU and PD are connected to the integrating capacitor C via the adding resistors R1 and R2, respectively, and the PU signal and the PD signal are added by the resistors R1 and R2 and then integrated by the capacitor C.

The charging voltage of this capacitor C is an amplifier 52 for gain compensation.
Is output as a phase difference detection signal.

Here, the resistors R1 and R2 have the same resistance value, and the PU signal and the PD signal are added one to one.

Next, the operation of the above embodiment will be described with reference to the time chart of FIG.

Initially, while both the first timer signal and the second timer signal are "L", the outputs of the NOR circuits 66 and 68 are "H" and both the PU signal and the PD signal are in the high impedance state.

When the first timer signal is output, the NOR circuits 66 and 68 are in the meantime.
Both outputs become "L", the PU signal becomes + Vcc, the PD signal becomes 0V, and the capacitor C is charged to 1 / 2Vcc and clamped.

When the burst signal is input, the EX-OR circuit 46 outputs a phase difference pulse with respect to the ref signal.

After that, when the second timer signal is output, the NOR circuit 6
The phase difference pulse itself is output from 6 and the inverted pulse of the phase difference pulse is output from the NOR circuit 68.

Therefore, when the phase difference pulse is "H", the tri-state buffer 40 is in a high impedance state, and 42 turns on and outputs 0V. Conversely, when the phase difference pulse is "L", the tri-state buffer 42 is in a high impedance state. Next to
40 turns on and outputs + Vcc.

NOR circuits 66 and 68 after the second timer signal output is completed.
Both are in the "H" output state and the tri-state buffer
Both 40 and 42 are in a high impedance state.

As shown in Fig. 4, when the burst signal is delayed from the ref signal by π / 2, the PU signal and PD signal alternately go to + Vcc and 0V for the same time, and become high impedance after the end of the second timer signal. Therefore, the voltage of the capacitor C is maintained at 1/2 Vcc, the gain is adjusted by the amplifier 52, and then the phase difference detection signal is output.

In other words, it means that there is a phase difference of π / 2 when the phase difference detection signal corresponding to 1/2 Vcc is output.

If the burst signal lags behind the ref signal by π / 2 or more, the duty ratio of the phase difference pulse increases.

At this time, the ratio of + Vcc on the PU signal side becomes higher than 0V on the PD signal side while the second timer signal is being output, and the charging voltage of the capacitor C increases after being clamped.

Therefore, the capacitor C when the second timer signal ends
Is higher than 1/2 Vcc, and the amplifier 52 outputs a phase difference detection signal corresponding to this voltage.

Conversely, when the burst signal leads the ref signal by a delay of π / 2, the duty ratio of the phase difference pulse decreases.

At this time, the ratio of + Vcc on the PU signal side becomes lower than 0V on the PD signal side while the second timer signal is being output, and the charging voltage of the capacitor C drops after being clamped.

Therefore, the capacitor C when the second timer signal ends
The charging voltage becomes lower than 1/2 Vcc, and the amplifier 52 outputs a phase difference detection signal corresponding to this voltage.

In this way, the integrated voltage of the capacitor C changes according to the phase change of the burst signal with respect to the ref signal, and the detection signal output corresponding to the phase difference is obtained from the amplifier 52.

The same effects as those of the first embodiment can be obtained by the second embodiment.

〔The invention's effect〕

According to the burst phase comparison circuit of the present invention, since one capacitor can perform both the integration operation and the sampling and holding operation of the phase difference pulse signal, the number of capacitors required for the circuit configuration can be reduced, and the rest can be digital gated. Since it can be formed with a gate array,
An excellent effect that the cost of assembling the IC can be reduced and high integration can be achieved can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a burst phase comparison circuit according to one embodiment of the present invention, FIG. 2 is a time chart explaining the operation of the burst phase comparison circuit of FIG. 1, and FIG. FIG. 4 is a circuit diagram showing such a burst comparison circuit.
5 is a time chart for explaining the operation of the burst phase comparison circuit shown in FIG. 5, FIG. 5 is a circuit diagram showing an example of a conventional burst phase comparison circuit, and FIG. 6 is a time chart for explaining the operation of FIG. 35: 1st timer circuit, 36, 48, 66, 68: NOR circuit, 37: 2nd timer circuit, 38, 50, 60: Inversion circuit, 51: Gate circuit, 52: Amplifier, 54: 1st Gate circuit, 56: Second gate circuit, 62,64: AND circuit, 40,52: Tri-state buffer, R1, R2: Resistor, C: Capacitor.

Claims (2)

[Claims] 1. A phase comparator which compares the phases of a binarized burst signal and a reference pulse signal, and outputs a phase difference pulse signal whose duty ratio changes according to the phase difference, and a horizontal synchronization signal based on the horizontal synchronization signal. A fixed period from a predetermined time point after the start to a predetermined time point in the middle of the burst signal,
A first timer circuit that outputs a first timer signal; and a second timer for a certain period from the end time of the first timer signal to a predetermined time before the end of the burst signal based on the first timer signal. A second timer circuit that outputs a timer signal, and a phase difference pulse signal that is input from the phase comparator, and a period during which the first timer circuit is outputting the first timer signal in the phase difference pulse signal is A pulse that is held at the H level (or L level) and remains as a phase difference pulse signal input from the phase comparator for at least the period during which the second timer circuit is outputting the second timer signal during other periods. A gate circuit that outputs a signal, and a position that is input from the gate circuit while the first timer circuit is outputting the first timer signal and while the second timer circuit is outputting the second timer signal. Phase difference pulse signal The first tri-state buffer circuit that outputs the first timer signal while the first timer circuit is outputting the first timer signal, and the L-level input from the outside (or H level) is output as it is, and the output of the second tri-state buffer circuit that keeps the output in a high impedance state during the other period is added to the outputs of the first tri-state buffer circuit and the second tri-state buffer circuit, and then integrated. And a burst phase comparison circuit comprising: an addition / integration circuit that outputs a phase comparison signal. 2. A phase comparator that compares the phases of a binarized burst signal and a reference pulse signal and outputs a phase difference pulse signal whose duty ratio changes according to the phase difference, and a horizontal synchronization signal based on the horizontal synchronization signal. A fixed period from a predetermined time point after the start to a predetermined time point in the middle of the burst signal,
A first timer circuit that outputs a first timer signal; and a second timer for a certain period from the end time of the first timer signal to a predetermined time before the end of the burst signal based on the first timer signal. A second timer circuit that outputs a signal, and a phase difference pulse signal that is input from the phase comparator, and the first timer circuit is outputting the first timer signal except during the second timer circuit Hold the H level (or the L level) except during the period in which the timer signal 2 is output,
Is held at L level (or H level) while the second timer circuit is outputting the first timer signal, and is input from the phase comparator while the second timer circuit is outputting the second timer signal. The first gate circuit that outputs the first pulse signal that remains as the phase difference pulse signal and the phase difference pulse signal that is input from the phase comparator, and the first timer circuit outputs the first timer signal. Is kept at the H level (or L level) except the period during which the second timer circuit is outputting the second timer signal,
Is held at L level (or H level) while the second timer circuit is outputting the first timer signal, and is input from the phase comparator while the second timer circuit is outputting the second timer signal. The second pulse circuit that outputs a second pulse signal that is an inverted signal of the phase difference pulse signal and the first pulse signal that is output from the first gate circuit, and the first pulse signal is at the L level. (Or H level)
During the period, the first power supply potential input from the outside is output,
Of the second pulse signal output from the first tri-state buffer circuit and the second gate circuit, the output of which is in a high impedance state while the pulse signal of H is at the H level (or the L level). Pulse signal is L level (or H level)
The second power supply potential that is different from the first power supply potential that is input from the outside during the period is output, and the output is in the high impedance state while the second pulse signal is at the H level (or L level). And a summing / integrating circuit for adding the outputs of the first tri-state buffer circuit and the second tri-state buffer circuit, integrating the outputs, and outputting a phase comparison signal. Burst phase comparator circuit.