JPH0650909B2 - CCD readout method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a signal reading method for a CCD image pickup device, and more particularly to noise and noise generated by a floating diffusion amplifier (FDA) incorporated in the image pickup device. , The image signal is read out with low noise without being affected by the reset noise generated at the time of resetting the output diode, and the influence of the timing jitter of the image sensor driving circuit is reduced to reduce random noise and fixed pattern noise. Is.

[Prior Art] Conventionally, a correlated double sampling method has been used to remove reset noise, but since noise generated by FDA has no correlation with a signal, low frequency components are removed, but high. The frequency component remains without being removed. Also,
FDA has also attempted to reduce the high frequency components of noise by limiting the frequency characteristics, but since the sample and hold is performed in the latter stage, it is not possible to lower the band too much, and the noise should be sufficiently low. I can't.

FIG. 4 shows an example of a correlated double sampling circuit used conventionally. Here, 100 is a CCD element, 1 and 2 are amplifiers, 3 is a differential amplifier, 4 to 7 are capacitors, 8
Up to 10 are analog switches, 11 and 12 are switches 8 respectively
And 9 and 10 are drivers for driving, and 13 is a CCD read output taken out from the amplifier 3.

Here, as shown in FIG. 5, the feedthrough level of the output of the CCD device 100 is set by the switch 8 and the capacitor 5.
40 is sampled and held, and the signal level 41 of the output of the CCD element 100 is sampled and held by the switch 9 and the capacitor 6.

The output when the reset switch in the CCD device 100 is on shows the reset level 42, and when the reset switch is off, it shows the feedthrough level 40. In this case, reset noise is superimposed on the signal output. After that, in the CCD element 100, the signal charge is transferred from the transfer section to the output diode, so that the signal level 41 is indicated. At this time, no noise is generated, and therefore reset noise having exactly the same value is superimposed. Therefore, the differential amplifier 3 causes the signal levels stored in the capacitors 6 and 5, respectively.
By taking the difference between 41 and feedthrough level 40,
The conventional correlated double sampling method removes the reset noise.

As this method, as shown in FIG. 4, both a signal level and a field through level are sampled and held to obtain a difference, and a method in which the feed through level is clamped to obtain an equivalent difference is considered. And both are considered to be equivalent in principle. With this clamping method, when there is a lot of noise in the internal amplifier like the CCD image sensor, the amplifier noise is held or clamped, and the reset noise removal effect is small.

In order to remove such amplifier noise, the sixth conventional method is used.
The circuit shown in the figure was used. FIG. 6 shows a sample and hold circuit part, in which 14 is an input, 15 is an output, 16 and 17 are amplifiers, 18 is a capacitor, 19 is an analog switch, 20 is a resistor, 21 is a control signal, and 22 is an amplifier. Is.

The switch 19 and the hold capacitor 18 perform sample hold. At this time, it is conceivable that the above-mentioned amplifier noise is removed by providing a filter effect with the ON resistance of the switch 19 and the resistance component of the external resistor 20 and the time constant of the capacitor 18.

This filter effect has a noise removing effect as the time constant is longer, but on the other hand, if the time constant is too long, the feedthrough level and the signal level cannot be distinguished, and the reset noise removing effect is lost. There is an inconvenience.

[Problems to be Solved by the Invention] Therefore, the difference between the signal level and the feed-through level is obtained in advance by using an analog delay line, and only the section where the difference is correctly taken is taken out, thereby reducing the low frequency range. It is considered to remove the reset noise and pass the output through a low pass filter to remove the high frequency noise generated by the floating diffusion amplifier (FDA) in the CCD. That is, the delay means for delaying the output of the CCD image sensor by a predetermined time, the means for subtracting the signal delayed by the delay means and the CCD image sensor output, and the signal of the CCD image sensor output of the subtracted output. A means for extracting the signal component of the superimposition period of the level period and the delayed signal feed-through level period, and of the extracted signal components, the component corresponding to the signal bandwidth of the CCD image sensor is passed to extract the image signal. It is possible to construct a CCD readout circuit including a filter means.

The present applicant has already applied for this CCD readout circuit (Japanese Patent Application No. 60-30318), but since the application has not been published yet, it will be described in more detail.

FIG. 1 shows the overall configuration of the CCD read circuit described above. Here, 30 is a CCD element including FDA. 32 is a buffer amplifier which is supplied with the CCD output 43 via the capacitor 31, 33 is a delay line which is supplied with the output of the amplifier 32, and CC
The D output 43 is taken out with a delay, for example, by a time corresponding to the period of the field through level. 34 is a delay line
A differential amplifier that subtracts the output of amplifier 32 from the output of 33, 35
Is a low-pass filter to which the output of the differential amplifier 34 is supplied through a gate means composed of a resistor 36 and a switch 37,
Is an electronic switch as a gate means for taking out the output of the differential amplifier 34 only during the signal level of the CCD output 43, 38 is a buffer amplifier supplied with the output of the switch 37, 39 is a CCD read output taken out from the buffer amplifier 38. is there.

The CCD output signal 43 obtained by the buffer amplifier 32 under an output impedance of an appropriate magnitude is delayed by the delay line 33 by, for example, a feedthrough level period. Further, after the difference between the two signals 43 and 44 is obtained by the differential amplifier 34, the switch 37 is operated by the gate pulse 45 only during the period in which the feedthrough level and the signal level period overlap and the subtraction of both periods is correctly performed. The output of the differential amplifier 34 is taken out by the resistor 36 and the switch 37 by making it differential.
In this case, if the delay time of the delay circuit is selected so that the overlap of these periods is maximized, the time width of the signal of the gate output can be increased, which is advantageous in signal processing.

Although the resistor 36 and the switch 37 are used in this example, a multiplication circuit may be used instead.

By passing the above-mentioned gate output 46 through a predetermined low-pass filter 35 through a buffer amplifier 38, spike noise (high-frequency noise) can be removed, and a CCD read output 39 from which FDA reduced noise is also removed is obtained. That is,
The CCD output signal 43 contains reduced and high frequency noise in both the feedthrough level and the signal level, but the reduced noise is removed as the gate output 46, and further high frequency noise and gate The accompanying harmonics are removed by the low pass filter 35.

However, as is clear from the timing chart shown in FIG. 3, since the subtraction signal 50 has a large level change (or, even if the level is constant, it is a large value rather than zero), the gate pulse 45 is A slight change in timing 59
Even if the noise occurs, it will appear as a fluctuation in the signal output.

As described above, when the gate pulse or the CCD driving pulse has timing jitter, the gate pulse width is effectively changed to operate, which causes fixed pattern noise, and even a slight jitter is conspicuous. These timing jitters are caused by changes in the periodic waveform due to the influence of the frequency divider circuit in the drive circuit and changes in the pulse width due to fluctuations in the threshold value in the waveform shaping circuit. Is very difficult.

[Object of the Invention] Therefore, in view of the above points, an object of the present invention is to reduce the change in the signal area due to the jitter of the gate pulse supplied to the CCD readout circuit, thereby reducing the visually noticeable fixed pattern noise. To provide a method.

[Means for Solving the Problems] In order to achieve such an object, in the CCD reading method according to the present invention, a CC that repeatedly occurs in the order of a reset level period, a feedthrough level period, and a signal level period.
D delay means for delaying the output of the image pickup device by a predetermined time, means for performing a subtraction between the signal delayed by the delay means and the CCD image pickup device output, and the subtraction output
Gate means for extracting a signal component of a superimposing period of the signal level period of the output of the CCD image pickup device and the feedthrough level period of the delayed signal, and corresponding to the signal bandwidth of the CCD image pickup device among the extracted signal components The subtraction is performed by passing the component through a circuit having a filter means for extracting the image pickup signal and setting the delay time of the delay means to a time width shorter than the feedthrough period and the signal period. A period in which the output signal level is zero is formed, and the signal component in the superposition period is extracted including a part of the formed period in which the signal level is zero.

[Examples] Hereinafter, the present invention will be described in detail based on Examples.

As one embodiment of the present invention, the CCD read circuit shown in the first diagram described above is used. Therefore, each component is as described above, and the description is omitted.

FIG. 2 is a timing chart for explaining the operation of this embodiment. The operation of this embodiment will be clarified by comparing it with the timing chart shown in FIG. That is, the delay time 61 is made slightly shorter than the signal level period 60, and the subtraction signal is generated near the rising and falling edges of the gate pulse 45 (at least in the period 59 with timing jitter).
50 is always zero level 62, or equal to the voltage when the gate means is closed. This prevents the signal output from being affected even when there is timing jitter.

[Advantages of the Invention] By implementing the present invention, (a) the conventional inconvenience that a slight error in the phase of the sampling pulse or the gate pulse causes the radio wave to be clogged, resulting in a beat fringe pattern of the drive signal. Can be resolved.

(B) The visual noise appearing as periodic vertical stripes can be removed by the jump from the frequency divider circuit in the drive circuit.

(C) It is possible to prevent characteristic changes due to influences such as temperature changes and pulse phase changes at power-on.

Thus, in the present invention, it is not necessary to strictly provide a shield or a ground line for removing these visual noises, so that it is possible to realize a lightweight and inexpensive imaging device.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a CCD read circuit used for implementing the present invention, FIGS. 2 (A) to (D) are timing diagrams showing the operation of the embodiment shown in FIG. 1, and FIG. A) to (D) are timing charts for explaining inconvenience caused by not implementing the present invention, FIG. 4 is a circuit diagram showing a conventional correlated double sampling circuit, and FIGS. 5 (A) to (E) are shown in FIG. FIG. 4 is a signal waveform diagram showing the operation of FIG. 4, and FIG. 6 is a circuit diagram showing a general sample hold circuit. 30 …… CCD element, 31 …… Capacitor, 32 …… Buffer amplifier, 33 …… Delay line, 34 …… Differential amplifier, 35 …… Low pass filter, 36 …… Resistance, 37 …… Switch, 38 …… Buffer amplifier.

Claims (1)

[Claims] 1. A CC that repeatedly occurs in the order of a reset level period, a feedthrough level period, and a signal level period.
D delay means for delaying the output of the image pickup device by a predetermined time, means for subtracting between the signal delayed by the delay means and the output of the CCD image pickup device, and the subtraction output of the CCD image pickup device output Gate means for extracting a signal component of a superimposing period of the signal level period and the feedthrough level period of the delayed signal, and a component of the extracted signal component that corresponds to the signal bandwidth of the CCD image sensor is passed. A signal having a subtraction output by setting the delay time of the delay unit to a time width shorter than the feedthrough period and the signal period, while passing the signal through a circuit having a filter unit for extracting the image pickup signal. A CCD reading method, characterized in that a zero period is formed and a signal component of the superposed period is extracted including a part of the zero period formed.